JP2004164775A - Memory circuit and data readout method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption in charging or discharging of a bit line. <P>SOLUTION: Charging to the bit line is carried out by using output voltage from a potential recycling power source, and when discharging the potential of the bit line, the potential is recovered to the potential recycling power source. More specifically, an earthing wire of a storage element is made as a power clock line to be connected to the potential recycling power source, and when discharging the potential of the bit line, a recovery measures recovers the potential via the power clock line. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory circuit and a data reading method, and in particular, to a memory circuit having a circuit configuration for performing adiabatic charging for charging / discharging of bit line charges in a memory, and a data reading method for reading data from the memory circuit. About.
[0002]
[Prior art]
A conventionally known method of reading data from an EEPROM will be described for a NAND type.
[0003]
FIG. 5 shows a circuit configuration of a conventional NAND type EEPROM.
[0004]
In each memory block 20 shown in the figure, transistors 10 as storage elements are vertically connected in series from a GND line, and connected in series, and connected to bit lines BL1 and BL2. The bit lines BL1 and BL2 are connected to the shielding transistors 11 and 12, and the bit line BL1 is connected to the sense circuit 13 and the constant voltage power supply VDD14.
[0005]
It is assumed that a voltage of 0 V is applied to the word line 1 (WL1) and a voltage of Vpass is applied to the other word lines (WL2, WL3, WL4). At this time, the transistor 10b of the word line 1 (WL1) is selected, and the state of the selected transistor 10b is low impedance (current is low) in a low threshold (low Vth) state as shown in FIG. Flow), and in a high threshold (high Vth) state, the impedance becomes high (current does not flow).
[0006]
In an EEPROM, a bit line is precharged to a predetermined voltage, and a bit line voltage that changes depending on whether a current flows in a storage element is compared with a reference voltage of a dummy cell. As the sense circuit 13, a latch type circuit is used. Hereinafter, an operation example will be described in detail.
[0007]
In the conventional circuit diagram shown in FIG. 5, when precharging a bit line, a constant voltage power supply VDD14 is used. The GND line 15 is used for discharging. Hereinafter, a detailed operation example will be described with reference to FIG.
[0008]
First, from the initial state, the precharge is performed by setting the PRE 16 to High. Further, all the word lines (WL1 to WL4) are High, and at this time, all the transistors in the storage element are conducting. In FIG. 7, the potential of the bit line is indicated by BL1, and immediately rises when PRE16 becomes High. Next, the word line 1 (WL1) is set to Low. At this time, the transistor 10b for the word line 1 (WL1) is selected. It does not conduct when the selected transistor 10b has a high threshold, and conducts when it has a low threshold.
[0009]
Next, the BSS 17 is set to High, and the GND line is connected to the transistors 10b to 10e as storage elements. When the selected transistor 10b is conducting, the charge on the bit line BL1 is discharged to the GND line 15. When the selected transistor 10b is not conducting, the charge of the bit line BL1 is not discharged but remains at a high potential.
[0010]
After that, the BSS 17 is set to Low, and the connection between the GND line 15 and the transistors 10b to 10e as storage elements is cut off. Then, the word line 1 (WL1) is set to High, all the word lines (WL1, WL2, WL3, WL4) are set to High, and all the transistors of the memory cell block 20 are turned on.
[0011]
Next, by setting the sense signal S to High and taking the potential of the bit line into the sense circuit 13, it is determined whether the potential of the bit line BL1 is high or low.
[0012]
Next, the BDS is set to Low, and the bit line and the memory cell block are electrically separated. Then, selecting a new memory cell block is repeated.
[0013]
Here, the BDS is a signal for selecting which memory cell block is valid. When a word line is moved in one memory cell block, the state of the BDS does not need to be changed because the selected memory cell block does not change.
[0014]
The timing chart of the second bit line charging is the first repetition (for the above-described conventional circuit, see, for example, Non-Patent Documents 1 and 2).
[0015]
[Non-patent document 1]
Flash Memory Technology Handbook, edited by Fujio Masuoka, Science Forum 1993.
[Non-patent document 2]
Junichi Miyamoto, Koji Sakui, Shigeru Atsumi, Kuniyoshi Yoshikawa, Flash memory, Low power consumption and high speed LSI technology, edited by Takayasu Sakurai, Realize, p. 192 (1998).
[0016]
[Problems to be solved by the invention]
However, in the above conventional method, there is a problem that power consumption cannot be reduced due to charging / discharging of a bit line having a large load capacity because the bit line is precharged.
[0017]
The present invention has been made in view of the above points, and has as its object to provide a memory circuit and a data reading method capable of reducing power consumption when charging or discharging a bit line.
[0018]
[Means for Solving the Problems]
The present invention provides a bit line, a charging unit for charging the bit line, a memory cell block including storage elements connected via the bit line, a word line for driving each storage element, and a word line. Depending on the state of the selected storage element, when a current flows in the ground direction, the voltage of the bit line is reduced. When no current flows, it is determined that the voltage of the bit line is maintained. And a determination circuit to be performed,
The charging means has means for charging the bit line using an output voltage from the charge recycling power supply,
When discharging the charge of the bit line, the charge recycling power supply has a recovery unit for recovering the charge.
[0019]
Further, according to the present invention, the ground line of the storage element is a power clock line connected to a charge recycling power supply,
The recovery unit recovers the charge via the power clock line when discharging the charge on the bit line.
[0020]
Further, the present invention has means for electrically connecting the bit line and the power clock line after the voltage of the power clock reaches the peak voltage when the bit line is precharged.
[0021]
The present invention provides a bit line, a charging unit for charging the bit line, a memory cell block including storage elements connected via the bit line, a word line for driving each storage element, and a word line. Depending on the state of the selected storage element, when a current flows in the ground direction, the voltage of the bit line is reduced. When no current flows, it is determined that the voltage of the bit line is maintained. A data read method in a memory circuit having a determination circuit
Adiabatic charging of bit lines via a power clock line connected to a charge recycling power supply,
Select the word line,
Connect the power clock line and the storage element connected to the word line,
Discharging the bit line adiabatically through the power clock line, recovering the charge on the bit line,
The potential of the bit line is taken into the determination circuit, and the potential of the bit line is determined.
[0022]
As described above, according to the present invention, the ground line of the memory cell block is not connected to the ground as in the prior art, but is connected to the power clock line connected to the charge recycling power supply, and the charge / discharge to the bit line is performed. Is performed through the power clock line, the power consumption required for charging / discharging the bit line can be reduced as compared with the conventional configuration in which a constant voltage power supply is used to precharge.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0024]
FIG. 1 shows a configuration of a memory circuit according to one embodiment of the present invention.
[0025]
In the present embodiment, when precharging the bit line, a power clock line PCK22 connected to a charge recycling power supply (not shown) is used instead of the conventional VDD 14 shown in FIG. In addition, the power clock line 21 is used instead of the GND 15 of the conventional circuit, so that the electric charge can be collected. Except for this, the configuration is the same as the configuration in FIG. 5 described above. As for the charge recycling type power supply, [Japanese Patent Application No. 11-33953, a multi-phase charge recycling step-like power supply circuit] and [Shunji Nakata et al. , A low power multiplier using diabatic charging binary decision diagram circuit, Jpn. J. Appl. Phys. 39, 2305 (2000)]. This makes it possible to collect charges.
[0026]
The detailed operation will be described below with reference to FIG.
[0027]
FIG. 2 is a timing chart of the memory circuit according to the embodiment of the present invention, and FIG. 3 is a diagram for explaining an operation according to the embodiment of the present invention.
[0028]
First, from the initial state (the bit line is low) (step 101), the PRE 16 is set to high to prepare for precharge (step 103). The word lines (WL1, WL2, WL3, WL4) are all high, and all the transistors 10b, c, d, e, h, i, j, and k in the storage element are conductive. Next, the power clock line PCK22 is gradually raised, and the bit line BL1 is also raised (step 104). As shown in FIG. 2, as shown by BL1, the potential of the bit line gradually rises similarly as PCK rises.
[0029]
Next, the word line WL1 is set to Low. At this time, the transistor 10b for the word line WL1 is selected. It does not conduct when the selected transistor 10b has a high threshold, and conducts when it has a low threshold.
[0030]
Next, the BSS 17 is set to High, and the PCK line 21 is connected to the transistors 10b to 10e as storage elements (step 105). Then, the potential of the PCK line 21 is gradually reduced, and the charge of the bit line BL1 is collected (Step 106). When the transistor 10b selected here has a high threshold value, it does not conduct, and the charge of the bit line BL1 is not collected and remains at a high potential. When the selected transistor 10b has a low threshold value, the transistor 10b is turned on, and the charge of the bit line BL1 is collected through the PCK line 21 connected to the transistor 10f having the BSS 17 as an input.
[0031]
After the potential of the PKC line 21 decreases, the BSS 17 is set to Low, and the connection between the PCK line 21 and the memory cell block 20 is disconnected (step 107).
[0032]
Then, the word line WL1 is set to High, all the word lines (WL1, WL2, WL3, WL4) are set to High, and the transistors 10b, c, d, e, h, i, j, and k, which are all storage elements, are turned on. State.
[0033]
Next, by setting the sense signal S to High and taking the potential of the bit line BL1 into the sense circuit 13, it is determined whether the potential of the bit line BL1 is high or low.
[0034]
Next, the BDS line 18 is set to Low, and the bit line BL1 is electrically disconnected from the memory cell block 20. Then, selection of a new memory cell block is repeated. Here, the BDS is a signal for selecting which memory cell block is valid. When a word line is moved within one memory cell block 20, the BDS state does not need to be changed because the selected memory cell block does not change. FIG. 2 shows a timing chart in consideration of the case where the selected memory cell block changes every time.
[0035]
Next, a case where the second charging of the bit line is performed will be described. As is apparent from FIG. 2, almost the same as the first charging is repeated. The difference is that a bit line whose bit line is already charged exists with a probability of approximately １ ／ (where the probability of existence of “1” (High) and “0” (Low) is Both are considered to be 1/2).
[0036]
If the bit line has already been charged and is in a high state, the PRE 16 is set to high when the PCK is completely high, unlike the first time chart (step 102). Thereby, the bit line is charged by the peak voltage of PCK. This makes it possible to prevent the transfer of charges from the high-potential bit line to the low-potential power clock line PCK22, which is effective in terms of energy consumption.
[0037]
When the bit line is in the low state, the timing is exactly the same as that in the first time chart, and PRE is first set to high. Then, PCK is gradually raised to charge the bit line.
[0038]
By using the power clock line PCK connected to the charge recycling power supply, the energy at the time of charging / discharging can be reduced to about 1/10 or less as shown in FIG.
[0039]
In the case of the adiabatic logic, since the potential of the bit line is gradually increased / decreased, the current density can be reduced as compared with the CMOS logic, and electromigration is less likely to occur. Therefore, the wiring cross-sectional area can be reduced as compared with the CMOS logic, the load capacity of the bit line can be reduced, and the energy can be further reduced.
[0040]
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications and applications are possible within the scope of the claims. For example, it goes without saying that the present invention can be applied not only to the NAND type but also to the NOR type.
[0041]
【The invention's effect】
In the conventional method, the bit line is precharged, so that there is a problem that the power consumption for charging / discharging the bit line is large. However, according to the present invention, as described above, the precharge of the bit line Since a power clock using a charge recycling power supply is used, power consumption can be reduced to about 1/10.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a memory circuit according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an operation of a memory circuit according to one embodiment of the present invention.
FIG. 3 is a diagram for explaining an operation in one embodiment of the present invention.
FIG. 4 is a diagram showing the effect of the present invention.
FIG. 5 is a circuit diagram of a conventional NAND type EEPROM.
FIG. 6 is a diagram illustrating a state of a selected transistor.
FIG. 7 is a timing chart of a conventional memory circuit.
[Explanation of symbols]
10 Storage element (transistor)
11, 12 Shielding transistor 13 Sense circuit 14 Constant voltage power supply (VDD)
15 Ground line (GND)
16 Precharge signal (PRE)
17 Select gate signal (BSS)
18 Select gate signal (BDS)
20 memory cell block 21 power clock line (PCK)
22 Power clock line (PCK)

Claims (4)

A bit line, charging means for charging the bit line, a memory cell block including storage elements connected via the bit line, a word line for driving each storage element, and a storage selected by the word line A determination circuit connected to the bit line for determining that the voltage of the bit line decreases when a current flows in the ground direction depending on the state of the element and that the voltage of the bit line is maintained when no current flows. And a memory circuit having
The charging means has means for charging the bit line using an output voltage from a charge recycling power supply,
The memory circuit according to claim 1, further comprising: a recovery unit that recovers the electric charge to the electric charge recycling power supply when discharging the electric charge of the bit line. A ground line of the storage element is a power clock line connected to the charge recycling power supply,
The collecting means,
2. The memory circuit according to claim 1, wherein when discharging the electric charge of the bit line, the electric charge is collected through the power clock line. 2. The memory circuit according to claim 1, further comprising: means for electrically connecting the bit line and the power clock line after the voltage of the power clock reaches a peak voltage when the bit line is precharged. A bit line, charging means for charging the bit line, a memory cell block including storage elements connected via the bit line, a word line for driving each storage element, and a storage selected by the word line A determination circuit connected to the bit line for determining that the voltage of the bit line decreases when a current flows in the ground direction depending on the state of the element and that the voltage of the bit line is maintained when no current flows. In the data read method in the memory circuit having
Adiabatically charging the bit line via a power clock line connected to a charge recycling power supply,
Select the word line,
Connecting a storage element connected to the power clock line and the word line,
Discharging the bit line adiabatically through the power clock line, recovering the charge on the bit line,
A data reading method, wherein the potential of the bit line is taken into the determination circuit, and the potential of the bit line is determined.

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