JP2004164744A - Ferroelectric memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory capable of reducing a power consumption and accelerating a reading speed. <P>SOLUTION: The ferroelectric memory utilizing a ferroelectric capacitor has: a plurality of word lines WL and a plurality of bit lines BL, BLB; a plurality of memory cells MC arranged at these cross points; and a plurality of plate lines PL. The memory cell has: a ferroelectric capacitor FC in which the first terminal is connected to the plate line; a cell transistor CT which is provided between the bit line and a second terminal of the ferroelectric capacitor and is driven by the word line; and a coupling capacitor CC which is provided between the second terminal and the bit line. At the reading time, the plate line is driven without driving the word line to output the voltage change of the second terminal generated in accordance with a residual polarization direction of the ferroelectric capacitor to the bit line through the coupling capacitor. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory device using a ferroelectric capacitor, and more particularly to a ferroelectric memory device that does not require word line driving in a read operation.
[0002]
[Prior art]
A ferroelectric memory is non-volatile and capable of performing a high-speed write operation, and is therefore expected as a semiconductor non-volatile memory replacing a flash memory. A memory cell of a ferroelectric memory is composed of a cell transistor and a ferroelectric capacitor. At the time of writing, the ferroelectric capacitor is polarized in a different direction depending on a voltage direction applied to the ferroelectric capacitor. The capacitor maintains its polarization direction as remanent polarization, and reads the direction of the remanent polarization at the time of reading.
[0003]
In Patent Document 1 described later, in a read operation, a bit line is precharged to a ground potential and then put into a floating state, a word line is driven to make a cell transistor conductive, and a plate line is driven to drive a ferroelectric capacitor. The charge is output to the bit line side via the cell transistor, and a voltage difference of the bit line generated according to the charge amount is amplified by a sense amplifier. Since the amount of charge taken out of the cell varies depending on the direction of the remanent polarization, the voltage change of the bit line varies and data can be read.
[0004]
[Patent Document 1]
JP-A-2002-74939 (published on March 15, 2002)
[0005]
[Problems to be solved by the invention]
In a conventional ferroelectric memory, a word line is driven to a power supply level and a plate line is driven in a state where a ferroelectric capacitor is connected to a bit line at the time of reading. Therefore, it is necessary to drive two lines, a word line and a plate line, which increases power consumption and has the problem that reading cannot be performed at high speed. In addition, since the data in the memory cell is destroyed by driving the plate line at the time of reading, the bit line is amplified by the sense amplifier, and then the plate line is driven again to rewrite the data to the ferroelectric capacitor. I have. That is, the plate line is driven once for reading and again for rewriting. Such an operation is also undesirable because it causes an increase in power consumption, and has a problem that the read cycle is lengthened.
[0006]
Therefore, an object of the present invention is to provide a ferroelectric memory device that can reduce power consumption by driving word lines and plate lines.
[0007]
It is a further object of the present invention to provide a ferroelectric memory device capable of high-speed reading without driving a word line at the time of reading.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention is a ferroelectric memory using a ferroelectric capacitor, wherein a plurality of word lines and a plurality of bit lines are arranged at intersections thereof. The memory cell includes a plurality of memory cells and a plurality of plate lines. The memory cell includes a ferroelectric capacitor having a first terminal connected to the plate line, and a bit line and a second terminal of the ferroelectric capacitor. The semiconductor device includes a cell transistor provided therebetween and driven by a word line, and a coupling capacitor provided between the second terminal and the bit line. Then, at the time of reading, the voltage change of the second terminal generated according to the remanent polarization direction of the ferroelectric capacitor by driving the plate line without driving the word line is transmitted to the bit via the coupling capacitor. It is characterized by outputting to a line.
[0009]
According to the aspect of the present invention, since the coupling capacitor is provided in the memory cell, the voltage variation generated at the second terminal of the ferroelectric capacitor by the driving of the plate line at the time of reading without driving the word line during reading. Can be output to the bit line via the coupling capacitor. The voltage fluctuation output to the bit line is amplified and read by a sense amplifier or the like provided on the bit line. Therefore, it is not necessary to drive a word line in a read operation, and low power consumption and high-speed read can be realized.
[0010]
Further, according to the aspect of the present invention, since the word line is not driven at the time of reading, the cell transistor is kept off. Accordingly, the charge is not discharged from the ferroelectric capacitor to the bit line side when the plate line is driven, so that the stored data is not destroyed, and the plate line is driven again to rewrite data. No need to do. Thereby, power consumption can be further reduced, and there is no rewriting, so that the read cycle can be shortened.
[0011]
To achieve the above object, according to a second aspect of the present invention, in a ferroelectric memory using a ferroelectric capacitor, a plurality of word lines and a plurality of bit lines are arranged at intersections thereof. A plurality of memory cells, a plurality of plate lines, a ferroelectric capacitor having the plate lines as a first electrode, a ferroelectric layer and a second electrode, and a bit. A cell transistor provided between the first electrode and a second electrode of the ferroelectric capacitor and having the word line as a gate; and a coupling capacitor provided between the second electrode and the bit line. The ring capacitor includes a third electrode connected to the second electrode and a bit line adjacent to the third electrode.
[0012]
According to the second aspect, since the memory cell has the coupling capacitor between the second electrode of the ferroelectric capacitor and the bit line, the plate line can be read without driving the word line during reading. Can output a voltage dependent on the remanent polarization direction of the ferroelectric capacitor to the bit line. Therefore, power consumption can be reduced, and the speed of the read operation can be increased.
[0013]
In a more preferred embodiment of the second aspect, a part of the wiring connecting the second electrode of the ferroelectric capacitor and the cell transistor is made close to the bit line as a third electrode.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments, but extends to the inventions described in the claims and their equivalents.
[0015]
FIG. 1 is a circuit diagram of the ferroelectric memory according to the present embodiment. The ferroelectric memory includes a plurality of word lines WL, a plurality of bit line pairs BL and BLB, and a memory cell MC provided at the intersection of the word lines WL and the bit lines BL. FIG. 1 shows one memory cell MC, and shows one word line WL connected thereto and a pair of bit lines BL and BLB. Further, a plate line PL is provided in the same direction as the word line WL. The word line WL is driven from the ground potential to the power supply potential VDD by the word driver WD. The plate line is driven from the ground potential to the power supply potential VDD or the boosted power supply level (not shown) by the plate line drive circuit PLD.
[0016]
FIG. 1 shows a memory cell MC of a two-transistor two-capacitor type. This memory cell has cell transistors CT0 and CT1 whose gates are connected to word lines, and ferroelectric capacitors FC0 and FC1 provided between the cell transistors CT0 and CT1 and the plate line PL. The ferroelectric capacitors FC0 and FC1 use the plate line PL as a first electrode, the second electrode is connected to a cell transistor, respectively, and the ferroelectric layer between the first and second electrodes has hysteresis characteristics and remanent polarization. Action.
[0017]
The memory cell MC further has coupling capacitors CC0 and CC1 between the second electrode of the ferroelectric capacitor and the bit lines BL and BLB. This coupling capacitor uses the bit lines BL and BLB as one electrode, and connects the other electrode to the second electrode of the ferroelectric capacitors FC0 and FC1.
[0018]
In the above-mentioned memory, in the write operation, the sense amplifier SA drives the bit line pair BL, BLB to the opposite phase level, and drives the word line WL to the power supply voltage VDD, thereby changing the bit line voltage to the ferroelectric capacitor. Apply to FC0 and FC1. For example, assume that bit line BL is driven to an H level and BLB is driven to an L level. At this time, the plate line PL is at the ground potential, for example, and the electric field in the first direction is applied to the ferroelectric capacitor FC0 on the bit line BL side driven to the H level, and the plate line PL is polarized in the first direction. In this state, when the plate line PL is driven to the power supply voltage VDD, the ferroelectric capacitor FC1 on the side of the bit line BLB driven to the L level now has the second direction opposite to the first direction. An electric field in a direction is applied to polarize in a second direction. At this time, the polarization direction of the ferroelectric capacitor FC0 is maintained by the hysteresis characteristics. After that, when the plate line is returned to the ground potential and the word line WL is lowered to the ground potential, the ferroelectric capacitor FC0 has the remanent polarization state in the first direction and the ferroelectric capacitor FC1 has the polarization state in the second direction. Is held as
[0019]
FIG. 2 is a timing chart showing a read operation of the memory according to the present embodiment. As a premise, the bit lines BL and BLB are in a floating state after being precharged to the ground potential. Then, in response to the fall of the clock CLK that controls the read cycle, the plate line PL is driven to the power supply voltage VDD. At this time, the word line WL is not driven, and remains at the ground potential. In response to the rise of the plate line PL, charges corresponding to the remanent polarization direction flow out to the nodes N0 and N1 on the second electrode side of the ferroelectric capacitors FC0 and FC1, and the potential on the node N0 side greatly increases. , The potential on the node N1 side does not rise so much. The voltage fluctuations at the nodes N0 and N1 also cause voltage fluctuations in the floating bit lines BL and BLB via the coupling capacitors CC0 and CC1, and a slight voltage difference is generated between the pair of bit lines BL and BLB. appear. In this state, when the sense amplifier activation signals PSA and NSA are driven to drive the sense amplifier SA, the voltage difference between the bit line pair is amplified, the bit line BL is driven to the power supply voltage VDD, and the bit line BLB is connected to the ground potential. Is driven. The voltage of the bit line pair is output to the outside via an output circuit (not shown).
[0020]
After the bit line pair is driven by the sense amplifier, the plate line PL is returned to the ground potential. Even if the plate line is no longer driven, the bit line pair is driven by the sense amplifier, so that the level does not change via the coupling capacitor. Then, as the plate line returns to the ground potential, the nodes N0 and N1 also return to the original ground potential. Eventually, the driving of the sense amplifier activation signals PSA and NSA is completed, the sense amplifier is inactivated, and the bit line is precharged to a ground potential by a precharge circuit (not shown).
[0021]
In the above read operation, since the word line WL is not driven, the cell transistors CT0 and CT1 maintain the non-conductive state. Therefore, even if the plate line PL is driven, the electric charge flowing out of the ferroelectric capacitor does not flow out to the bit line via the cell transistor. As a result, when the plate line PL is returned to the ground potential, The capacitor is returned to its original polarization state. That is, the storage state of the ferroelectric capacitor is not destroyed, and accordingly, a rewrite operation for driving the plate line again is not required. After all, in the read operation, the word line WL is not driven, and the plate line PL is driven only once. Compared with a conventional read operation involving one drive of the word line WL and a read operation involving two drives of the plate line PL, the number of drives is reduced, so that power consumption is reduced, reading is speeded up, and the read cycle is reduced. Can be shorter.
[0022]
In the read operation of FIG. 2, the plate line PL is driven from the ground potential to the power supply voltage VDD. However, the drive level may be set to an appropriate level lower than the power supply voltage VDD. In this case, the polarization state of the ferroelectric is reliably maintained by appropriately controlling the driving level of the plate line in accordance with the hysteresis characteristic of the ferroelectric of the ferroelectric capacitor by driving the plate line PL. That is, the drive level of the plate line PL is set to a drive level lower than the maximum applied voltage for shifting the state of the hysteresis characteristic so that the polarization state at the time of writing is maintained.
[0023]
The hysteresis curve shown in FIG. 2 shows that the dielectric polarization state of the ferroelectric film changes to H1-H2-H3-H4 due to the application of a voltage, and shows two stable states H2 and H4 in the state where no voltage is applied. Has been shown. For example, in the state H4, if the applied voltage VDD of the plate line PL is lower than the voltage Vh in the state H1, the state does not transition to the next state H2. Similarly, in the state H2, if the applied voltage VDD of the plate line PL is lower than the voltage Vh in the state H3, there is no transition to the next state H4. Therefore, it is preferable to set the drive level of the plate line to the maximum level in a range smaller than the voltage Vh.
[0024]
FIG. 3 is a timing chart of another read operation in the present embodiment. This read operation is different from the read operation in FIG. 2 in that the drive level of the plate line PL is a boosted power supply Vpp level higher than the power supply voltage VDD. If the hysteresis characteristic of the ferroelectric capacitor can maintain the aforementioned polarization state even when the plate line is driven to the boosted power supply Vpp, it is desirable to drive the plate line PL to the boosted power supply Vpp level higher than the power supply voltage. . This is because the higher the drive level, the larger the voltage fluctuation generated at the nodes N0 and N1 and the larger the voltage fluctuation output to the bit line via the coupling capacitor.
[0025]
Next, a specific structure of the memory according to the present embodiment will be described. FIG. 4 is a plan view of the memory, and FIG. 5 is a cross-sectional view along XX of FIG. An N-type diffusion layer 10 constituting a cell transistor and a gate electrode WL are formed on the surface of a P-type semiconductor substrate 1. The gate electrode also serves as the word line WL. The diffusion layer 10 is formed in a region defined by the element isolation insulating film 2. Further, a plate line layer PL constituting a ferroelectric capacitor, a ferroelectric layer FD, and a second electrode layer 12 are formed on the insulating film 3. The plate line layer PL extends in parallel with the word line layer WL, in the row direction in FIG. 4, and in the direction perpendicular to the plane of FIG. The plate line layer PL also serves as the first electrode layer of the ferroelectric capacitor, and is a conductive layer made of, for example, platinum Pt, like the second electrode layer 12.
[0026]
As shown in FIG. 4, the plate line layer PL forming the first electrode of the ferroelectric capacitor has a wiring pattern extending in the row direction, whereas the second electrode layer 12 of the ferroelectric capacitor has It has a rectangular pattern separated for each memory cell. The second electrode layer 12 is connected to the conductive layer 14 via the contact hole 16 and further connected to the diffusion layer 10 of the cell transistor via the contact hole NA. Further, the bit line layers BL and BLB are formed on the conductive layer 14 and connected to the other diffusion layer 10 of the cell transistor via the contact holes NB. Insulating layers 4 and 5 are provided above and below the conductive layers 14, BL and BLB. Although only the bit line BLB is visible in the cross-sectional view taken along the line XX in FIG. 4, the cross-sectional view along the bit line BL has the same structure, and therefore, is described as the bit lines BL and BLB in FIG. .
[0027]
In the configuration of the memory cell of FIGS. 4 and 5, the conductive layer 14 is formed on the first aluminum wiring layer, and the bit line BL is formed on the second aluminum wiring layer thereon. That is, of the multi-layered wiring composed of aluminum wiring, the two lowest wiring layers are used for the conductive layer 14 and the bit lines BL and BLB. The upper aluminum wiring layer is used, for example, for power supply wiring. Then, the conductive layer 14 and the bit line BL are provided to face each other with a thin insulating layer therebetween, and the coupling capacitors CC0 and CC1 are formed there. That is, by arranging the conductive layer 14 connecting the second electrode 12, which is the top electrode of the ferroelectric capacitor, and the cell transistors CT0, CT1, and the bit lines BL, BLB close to each other, the coupling capacitor is placed there. Can be provided, so that the area of the memory cell does not increase.
[0028]
It is preferable that the thickness of the insulating layer between the conductive layer 14 and the bit lines BL and BLB be smaller than the thickness of the insulating layer between other multilayer wiring layers (not shown). Further, it is preferable to make the dielectric constant of the insulating layer higher than that of the other insulating layers. In any case, this contributes to increasing the capacitance value of the coupling capacitors CC0 and CC1.
[0029]
6 and 7 are a plan view and a sectional view showing a modification of the memory of FIGS. The same reference numbers as in FIGS. As shown in FIGS. 6 and 7, in this modification, the conductive layer 14 extends long in the bit line direction. That is, one end 14A of the conductive layer 14 extends over the word line WL to approach the contact hole NB, and the other end 14B extends to the outside of the top electrode 12 and the plate line PL of the ferroelectric capacitor. Extending. The conductive layer 14 does not need to extend in the vertical direction in FIG. 6 (the horizontal direction in FIG. 7) as long as it only connects between the contact hole 16 and the NA. It is extended to increase the capacity. Thereby, the area where the bit lines BL and BLB and the conductive layer 14 are close to each other increases, and the capacitance of the coupling capacitor increases. As a result, voltage changes at the nodes N0 and N1 connected to the second electrodes of the ferroelectric capacitors at the time of reading can be effectively transmitted to the bit lines BL and BLB.
[0030]
FIG. 8 is a plan view showing a second modification of the memory of FIG. The cross-sectional view is the same as FIG. 5 and is omitted. In the modification of FIG. 8, the width of the conductive layer 14 and the bit lines BL and BLB is formed larger than the top electrode 12 of the ferroelectric capacitor and the diffusion layer 10 of the cell transistor. With this configuration, the area of the coupling capacitor formed between the conductive layer 14 and the bit line layers BL and BLB can be increased, and the coupling capacitance can be increased. The thickening of the bit lines BL and BLB is limited only to the region facing the conductive layer 14, and may be thinner in other areas.
[0031]
FIG. 9 is a plan view showing a third modification of the memory of FIG. The sectional view is the same as FIG. In the modification shown in FIG. 9, both ends 14A and 14B of the conductive layer 14 extend to the vicinity of the contact hole NB beyond the word line WL and to the outside of the plate line PL and the top electrode 12, and the bit lines BL and The width of the BLB and the conductive layer 14 is wider than that of the top electrode 12, the diffusion layer 10, and the like. Thereby, the capacitances of the coupling capacitors CC0 and CC1 can be maximized.
[0032]
A second specific structure of the memory according to the present embodiment will be described. FIG. 10 is a plan view of the memory, and FIG. 11 is a cross-sectional view along YY of FIG. This memory is different from FIGS. 4 to 9 in that the conductive layer 14 connecting the top electrode (second electrode) 12 of the ferroelectric capacitor and the cell transistor and the bit lines BL and BLB are made of the same material such as aluminum. Is formed on the wiring layer. By arranging the bit lines BL and BLB and the conductive layer 14 close to each other in the horizontal direction, horizontal coupling capacitors CC0 and CC1 are formed. Therefore, the bit line BLB is indicated by a broken line in the cross-sectional view of FIG. The bit lines BL and BLB are connected to the contact hole NB via the lead-out wiring 18. In addition, the conductive layer 14 and the lead-out wiring 18 are connected to the diffusion layer 10 of the cell transistor via the contact hole NB formed in the same step.
[0033]
As described above, even when the bit lines BL and BLB and the conductive layer 14 are provided adjacent to each other in the horizontal direction, the coupling capacitor is formed by the dielectric film between both layers, so that the area of the memory cell increases. I won't let you.
[0034]
12 and 13 are a plan view and a cross-sectional view showing a first modification of FIGS. In this modification, both ends of the conductive layer 14 provided alongside the bit lines BL and BLB extend in the vertical direction in FIG. 12 and in the horizontal direction in FIG. That is, one end 14A of the conductive layer 14 extends over the word line WL to approach the lead-out wiring 18 connected to the contact hole NB, and the other end 14B extends to the outside of the plate line PL and the top electrode 12. Extending. By doing so, it is possible to increase the area close to the adjacent bit lines BL and BLB and increase the capacitance of the coupling capacitors CC0 and CC1. Further, a capacitance is also formed between the lead-out wiring 18 and the conductive layer 14, and the capacitance value further increases.
[0035]
FIG. 14 is a cross-sectional view showing a second modification of FIGS. In this modification, the bit lines BL, BLB and the conductive layer 14 are formed to be thicker than the other wiring layers 20. One end 14A of the conductive layer 14 extends to the vicinity of the lead-out wiring 18, and the other end 14B extends to the outside of the plate line PL and the top electrode 12. By increasing the thicknesses of the bit lines BL and BLB and the conductive layer 14, the capacitance of the coupling capacitors CC0 and CC1 provided therebetween can be increased. By extending both ends of the conductive layer 14, the capacity of the coupling capacitor can be increased for the same reason as in FIGS. In particular, by bringing the wiring close to the lead-out wiring 18 connected to the bit lines BL and BLB, a large capacitance is formed therebetween, and the capacitance of the coupling capacitor can be further increased. Even with the configuration of FIG. 14, the area of the memory cell does not increase, so that there is no adverse effect on high integration.
[0036]
FIG. 15 is a sectional view showing a third specific configuration of the memory according to the present embodiment. The plan view is substantially the same as, for example, FIG. In this example, the bit lines BL and BLB are formed in a first conductive layer of aluminum or the like, and a conductive layer 22 connecting the second electrode (top electrode) 12 of the ferroelectric capacitor and the diffusion layer 10 of the cell transistor. Is formed as a special conductive layer instead of a multilayer wiring of aluminum. For example, a high-resistance but conductive wiring made of TiN or the like is used. Then, the insulating layer between the conductive layer 22 and the bit line layers BL and BLB opposed to the conductive layer 22 is formed very thin, and the coupling capacitors CC0 and CC1 are formed. The conductive layer 22 and the diffusion layer 10 of the cell transistor are connected by a contact hole NC.
[0037]
In this embodiment, one electrode of the coupling capacitor can be formed as the conductive layer 22 without using an aluminum wiring layer having a multilayer wiring structure.
[0038]
FIG. 16 is a timing waveform chart showing a high-speed write operation in the present embodiment. The high-speed write operation in FIG. 16 will be described on the premise of the memory circuit shown in FIG. First, when it is detected that the write command WRT has become L level at the falling timing of the timing clock CLK, the sense amplifier activation signals PSA and NSA are driven, and the sense amplifier SA is activated. Accordingly, the sense amplifier SA drives one bit line BL to H level and the other bit line BLB to L level according to data from an input circuit (not shown).
[0039]
With the bit line pair BL and BLB thus driven to the maximum amplitude in accordance with the write data, the plate line PL is driven to the power supply voltage VDD before driving the word line WL. When the plate line PL is driven to the power supply voltage, the word line WL is not driven, and thus both the cell transistors CT0 and CT1 are in a non-conductive state. Therefore, compared with the state where the cell transistors are turned on and the bit lines BL and BLB are connected to the nodes N0 and N1, the driving load of the plate line PL is lighter, which contributes to higher speed and lower power consumption. Become.
[0040]
By driving the plate line PL to the power supply voltage, a voltage difference occurs between the nodes N0 and N1. Therefore, when the word line WL is driven, the voltages of the bit lines BL and BLB are directly applied to the ferroelectric capacitors FC0 and FC1. Since the bit line BLB is at L level, the node N1 is also at L level, a voltage is generated between the plate line PL at H level and a voltage in a certain direction is applied to the ferroelectric capacitor FC1. Polarization state. On the other hand, since the bit line BL is at the H level, the node N0 is also set at the H level, and no voltage difference occurs between the bit line BL and the plate line PL at the H level.
[0041]
Thereafter, when the plate line PL is lowered to the ground potential, a voltage in the opposite direction is applied to the ferroelectric capacitor FC0, and the ferroelectric capacitor FC0 is polarized in that direction. Thus, the polarization state in the opposite direction remains as the remanent polarization in the ferroelectric capacitors FC0 and FC1. Then, the sense amplifier is inactivated, and the word line WL is lowered to the ground potential.
[0042]
In the above-described write operation, the plate line PL is driven to the power supply level prior to driving the word line, so that the drive load of the plate line is reduced and high-speed write can be realized. That is, in this write operation, the coupling capacitors CC0 and CC1 are not particularly used.
[0043]
FIG. 17 is a timing waveform chart showing a read-modify-write operation in the present embodiment. The read-modify-write operation is an operation of writing certain data to a certain memory cell immediately after performing a read operation. The high-speed write operation in FIG. 16 will be described on the premise of the memory circuit shown in FIG.
[0044]
When the read-modify-write command CMD is detected at the rising edge of the timing clock CLK, the read operation as shown in FIG. 2 is started. That is, the plate line PL is driven from the ground potential to the power supply potential VDD without driving the word line WL. Accordingly, a minute voltage is generated at the nodes N0 and N1 connected to the second electrode of the ferroelectric capacitor, and a minute voltage difference is generated between the pair of bit lines BL and BLB via the coupling capacitors CC0 and CC1. I do. In this state, when the activation signals PSA and NSA of the sense amplifier are driven, a slight voltage difference between the bit line pair is detected and amplified by the sense amplifier SA. Thereby, the bit line pair BL, BLB is driven to the ground potential and the power supply potential. In this read state, the bit line BL is at H level and the bit line BLB is at L level.
[0045]
Thereafter, in order to write the inverted data into the memory cell, the word line WL is driven, and the sense amplifier is activated in accordance with the write data while the word line is driven. If the write data is inverted data, the sense amplifier is inverted and drives the bit line BLB to H level and the bit line BL to L level. Since word line WL is driven to the power supply level, H level of bit line BLB is applied to node N1, and L level of bit line BL is applied to node N0. Now, since the plate line PL is at the H level, the ferroelectric capacitor FC0 is polarized. Then, when the plate line PL is lowered to the L level, the ferroelectric capacitor FC1 is now in a polarized state. However, the polarization state is opposite to that of FC0. Then, even if the word line WL falls and the sense amplifier is deactivated, the ferroelectric capacitors FC0 and FC1 remain in a remanent polarization state, and data is stored.
[0046]
As described above, in the memory according to the embodiment in which the coupling capacitor is provided, the plate line PL is driven only once even in the read-modify-write operation. Can be achieved. The one-time driving of the word line is the same in the conventional example.
[0047]
As described above, the embodiments are summarized as follows.
[0048]
(Supplementary Note 1) In a ferroelectric memory using a ferroelectric capacitor,
Multiple word lines and multiple bit lines,
A plurality of memory cells arranged at their intersections,
Having a plurality of plate lines,
The memory cell is driven by the word line provided between the bit line and a second terminal of the ferroelectric capacitor, the ferroelectric capacitor having a first terminal connected to the plate line. A cell transistor; and a coupling capacitor provided between the second terminal and the bit line;
At the time of reading, the voltage change of the second terminal generated according to the remanent polarization direction of the ferroelectric capacitor by driving the plate line without driving the word line is performed via the coupling capacitor. A ferroelectric memory for outputting the data to the bit line.
[0049]
(Supplementary Note 2) In Supplementary Note 1,
The voltage change of the second terminal is output to the bit line via the coupling capacitor, and then the bit line is driven by a sense amplifier, and then the driving of the plate line is terminated. Ferroelectric memory.
[0050]
(Supplementary Note 3) In Supplementary note 1,
In the read-modify-write operation, the plate line is driven without driving the word line, and the voltage change of the second terminal generated according to the remanent polarization direction of the ferroelectric capacitor is detected by the cup. Output to the bit line via a ring capacitor, read storage data, then drive the word line to make the cell transistor conductive, drive the bit line according to the write data, A ferroelectric memory, wherein driving of a line is terminated.
[0051]
(Supplementary Note 4) In Supplementary Note 1,
In the write operation, before driving the word line, the plate line is driven, and then, while the bit line is driven according to the write data, the word line is driven, and then the driving of the plate line is terminated. A ferroelectric memory.
[0052]
(Supplementary Note 5) In Supplementary Note 1,
In the write operation, before driving the word line, the plate line is driven, then the word line is driven, and then the bit line is driven according to the write data, and then the plate line is driven. A ferroelectric memory characterized by terminating.
[0053]
(Supplementary Note 6) In a ferroelectric memory using a ferroelectric capacitor,
Multiple word lines and multiple bit lines,
A plurality of memory cells arranged at their intersections,
Having a plurality of plate lines,
The memory cell includes a ferroelectric capacitor having the plate line as a first electrode and further having a ferroelectric layer and a second electrode, and a memory cell between the bit line and a second electrode of the ferroelectric capacitor. A cell transistor provided with the word line as a gate, and a coupling capacitor provided between the second electrode and the bit line.
The ferroelectric memory, wherein the coupling capacitor includes a third electrode connected to the second electrode and the bit line adjacent to the third electrode.
[0054]
(Supplementary Note 7) In Supplementary note 6,
A part of a wiring connecting the second electrode of the ferroelectric capacitor and the cell transistor is used as the third electrode, and the third electrode is provided near the bit line. Dielectric memory.
[0055]
(Supplementary Note 8) In supplementary note 6,
Furthermore, it has a multilayer wiring layer,
The third electrode is formed on a first wiring layer of the multilayer wiring layers, and the bit line is formed on a second wiring layer provided above the first wiring layer. A ferroelectric memory characterized by the above-mentioned.
[0056]
(Supplementary Note 9) In Supplementary note 8,
The interlayer insulating layer between the third electrode and the bit line is formed thinner than other interlayer insulating layers of the multilayer wiring layer or has a higher dielectric constant. Dielectric memory.
[0057]
(Supplementary Note 10) In Supplementary Note 8,
One end of the third electrode extends to near the contact hole connecting the bit line and the cell transistor, and the other end extends to the outside of the second electrode of the ferroelectric capacitor. Characteristic ferroelectric memory.
[0058]
(Supplementary Note 11) In Supplementary Note 8,
2. The ferroelectric memory according to claim 1, wherein the width of the bit line and the width of the third electrode are larger than the width of the second electrode of the ferroelectric capacitor.
[0059]
(Supplementary Note 12) In Supplementary Note 6,
Furthermore, it has a multilayer wiring layer,
A ferroelectric memory, wherein the third electrode and the bit line are formed close to each other on the same wiring layer of any of the plurality of wiring layers.
[0060]
(Supplementary Note 13) In Supplementary Note 12,
One end of the third electrode extends to near the contact hole connecting the bit line and the cell transistor, and the other end extends to the outside of the second electrode of the ferroelectric capacitor. Characteristic ferroelectric memory.
[0061]
(Supplementary Note 14) In Supplementary Note 12,
A ferroelectric memory, wherein a wiring layer on which the third electrode and the bit line are formed is formed thicker than other wiring layers of the multilayer wiring layer.
[0062]
(Supplementary Note 15) In Supplementary Note 6,
Furthermore, it has a multilayer wiring layer,
The bit line is formed in a lowermost wiring layer of the multilayer wiring layer,
2. The ferroelectric memory according to claim 1, wherein the third electrode is formed of a local wiring layer formed below the multilayer wiring layer.
[0063]
(Supplementary Note 16) In any one of Supplementary Notes 6 to 15,
A first electrode, a ferroelectric layer, and a second electrode constituting the ferroelectric capacitor are formed on a first insulating layer covering a gate of the cell transistor;
Further, the third electrode and the bit line are formed on a second insulating layer covering the ferroelectric capacitor.
[0064]
【The invention's effect】
As described above, according to the present invention, in a ferroelectric memory, it is not necessary to drive a word line in a read operation, so that low power consumption and high-speed read can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a ferroelectric memory according to the present embodiment.
FIG. 2 is a timing chart showing a read operation of a memory in the present embodiment.
FIG. 3 is a timing chart of another read operation in the present embodiment.
FIG. 4 is a plan view of a memory according to the present embodiment.
FIG. 5 is a cross-sectional view of a memory according to the present embodiment.
FIG. 6 is a plan view showing a modification of the memory of FIG. 4;
FIG. 7 is a sectional view showing a modification of the memory of FIG. 5;
FIG. 8 is a plan view showing a second modification of the memory of FIG. 4;
FIG. 9 is a plan view showing a third modification of the memory of FIG. 4;
FIG. 10 is a plan view of a second specific structure of the memory according to the present embodiment.
FIG. 11 is a sectional view taken along the line YY of FIG. 10;
FIG. 12 is a plan view showing a first modification of FIGS.
FIG. 13 is a sectional view showing a first modification of FIGS.
FIG. 14 is a sectional view showing a second modification of FIGS.
FIG. 15 is a sectional view showing a third specific configuration of the memory according to the present embodiment;
FIG. 16 is a timing waveform chart showing a high-speed write operation in the present embodiment.
FIG. 17 is a timing waveform chart showing a read-modify-write operation in the present embodiment.
[Explanation of symbols]
WL: word line, BL, BLB: bit line, PL: plate line (first electrode), 12: second electrode, 14: third electrode, FC0, FC1: ferroelectric capacitor, CC0, CC1: Coupling capacitor

Claims (10)

In a ferroelectric memory using a ferroelectric capacitor,
Multiple word lines and multiple bit lines,
A plurality of memory cells arranged at their intersections,
Having a plurality of plate lines,
The memory cell is driven by the word line provided between the bit line and a second terminal of the ferroelectric capacitor, the ferroelectric capacitor having a first terminal connected to the plate line. A cell transistor; and a coupling capacitor provided between the second terminal and the bit line;
At the time of reading, the voltage change of the second terminal generated according to the remanent polarization direction of the ferroelectric capacitor by driving the plate line without driving the word line is performed via the coupling capacitor. A ferroelectric memory for outputting the data to the bit line. In claim 1,
The voltage change of the second terminal is output to the bit line via the coupling capacitor, and then the bit line is driven by a sense amplifier, and then the driving of the plate line is terminated. Ferroelectric memory. In claim 1,
In the read-modify-write operation, the plate line is driven without driving the word line, and the voltage change of the second terminal generated according to the remanent polarization direction of the ferroelectric capacitor is detected by the cup. Output to the bit line via a ring capacitor, read storage data, then drive the word line to make the cell transistor conductive, drive the bit line according to the write data, A ferroelectric memory, wherein driving of a line is terminated. In claim 1,
In the write operation, before driving the word line, the plate line is driven, and then, while the bit line is driven according to the write data, the word line is driven, and then the driving of the plate line is terminated. A ferroelectric memory. In claim 1,
In the write operation, before driving the word line, the plate line is driven, then the word line is driven, and then the bit line is driven according to the write data, and then the plate line is driven. A ferroelectric memory characterized by terminating. In a ferroelectric memory using a ferroelectric capacitor,
Multiple word lines and multiple bit lines,
A plurality of memory cells arranged at their intersections,
Having a plurality of plate lines,
The memory cell includes a ferroelectric capacitor having the plate line as a first electrode and further having a ferroelectric layer and a second electrode, and a memory cell between the bit line and a second electrode of the ferroelectric capacitor. A cell transistor provided with the word line as a gate, and a coupling capacitor provided between the second electrode and the bit line.
The ferroelectric memory, wherein the coupling capacitor includes a third electrode connected to the second electrode and the bit line adjacent to the third electrode. In claim 6,
A part of a wiring connecting the second electrode of the ferroelectric capacitor and the cell transistor is used as the third electrode, and the third electrode is provided near the bit line. Dielectric memory. In claim 6,
Furthermore, it has a multilayer wiring layer,
The third electrode is formed on a first wiring layer of the multilayer wiring layers, and the bit line is formed on a second wiring layer provided above the first wiring layer. A ferroelectric memory characterized by the above-mentioned. In claim 6,
Furthermore, it has a multilayer wiring layer,
A ferroelectric memory, wherein the third electrode and the bit line are formed close to each other on the same wiring layer of any of the plurality of wiring layers. In claim 6,
Furthermore, it has a multilayer wiring layer,
The bit line is formed in a lowermost wiring layer of the multilayer wiring layer,
2. The ferroelectric memory according to claim 1, wherein the third electrode is formed of a local wiring layer formed below the multilayer wiring layer.

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