JP2004164670A - Semiconductor integrated circuit device, functional circuit block, memory, and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microprocessor capable of reducing the power consumption and increasing the processing speed. <P>SOLUTION: The microprocessor has a detection means for detecting instructions which operate respective arithmetic circuits in advance and a means for activating one or more arithmetic circuits corresponding to instructions detected by the detection means before arithmetic performance and inactivating the activated arithmetic circuits after the end of arithmetic performance, and n (n≥2) instructions are simultaneously read out and decoded, and n arithmetic circuits are used to simultaneously perform arithmetics. Thus a semiconductor integrated circuit device, especially a microprocessor having an on-chip memory like a cache memory, capable of reducing the power consumption and increasing the processing speed in a functional circuit block can be obtained. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a semiconductor integrated circuit such as a microprocessor having a functional circuit block that requires low power consumption, such as a built-in cache memory that requires high-speed access and multi-bit output.

  Hereinafter, a conventional technique will be described using a microprocessor as an example.

  Recent high-speed microprocessors (hereinafter referred to as MPUs) have a cache memory inside the MPU to solve the problem caused by the mismatch between the internal instruction execution speed and the transfer speed of instructions and operands from the external main memory to the inside. In order to improve the processing performance by increasing the degree of parallelism and increasing the degree of parallelism, it has become common to incorporate a plurality of arithmetic units, and as a result, the increase in power consumption has become a serious problem. .

  The main purpose of incorporating a cache memory is to fetch instructions and data at high speed at a speed commensurate with the execution speed of the MPU.

  Today, the clock cycle of the fastest CISC type MPU is 25-40 MHz, but it is expected that RISC type MPUs exceeding 100 MHz will appear in the near future.

  Such an ultra-high-speed MPU requires an ultra-high-speed access of several ns or less as a built-in cache memory.

  The built-in cache memory has a feature that the number of words is relatively small, but the number of bits read out per word is extremely large (8 bits in a general-purpose SRAM). For example, parallel reading of several hundred bits is generally realized even in today's 32-bit MPU, and it is expected that the number of parallel readings will further increase if the MPU becomes 64-bit in the future.

  Here, in general, a differential high-sensitivity sense amplifier using a bipolar transistor is suitable as a sense amplifier for an ultra-high-speed memory. However, this circuit constantly consumes relatively large power. Also, power is consumed in other parts of the memory even if no memory access occurs without special power saving means.

  That is, the power consumption of the memory circuit becomes extremely large in a single-chip MPU incorporating a cache memory of ultra-high-speed access and multi-bit parallel output, so that there is no appropriate means for reducing power consumption. But it is expected that it will soon become impossible.

  A first prior art known as a low power consumption technique is to switch a memory circuit between a standby mode power consumption and a normal operation mode power consumption by a chip select signal CS equivalent to a memory address signal. There are those that reduce the power consumption.

  Further, as a second conventional technique, a change in an address signal is detected by, for example, an ATD (Addres Transition Detector) circuit, and a clock pulse required for an internal operation is generated based on the signal, thereby requiring a memory sense amplifier or the like. A device that operates only during a period to reduce power consumption is known.

Further, as described in Patent Document 1, for example, in a logic LSI such as an MPU, a) a power control instruction is provided corresponding to a plurality of function blocks, and the corresponding function block is switched to an active or inactive state by a program. B) A clock control circuit is provided for each functional block, and a method for realizing low power consumption by controlling the presence or absence of clock supply is provided. C) A power control circuit is provided for each functional block. A method of realizing low power consumption by cutting off the power supply to a functional block not used at the time of executing an instruction is known. However, in the above prior art, there is no consideration for noise induced on a power supply line or a ground line due to a rapid change of a power supply current when switching between a normal power consumption state and a low power consumption state. There is a problem.
1) Since the circuit current greatly changes between the low power consumption state and the normal operation state in a short time, a large noise voltage is generated due to the inductance and resistance of the power supply line and the GND line.
2) The functional circuit itself or another internal circuit malfunctions due to the noise voltage. Further, even if no malfunction occurs, a certain time is required until the noise voltage disappears, so that the memory access speed is effectively reduced.

  FIG. 24A is a diagram for explaining generation of noise voltage in the power supply system. In the figure, reference numeral 1300 denotes a power supply, reference numeral 1310 denotes a power supply, functional circuit blocks 1321 and 1322 such as, for example, a memory circuit, and GND system inductances 1331 and 1332, respectively, a power supply system and a GND system resistance.

FIG. 24B shows how the power supply current i changes and the power supply potential v ₁ and the GND potential v ₂ change when the SW is turned on at time t ₁ and turned off at time t ₂ .

As shown, when the switch SW is turned on at time t ₁ , the circuit current i changes from 0 to a steady current during Δt ₁ time. At this time, the power supply potential v ₁ of the circuit as shown changes greatly to have a peak in the negative direction, the GND potential v ₂ changing to have a peak in the positive direction increases. Conversely, when the switch SW is turned off at the time t ₂ , the circuit current i changes from the steady current to 0 during the time Δt ₂ . At this time, the power supply potential v ₁ of the circuit changes to have a peak in the positive direction increases, GND potential v ₂ changes greatly to have a peak in the negative direction.

For example, now, the circuit 1310 in FIG. 24 is a 500 sense amplifier, and 2
It is assumed that a current of mA is consumed, and this current is switched from 0 to a steady current at Δt = 1 ns. At this time, the resistances 1331 and 1332 are ignored, and the inductance 1321 and
1322 The L = 5 nH assuming the power supply noise v _n are as follows.

  That is, in today's semiconductor integrated circuits operating at a power supply voltage of 5 V or less, such large power supply noise becomes unacceptable.

Even if the noise can be reduced to an appropriate level, Δt ₁ time and Δt ₂ time are required until the power supply and the GND noise disappear, as shown in FIG. This time depends on the current switching time, but usually requires 1 to 3 ns. This time is unacceptable in an ultra-high-speed memory or the like that requires an access time of several ns or less, and becomes a major obstacle to high-speed operation.

  As described above, the problem of noise due to a change in power supply current is the same for a plurality of arithmetic units and other functional circuit blocks in a semiconductor chip.

  Incidentally, various technologies have begun to be introduced in recent high-performance MPUs in order to increase the processing capacity. The processing performance of the computer is evaluated by the following equation.

  The CPI is the number of cycles required for one instruction.

Attention in recent years' technology is the PISC processor. RISC is primarily intended to improve performance by bringing the above CPI closer to one.

Recently, as the next technology of RISC, Super Scalar, VLIW and the like have started to attract attention. This technology reads out at most n instructions at the same time, interprets n instructions at the same time, and executes n instructions at the same time. By increasing the degree of parallelism in hardware, the CPI in the above equation can be reduced to 1 / n. To improve the performance of the computer. High-speed operation circuits such as Super Scalar and VLIW include differential logic circuits using bipolar transistors and the like.
Although low-amplitude circuits based on BiCMOS have come to be used, circuits that flow direct current constantly consume relatively large power.

  In MPUs such as Super Scalar and VLIW, n high-speed operation circuits having the same function are required, and there is a problem that the power consumption of the operation circuit increases by n times.

  A related technique of this type is discussed, for example, in Non-Patent Document 1.

JP-A-61-45354 Nikkei Electronics No. 487, P191-200 of November 27, 1989 issue

  As is clear from the above description, the conventional technology for reducing power consumption in a semiconductor integrated circuit or an electronic circuit such as a microprocessor does not consider the problem of noise generated in a power supply line or a ground line at the time of power switching. Since it takes a certain amount of time until a circuit malfunctions or noise disappears, there is a problem that a quick start-up cannot be performed.

  In particular, in a conventional MPU having an on-chip memory, there is a trade-off relationship between low noise at the time of power switching and high-speed memory access, so that there has been a problem that it is difficult to achieve ultra-high speed.

  In addition, although the microprocessor having the cache memory has been described above, a similar problem occurs in a semiconductor integrated circuit or an electronic circuit having a functional block that requires high speed.

  Therefore, an object of the present invention is to provide a semiconductor integrated circuit device capable of reducing power consumption and increasing the speed of a functional circuit block, and in particular, to provide a microprocessor having an on-chip memory such as a cache memory.

  Here, the activation means supplying a predetermined power required for the operation of the circuit, and the inactivation means supplying a power smaller than the predetermined power.

According to the semiconductor integrated circuit device of the present invention, the functional circuit block having the power supply system inductance L, the allowable power supply noise V _n , and the switching width ΔI of the circuit current, and activating the functional circuit block in advance of the time T before the operation starts. Means for generating an operation start notice signal to
Wherein T, L, V _n and ΔI is

Satisfy the relationship.

  Further, according to the memory of the present invention, a notice signal for announcing the start of the operation is received, and the circuit current is increased to a predetermined value over a predetermined time from the reception of the notice signal, so that the normal operation is performed in the low power consumption mode. A functional circuit block having a function of shifting to the power consumption mode, reducing the circuit current to the low power consumption mode current over a predetermined time after the execution of the operation is completed, and shifting to the low power consumption mode; And is activated by an access notice signal for giving notice of access, and executes a predetermined memory operation based on an address signal, a read / write control signal, and a data input / output signal.

  Further, the microprocessor of the present invention is a microprocessor that simultaneously reads and decodes n (n ≧ 2) instructions, and simultaneously executes an operation using the n arithmetic circuits, and operates each arithmetic circuit. Detecting means for detecting an instruction in advance, and means for activating one or more arithmetic circuits corresponding to the instruction detected by the detecting means prior to execution of the operation, and deactivating the activated arithmetic circuit after completion of the operation And

  Further, the microprocessor of the present invention has means for detecting the occurrence of various race conditions between instructions executed at the same time, and in the case where a race condition has occurred, among the arithmetic circuits corresponding to the conflicting instructions, One of them is activated prior to execution of the operation, and a signal for inactivating other operation circuits is sent to the preceding detection means.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device capable of reducing the power consumption and operating speed of a functional circuit block, and in particular, to provide a microprocessor having an on-chip memory such as a cache memory.

  Hereinafter, an embodiment of a semiconductor integrated circuit according to the present invention will be described using a microprocessor as an example.

  FIG. 1 shows a configuration of a microprocessor (MPU) according to a first embodiment of the present invention.

  In the figure, reference numeral 100 denotes a single-chip MPU, but for convenience of explanation, only the components necessary for understanding the present embodiment are described below, and other parts are omitted.

  In the figure, reference numeral 101 denotes a program counter, which generates an instruction data read address in synchronization with a clock signal CLK. A memory address register 102 holds a read address of the instruction cache memory 103. An instruction data register 104 holds the instruction data read from the instruction cache memory 103.

  Reference numeral 111 denotes another memory address register, which holds a read or write address of the data cache memory 112. A memory data register 113 holds read data of the data cache memory 112 or write data to the data cache 112.

  The instruction data register 104 and the data register 113 are coupled to the internal data bus 172 and exchange data with the external data bus 161 via the input / output control circuit 160.

  Reference numeral 120 denotes a first instruction decoder, which decodes the output 105 of the instruction register 104 and outputs predetermined instruction control signals 121 and 122. An arithmetic unit 140 receives data necessary for the operation from the register file 150 via the internal bus 173, executes arithmetic operation, logical operation, shift operation, and the like, and outputs the result to the register file 150 via the internal bus 174. Write to. In other cases, the operation result is written to the memory address register 111 via the internal bus 175.

  The output 121 of the instruction decoder 120 specifies the content of the operation to the arithmetic unit 140. The output 122 of the instruction decoder 120 specifies a read or write operation for the register file 150.

  Reference numeral 130 denotes a second instruction decoder, which interprets the output 105 of the instruction register 104, predicts a memory access to the data cache 112, for example, and performs a predetermined process. Is output.

  The data cache 112 executes a predetermined memory access from this signal, an address signal from the memory address register 111, and a read / write control signal (omitted in the figure).

  The second instruction decoder 130 can have a function of generating the operation start notice signals 132 and 133 as required, in addition to the arithmetic unit 140, the register file 150, and the like.

  FIG. 2 shows a typical instruction execution stage of the MPU according to the present embodiment.

  In the figure, Instruction 1 and Instruction 2 indicate the execution stages of the RR operation (register-register operation).

  Instruction data is fetched from the instruction cache 103 at the IF stage in the figure, decoded by the instruction decoder 120 at the D stage, and a predetermined operation is executed by the arithmetic unit 140 at the EX stage. Finally, the operation result is written in the register file 150 in the W stage.

  Next, it is shown in the middle of the figure. In the LOAD instruction and the STORE instruction in which access to the data cache 112 occurs, the same operation as the above-described RR operation is performed up to the IF stage and the D stage. Is performed, and the data cache 112 is accessed in the next CA stage. Finally, in the W stage, the read data is written to the register file 150.

  As described above, in the LOAD / STORE instruction, the effective address calculation stage AC is always interposed between the decode stage D and the memory access stage CA. In this embodiment, the memory access occurs at the D stage two stages before the CA stage. , And outputs an access notice signal to the cache memory 112.

  Next, FIG. 3 shows the operation timing from the fetch of the instruction to the generation of the access notice signal and the execution of the memory access in more detail.

In the figure, reference numeral 3a denotes a system clock CLK, which has the same length as one of the instruction execution stages of FIG. 3, for example, 5 ns. 3b is IF stage, indicating that LOAD of M ₁ ~M ₅ in the figure, STORE instruction is fetched.

3c is a D stage, indicating that the LOAD or STORE instructions M ₁ ~M ₅ in the next stage of the IF stage is decoded.

3d is AC stage, the calculation of the execution address A ₁ to A ₅ for LOAD / STORE instructions M ₁ ~M ₅ decoded by 3c of the D stage is performed.

3e is a memory address A ₁ to A ₅ address calculation result, actual memory access CA stage 3f using this address is executed.

3g is a memory access prediction signal M ₁ ~M ₄ obtained by the second instruction decoder 130 shown in FIG. 1, is obtained as a result of decoding the M ₁ ~M ₅ of 3c in the D stage. Further, 3h denotes a memory access notice signal 131 obtained by performing predetermined processing to the memory access prediction signal M ₁ ~M ₅ of 3g, is output to the data cache 112.

Here, the access warning signal 3h is generated prior to one stage prior to the actual memory access 3f E ₁ stage to be performed, similarly occurs prior to the previous one stage relative to Ea stage I do.

Here, FIG. 4A shows the internal configuration of the second instruction decoder 130 (see FIG. 1) for generating the memory access notice signal 131, and FIG. 4B shows the operation timing.

In the figure, reference numeral 410 denotes a memory access prediction circuit which detects whether or not instruction data output from the instruction register 104 is an instruction accompanied by memory access. More specifically, it detects a LOAD instruction and a STORE instruction, and generates a detection signal DET as shown by 3g in FIG. 4B.
A flip-flop 420 latches the detection signal DET3g with the clock signal CLK3a, and its output / Q4a becomes a signal as shown in FIG. 4B (where / Q represents an inverted output of Q). An inverter 430 inverts the output / Q4a of the flip-flop 420 and generates an access notice signal PR3h as shown in FIG.

  The polarity of the PR signal 131 is not essential, but is a positive active signal in this embodiment.

  Next, FIG. 5 shows the internal configuration of the data cache memory 112 (see FIG. 1).

  In the figure, reference numeral 510 denotes an address buffer which receives an address signal Ai and outputs it as positive and negative address signals required for the address decoder / driver 520. The output of the address decoder / driver 520 is output to the memory array 530, and selects a memory array to be read or written.

A sense amplifier 540 amplifies a small signal read from the memory array 530 to a predetermined signal level and outputs the amplified signal. An output driver 550 is provided to drive the output _Do having a relatively heavy load.

  A write control circuit 560 writes the write data Di to a predetermined address of the memory array 530 using the write control signal WE.

Reference numeral 570 denotes a current control signal generating circuit which generates at least one or more current control signals 575 in response to the access notice signal PR. In the present example, and if the data cache memory 112 is shared, in order also provides an example of such a case where there is access to factors other than the execution of the instructions, receiving a plurality of warning signal PR ₁ ... PR _n, at least The case where one or more current control signals 575 are generated is shown.

  The control of the circuit current by the current control signal 575 is applicable to all circuit elements except the current control signal generation circuit 570 in the cache memory 112. Which circuit is selected for control depends on the actual hardware configuration and application to be applied.

  FIG. 6A shows a configuration example of the current control signal generation circuit 570 (see FIG. 5), and FIG. 6B shows the operation timing.

In the figure, reference numeral 610 denotes an OR gate, which takes an OR of the access notice signals PR _{1 to} PR _n and supplies its output to the inverter 620 and the flip-flop 660. Reference numeral 630 denotes a NOR gate, which NORs the output of the inverter 620 and the / Q output of the flip-flop 630, and
A signal PUP as shown in FIG.

Reference numeral 640 denotes an AND gate, which ANDs the Q output 6b of the flip-flop 660 and the clock signal CLK3a and outputs an MCLK signal shown in 6d of FIG. 6B. Also,
650 and 670 are an OR gate and a delay circuit, respectively. The OR gate 650 ORs the MCLK signal 6d and the signal obtained by delaying the MCLK signal by the delay circuit 670 for a predetermined time, and outputs the ΦSA signal shown in 6f of FIG. Is output.

  MA6e in FIG. 6B indicates a memory address in a memory access execution cycle.

As shown in FIG. 6B, the memory access to the memory addresses A ₁ and A ₂ is performed at the stage 6g at t ₂ and t ₃ . 6c PUP signal contrast becomes rising, the falling down signal at the end of t ₃ stage 1 stage preceding t ₁ stage than t ₂ stages.

The circuit current is controlled based on the PUP signal 6c, and this is shown in FIG. As shown in FIG. 7A, the current of the target circuit is raised from i ₁ to a predetermined current value i ₂ during the t ₁ stage based on the PUP signal 6c, and the memory access at t ₂ and t ₃ is performed. It maintains its current value at the stage, from the beginning of t ₄ stage a memory access is completed, pulls up to a predetermined low current value i ₂ of the current value.

Next, the MCLK signal 6d (FIG. 6B) is a pulse signal generated corresponding to each of the memory access stages t ₂ and t ₃ , and is useful as a memory clock in the case of being realized by a clock synchronous type memory. For the clock synchronous memory, refer to Documents 1) to 3).
Reference 1) Kevin j.O'connor: Modular Embeded Cache Memory for a 32b Piplined RISC
Microprocessor.1987 IS SCC p.256,257
2) Masanori Odaka et al: A 512kb / 5ns BiCMOS RAM with 1KG / 150ps Logic Gate
Array.1989 IS SCC p.28,29
3) Masayoshi Kimoto et al: A 1.4ns / 64kb RAM with 85ps / 3688 Logic Gate Array.
1989 CI CC p.15.8.1-15.8.4
The ΦSA signal 6f is a pulse signal generated corresponding to each of the memory access stages t ₂ and t ₃ , and is useful, for example, as a signal for pulsing the sense amplifier for a predetermined period.

  In other words, by independently controlling the activation of the sense amplifier alone, the power supply noise generated by the current switching is kept within an allowable range, and the signal is used as a signal for minimizing the activation time of the sense amplifier which is a high power consumption source. Can be.

  An example in which the circuit current is actually controlled using the above PUP signal and ΦSA signal will be described below.

  First, FIG. 8A shows a first example of a circuit for controlling a circuit current using a PUP signal, and FIG. 8B shows an operation waveform thereof.

In the figure, reference numerals 811 and 812 denote PMOSs, each of which has a source connected to the power supply V ₁ , a gate which is commonly connected and also connected to a drain of the PMOS 811. Reference numerals 821, 822, and 823 denote NMOSs. The drain of the transistor 821 is connected to the drain of the PMOS 811, the gate is connected to the PUP signal, and the source is connected to the reference potential.

  The drain of the NMOS 822 is connected to the drain of the PMOS 812, the gate is connected to the output of the inverter 830, the source is connected to the reference potential, and the input of the inverter 830 is connected to the PUP signal.

  Reference numeral 840 denotes an active circuit such as a differential amplifier, which is provided in a functional circuit block such as the data cache memory 112, the arithmetic unit 140, and the register file 150 (see FIG. 1). A predetermined operating current determined by the constant current source 850 flows. Further, an integrating capacitor C is connected between the gate of the NMOS 823 and GND.

The PMOSs 811 and 812 and the NMOSs 821 and 823 constitute a current mirror circuit. As shown in FIG. 4B, when the PUP signal rises from the “0” level to the “1” level, a predetermined value is supplied from the PMOS 812 to the capacitor C. , And the gate voltage Vg of the NMOS 823 and the current i of the circuit 840 rise gradually at a predetermined slew rate as shown in the middle and lower parts of FIG. The rise time t ₁ is a time corresponding to the stage t ₁ shown in FIG.

Similarly, when PUP changes from the "1" level to the "0" level, the voltage Vg and the current i gradually fall at a predetermined slew rate, and the fall time t ₄ similarly corresponds to t ₄ shown in FIG. It's time.

Note that the rise time t ₁ and the fall time t ₄ of the current i do not necessarily have to be the same, and since the operation of the circuit is completed, when the fall is made, shorten t ₄ within a range where no special inconvenience occurs. You can also.

  FIG. 9A shows a second example of the circuit for controlling the circuit current using the PUP signal, and FIG. 9B shows the operation waveform thereof.

In the figure, reference numerals 911 to 914 denote inverters, reference numerals 921 to 923 denote NMOSs, reference numerals 931 to 933 denote constant current sources, and reference numeral 940 denotes an active circuit such as a differential amplifier. The data cache memory 112, the arithmetic unit 140, and the register file 150 ( (See FIG. 1).

Here, if the delay time of the inverters 912 to 914 is designed to increase in the order of 914, 913, and 912, when the PUP signal changes from “0” to “1” level as shown in FIG. Currents i _{1 to} i ₃ flowing through 923 also rise with a predetermined time difference, and the operating current of active circuit 940 rises stepwise to a steady current of i ₁ + i ₂ + i ₃ after time t ₁ .

Similarly, the circuit current of the active circuit 940 when the PUP signal changes to "0" level from "1" falling into stepped in time t _4, similarly smooth to the embodiment of FIG. 8 effectively described above A large current change can be obtained.

The rise time t ₁ and the fall time t ₂ correspond to the times of the stages t ₁ and t ₄ in FIG. 7, as in the first example.

  Although an example in which the circuit current is actually controlled using the PUP signal and the ΦSA signal has been described above, the present embodiment is not limited to this, and may be implemented by another general method for controlling the circuit current. This embodiment can also be realized.

  Hereinafter, an example of the circuit current control in each unit of the data cache memory 112 (see FIG. 1) will be described taking the case where the first circuit current control circuit is used as an example.

  FIG. 10 shows an embodiment of the current control of the address buffer indicated by 510 in FIG.

  In the figure, 1011 to 1014 are NPN transistors, 1021 and 1022 are resistors, 1031 to 1033 are NMOSs, and 1041 to 1043 are constant current sources.

The emitters of NPNs 1011 and 1012 are commonly connected and connected to a constant current source 1041 via an NMOS 1031. Based NPN1011 and 1012 are respectively connected to the address signal Ai and the reference power source V _R, are connected in the collector via a resistor 1021, 1022 to power V _1. The collector of NPN1013,1014 is connected to the power source V _1, each base
Connected to the collectors of NPN1011 and NPN1012. The emitters of NPNs 1013 and 1014 are connected to constant current sources 1042 and 1043 via NMOSs 1032 and 1033, respectively.

  The output / ai is taken from the emitter of the NPN 1014 as the non-inverted output of the input Ai, and the output / ai is taken from the emitter of the NPN 1013 as the inverted output of the input Ai. The gates of the NMOSs 1031 to 1033 are commonly connected to the control signal Vg. The control signal Vg corresponds to the signal Vg shown in FIG.

Here, the NPNs 1011 and 1012, the resistors 1021 and 1022, and the constant current source 1041 constitute a differential amplifier. When the current control signal Vg is at the “1” level and the address signal Ai is higher than Vg, the NPN 1011 ON, NPN1012 is turned off, the collector of NPN1011 is at “0” level,
The collector of NPN1012 becomes "1" level.

  The collector of the NPN 1011 is connected to the base of the emitter follower transistor 1013, and the output / ai of "0" level is obtained from the emitter. Similarly, the collector of NPN 1012 is connected to the base of emitter follower transistor 1014, and an output / ai of "1" level is obtained from the emitter.

When the address signal Ai is lower than V _R, NPN1011 and NPN1012 is the reverse operation, / ai outputs "1" level, ai output becomes "0" level.

Next, when the current control signal Vg is "0" level, NMOS1031～1033 off all this time, since the current path from the power source V ₁ to the GND is eliminated, this circuit will not consume power.

  Here, since the current control signal Vg is set so that the rise and fall times become a predetermined time as shown in FIG. 8B, the change in current is also as shown by 7a in FIG. It can be gentle.

  Therefore, the power source and the GND noise (see FIG. 24B) at the time of the current switching as shown in FIG. 24B can be suppressed to a desired magnitude.

  Next, FIG. 11 shows an example of circuit current control of the decoder / driver 520, memory array 530, and sense amplifier 540 (see FIG. 5) in the data cache memory.

  In the figure, reference numerals 1161 and 1162 denote NOR gates, which correspond to the last stage of the address decoder.

Reference numerals 1171 and 1172 denote word drivers composed of AND gates. The outputs of the address decoders 1161 and 1162 are connected to one input, the control signal Vg is connected to the other input, and the word lines WL ₁ and WL ₂ are respectively connected by the outputs. Drive.

  Although not particularly limited, reference numeral 1100 denotes a 4MOS type memory cell, and only one cell is shown for convenience of explanation.

1111 and 1112 are load MOSs for pulling up bit lines. Also, 1113 ~
Reference numeral 1116 denotes a MOS switch for selecting a bit line, and a desired bit line is coupled to the common data line 1120 by column selection signals C ₁ and C ₂ .

Reference numerals 1121 and 1122 denote emitter follower circuits using NPN transistors, which level-shift the signal on the common data line 1120 by VBE (base-emitter voltage).
Communicate to each base of NPN1123, 1124. The emitters of NPN 1123 and 1124 are connected in common,
It is connected to a current source 1151 via an NMOS 1141. The collectors of NPNs 1123 and 1124 are connected to power supply V ₁ via resistors 1131 and 1132.

  The NPNs 1123 and 1124, the resistors 1131 and 1132, and the current source 1151 constitute a differential amplifier, and amplify a small signal read from the memory cell 100 to a predetermined amplitude. Similarly, 1150 constitutes a differential amplifier composed of two resistors and two NPNs, and is connected to a constant current source 1152 via an NMOS 1142.

  The two inputs of 1150 are connected to the collectors of NPNs 1123 and 1124, and further amplify those signals to obtain an output signal of a predetermined amplitude at terminal 1151.

Here, since the above-described current control signal Vg (see FIG. 8) is connected to one input of the AND gates 1171 and 1172, when the Vg is at the “1” level, the AND gates 1171 and 1172 are selectively connected. Driven to selectively drive the word lines WL ₁ and WL ₂ . On the other hand, when Vg is at the “0” level, all word drivers including the AND gates 1171 and 1172 are turned off. Therefore, at this time, the current flowing into all the memory cells including the memory cell 1100 is cut off. Therefore, unnecessary power consumption in a state where no memory is accessed is cut.

Similarly, the current control signal Vg is connected to the gates of the NMOSs 1141 and 1142. When Vg is at “1” level, the NMOSs 1141 and 1142 are on, and when Vg is at “0” level, they are off.

  Therefore, the current of the sense amplifier does not flow when the memory is not accessed, so that unnecessary power consumption is cut.

  Here, the change in the circuit current due to the current control signal Vg is as shown by 7a in FIG. 7, so that not only the power supply and GND noise due to the current switching can be suppressed to an allowable value, but also the above-mentioned time at the start of memory access. Since the noise has disappeared, high-speed operation is possible.

When the switch SW1180 is switched to the signal φSA in FIG. 11, the NMOSs 1141 and 1142 are operated in a pulsed manner. As described above, the ΦSA signal is a pulse signal that goes to “1” level only for a predetermined time of the memory access stages t ₂ and t ₃ (see FIG. 6B). Since power is supplied to the sense amplifier, power consumption can be reduced.

  Next, FIG. 12 shows an example of circuit current control of the output driver 550 (see FIG. 5) of the data cache memory 112.

In the figure, the drain, gate, and source of the PMOS 1211 are connected to the base of the NPN 1241, the input V _IN , and the power supply V ₁ , respectively. The drain, gate, and source of the NMOS 1221 are connected to the base of the NPN 1241, the input V _IN , and one end of the resistor 1251, respectively. The drain, gate, and source of the PMOS 1222 are connected to the drain of the NMOS 1221, the current control signal Vg, and the base of the NPN 1241, respectively. A capacitor 1261 is connected to both ends of the resistor 1251. An anode and a cathode of the diode 1231 are respectively connected to the collector and base of NPN1241, power V ₁ is connected to the collector of NPN1241. The emitter of NPN1241 is an output terminal, between the output terminal and the power supply V ₂ terminating resistor 1252 is connected.

Now, when the current control signal Vg is at the “1” level, the PMOS 1222 is off. At this time, if the input V _IN is at the “0” level, the PMOS 1211 turns on and the NMOS 1221 turns off.

Therefore, at this time, the base voltage of the NPN 1241 rises via the PMOS 1211 and the output V _OUT goes to the “1” level. Conversely, when V _IN is at the “1” level, the PMOS 1211 is turned off and the NMOS 1221 is turned on, the base voltage of the NPN 1241 is reduced, and the output V _OUT becomes the “0” level.

  Note that the diode 1231 is a clamper for suppressing a decrease in the base potential of the NPN 1241 to a predetermined value.

  Further, the resistor 1251 is for current limiting, and the capacitor 1261 is for speeding up.

Next, when Vg is at the “0” level, the PMOS 1222 is turned on. At this time, the base potential of NPN 1241 is lowered irrespective of the level of input V _IN , and output V _OUT becomes “0” level. Therefore, the collector voltage V _{OUT of} NPN 1241 is smaller than that at the time of “1” level, and low power consumption can be achieved.

  Therefore, an effect similar to that of the above-described circuit current control of the address buffer 510, the decoder / driver 520, the memory array 530, and the sense amplifier 540 can be obtained.

  As described above, an example of the circuit current control in each unit of the data cache memory 112 (see FIG. 1) has been described taking the case where the first circuit current control circuit is used as an example. Circuit current control circuit (see FIG. 9) or another circuit current control circuit may be used.

  As described above, in the present embodiment, the description has been made mainly on the example of the low power consumption by the memory access method using the access notice signal, but as described above, for example, the instruction such as the arithmetic unit and the register file in the single chip MPU The same applies to all functional circuits whose operation is controlled by word interpretation. Further, in the present embodiment, an example has been described in which the start-up of the circuit current is started in synchronization with the previous stage of the operation execution stage. The start-up may be started in advance of the start of the execution stage for the time during which the noise of the above can be suppressed to a predetermined value. In this case, the PUP signal may be a significant signal at a desired timing, not in synchronization with the stage before the execution stage.

  As described above, according to the present embodiment, after the memory circuit and other functional circuits included in the single-chip microprocessor start up the circuit current at a predetermined rate by the access notice signal prior to the actual operation before the operation starts, Perform a predetermined operation. Therefore, these functional circuits consume power required for circuit performance only when actually operating, which is effective in reducing the power of a single-chip microprocessor.

  In addition, new functions can be added as much as the power consumption is reduced, which is also effective for higher functions and higher integration.

  In addition, since each functional circuit can change the circuit current at a predetermined rate, noise of the power supply and the ground line due to the current change can be suppressed to a predetermined value. Therefore, there is an effect that a highly reliable circuit operation can be realized.

  Furthermore, in the respective functional circuits to which the present embodiment is applied, since the noise of the power supply line and the ground line has disappeared at the time of starting the actual operation, the circuit can operate in the best power supply state, and the circuit can operate at high speed. There is also an effect on the operation.

  Next, a case where the present invention is applied to a Super Scalar type RISC processor will be described.

  Super Scalar type RISC processor is mainly equipped with a plurality of operation units that share a register file, simplifies instructions and reduces the number of pipeline stages, and reads out multiple instructions in one machine cycle. Is controlled. In other words, a plurality of instructions are read and executed simultaneously in one machine cycle, so that a plurality of operation units operate simultaneously and the processing capability can be increased.

  FIG. 13 is a list of instructions of the processor described in the second embodiment. These instructions can be roughly classified into basic instructions, branch instructions, load / store instructions, and system control instructions. The number of instructions is limited as described above for simplicity of explanation, but this does not limit the present invention, and the number of instructions may be further increased.

  FIG. 14 shows the configuration of the second embodiment. 1400 is a memory interface, 1401 is a data cache, 1402 is a sequencer, 1403 is an instruction cache, 1404 is a 32-bit first instruction register, 1405 is a 32-bit second instruction register, 1406 is a first decoder for the first instruction, 1408 is a second decoder for the first instruction, 1409 is a second decoder for the second instruction, 1407 is a first decoder for the second instruction, 1413 is a conflict detection circuit between the first and second instructions, Reference numeral 1410 denotes a first operation unit, 1412 denotes a second operation unit, and 1411 denotes a register file. In this embodiment, up to two instructions are read and executed in parallel during one machine cycle. FIG. 15 shows the most basic operation of the pipeline processing in this embodiment. The pipeline is composed of five stages: IF (Instruction Fetch), D (Decode), EX (Execution), T (Test), and W (Write).

  Next, the operation will be described with reference to FIG. In the IF stage, two instructions pointed to by the program counter in the sequencer 1402 are read from the instruction cache 1403 and set in the first instruction register 1404 and the second instruction register 105 via buses 1415 and 1417, respectively.

  In the D stage, the contents of the first instruction register 1404 are decoded by the first decoder 1406, and the contents of the second instruction register 1405 are decoded by the second decoder 1407. As a result, the contents of the register pointed to by the first source register field of the first instruction register 1404 are sent to the first arithmetic unit 1410 via the bus 1425, and the contents of the register pointed to by the second source register field are sent to the first arithmetic unit 1410 via the bus 1426. Is done. The contents of the register pointed to by the first source register of the second instruction register are sent to the second arithmetic unit 1412 via the bus 1427, and the contents of the register pointed to by the second source register field are sent to the second arithmetic unit 1412 via the bus 1428.

  Next, the operation of the EX stage will be described. In the EX stage, the first operation unit 1410 performs an operation between the data transmitted by the buses 1425 and 1426 in accordance with the contents of the operation code of the first instruction register. In parallel, according to the contents of the operation code of the second instruction register 1405, the second operation unit 1412 performs an operation between the data sent by the buses 1427 and 1428. The load store instruction calculates the address here.

  Next, the operation of the T stage will be described. In the T stage, the basic instruction keeps holding data. The load store instruction executes a memory access to the data cache 1401 at this stage based on the address calculated in the previous EX stage based on the address output through the bus 1429 or the bus 1431. In the case of a store instruction, data to be stored at the same time is output through a path 1437.

  Finally, the operation of the W stage will be described. In the W stage, the operation result of the first operation unit 1410 is stored in the register pointed to by the destination field of the first instruction register via the bus 1429. The operation result of the second operation unit 1412 is stored in the register pointed to by the destination field of the second instruction register via the bus 1431. Further, at the time of a load instruction, the data is stored through a bus 1430 to a register indicated by a destination field in the load instruction.

  FIG. 15 shows a flow of continuously processing the basic instructions. Two instructions are processed in one machine cycle. Also, in this example, the case where the first arithmetic unit and the second arithmetic unit always operate in parallel is illustrated.

  However, depending on the combination of the first instruction and the second instruction, both instructions may not be executed simultaneously. This is called a conflict.

  For example, the register pointed by the destination register field of the first instruction and the register pointed by the first source register field of the second instruction, or the register pointed by the second source register field S2 of the second instruction are It is time to match.

  When such a conflict occurs, the hardware is controlled to execute the instruction contained in the first instruction register in one machine cycle, and then execute the second instruction register in the next one machine cycle. . That is, each of the first instruction and the second instruction is executed over one machine cycle. FIG. 16 shows a pipeline when a conflict occurs. In this example, both the first instruction and the second instruction are addition instructions. Considering the two instructions at address 2, the first instruction adds the contents of the registers R (1) and R (2) to form the register R ( 3), and the second instruction is to add the contents of the register R (4) and the register R (3) and store the result in the register R (5). Here, the destination register R (3) of the first instruction competes with the source register R (3) of the second instruction. In such a case, as shown in FIG. 16, each instruction is executed every one machine cycle.

  That is, the first instruction is executed by the PC2, the second instruction executed in parallel is invalidated, and then the first instruction is invalidated in the next cycle, and the second instruction executed in parallel is executed. realizable. It should be noted that the collision between the destination and the source when shifted by one cycle may use a conventionally well-known short path.

  As shown in FIG. 14, the Super Scalar type RISC processor has two operation units, and in the case of the above-mentioned conflict, only one of the operation units is always used. The remaining arithmetic units perform meaningless processing.

  In a Super Scalar-type RISC processor, when various conflicts are found, it is important to detect and activate the operation unit to be used prior to the start of operation. This situation will be described in detail with reference to FIG. After the first and second instructions are read in the IF stage, various conflict checks between the first and second instructions are performed by the conflict detection circuit 1413 in the D stage.

  After various types of conflict checking, if it is determined that a conflict has occurred, only one of the arithmetic units is executed. Therefore, the arithmetic unit to be used may be activated through signals 1432 and 1433.

  If no conflict occurs, both arithmetic units are activated. If the control signal for the next machine cycle transmits the activation of the activated arithmetic unit in the latter half of one machine cycle, the arithmetic unit is continuously activated. If the activation is not transmitted, the arithmetic unit is inactivated after the end of the machine cycle.

  The case where a conflict occurs will be described in detail. When the conflict detection circuit for the first and second instructions detects a conflict, the first operation unit is first executed, so that the first arithmetic unit is notified of activation by the control signal 1435 via 1433, and is activated. Is done. At the same time, it is informed that the second arithmetic unit is not activated by the control signal 1436 via the control signal 1432. Therefore, the second arithmetic unit remains inactive, that is, remains at low power consumption.

  At this time, the signal 1434 informs the sequencer 1402 that a conflict has been detected.

  In the next cycle, to execute the second instruction, the control signal 1435 informs via the 1433 that the first arithmetic unit will not be activated. Therefore, the first arithmetic unit becomes inactive. At the same time, it is reported that the second arithmetic unit is activated from the control signal 1436 via the control signal 1432.

  As described above, in the two-instruction simultaneous processing, when various conflicts are found, the operation unit to be used is detected and activated prior to the start of operation, so that the operation unit that is not activated Can reduce power consumption, and has the effect of suppressing overall power consumption.

  FIGS. 17 to 19 show the first operation unit 1410, the second operation unit 1412, and the register file 1411 in FIG. 14, and the connection relation is omitted.

FIG. 17 shows a circuit using at least one or more differential inputs to the first and second arithmetic units, for example, an ECL circuit. Super composed of such arithmetic units
In the Scalar-type microprocessor, when a conflict is detected, the execution is performed one machine cycle at a time. Therefore, the first or second arithmetic unit actually used is activated by the signal line 1435 or 1436 and the target operation is performed in advance. Is executed by flowing a current of a predetermined value from the current source in order to perform the operation.However, since the remaining unactivated arithmetic units reduce or allow the current to flow from the current source, the power is reduced. Do not consume.

  FIGS. 18, 19, and 20 show a circuit in which the first and second arithmetic units take logic between the base and emitter of at least one or more bipolar transistors, for example, an ECL circuit or a BiCMOS circuit. . The circuit configuration itself is described in detail in JP-A-60-175167. This circuit has a drawback that when the bipolar transistor is ON, a direct current flows and the power increases. For this reason, it is effective not to consume the power of the arithmetic unit that is not used when a conflict or the like occurs. The control method is the same as that described with reference to FIG.

  The difference between FIG. 18 and FIG. 19 is that the method for reducing power is different. FIG. 18 shows that a P-channel MOS transistor is inserted between the collector side of a bipolar transistor and Vcc. The P-channel MOS transistor is turned on when turned on, and is deactivated when turned off. .

  FIG. 19 shows that the circuit is in the operating state, but when the signal 1435 or 1436 is turned on, the bipolar transistor is forcibly turned off and the current between the collector and the emitter of the bipolar transistor is stopped. This means that the DC current was forcibly cut, thereby reducing power consumption.

  FIG. 20 shows a first operation unit 1410, a second operation unit 1412, a register file 1411, and a clock distribution system for taking the timings of the first operation unit 1410, the second operation unit 1412, and the clock distribution system shown in FIG. A point to be noted in the distribution system of FIG. 20 is a clock driver A in the distribution system.

  The clock driver A independently supplies a clock to only the first operation unit 1410, the register file 1411, and the second operation unit 1412. In a Super Scalar type microprocessor configured with an arithmetic unit including such a distribution system, when a conflict is detected, the microprocessor is executed every machine cycle, but the first or second arithmetic unit not actually used is , The signal line 1435 or 1436 is used to stop the clock to a specific area of the clock distribution system. Thereby, the logic below the clock distribution system to be supplied to each block is fixed. That is, one of the two operation units is supplied with a clock and is operating, but the other one is not supplied with the clock.

  CMOS circuits and BiCMOS basic circuits have complementary characteristics and consume very little power, but consume power during transitional periods when input data changes. Stopping the clock supply means that the logic is fixed and does not change. For this reason, there is an effect that power consumption can be reduced, and the control method in FIG. 20 is effective for a circuit configured by an arithmetic unit including a CMOS circuit and a BiCMOS basic circuit.

  As described above with reference to FIGS. 17 to 20, it is possible to reduce the power consumption in the inactive state in accordance with the circuit type of the arithmetic unit. It is apparent that the power consumption can be reduced correspondingly in each of the configurations of the arithmetic units by the combination of the circuit types shown in FIGS.

  In the present embodiment, those that cannot be processed simultaneously due to a combination of conflicts between registers (for example, a combination of a load instruction and a load instruction) are given. As an example, FIG. 21 shows the combination. However, the combination is determined by hardware implementation and is not directly related to the present invention. That is, when there is a restriction on one or more combinations in FIG. 21, a conflict due to the combination of instructions is established.

Returning again to FIG. 14, the conflict detection circuit 1413 and the decoders 1406, 1408,
Other operations 1409 and 1407 will be described as a third embodiment.

  In the example described above, when various types of conflicts are found, they are detected and activated prior to the start of operation of the arithmetic unit to be used, but in the third embodiment, various types of conflicts are found. At this time, the operation unit that is not used is detected and inactivated before the operation starts. This will be described in detail with reference to FIG. After the first and second instructions are read in the IF stage, various conflict checks between the first and second instructions are checked in the D stage by the conflict detection circuit 1413 between the first and second instructions. Done. After various types of conflict checking, it is recognized that a conflict has occurred. However, since the execution is performed by only one of the arithmetic units, the remaining arithmetic units may be inactivated through signals 1432 and 1433. That is, when the conflict detection circuit between the first and second instructions detects a conflict, the first instruction is executed first, but the second instruction invalidates the first decoder for the second instruction by the signal 1432, and the second operation The unit is deactivated through control signal 1436. At this time, the signal 1434 informs the sequencer 1402 that a conflict has been detected. In the next cycle, the first decoder for the first instruction is invalidated by the output 1433 of the conflict detection circuit, and the first arithmetic unit is inactivated through the control signal 1435. In parallel with this, the second instruction is executed. The deactivated arithmetic unit is controlled so as to be activated again in the latter half of one machine cycle, so that the subsequent instruction can be executed.

  As described above, in the two-instruction simultaneous processing, whether or not there is a conflict between two instructions that may be executed simultaneously is detected, and if there is a conflict, the arithmetic unit that is not used is deactivated. This has the effect of reducing the overall power consumption.

  FIGS. 17 to 19 show the first operation unit 1410, the second operation unit 1412, and the register file 1411 in FIG. 14, and the connection relation is omitted. The manner of reducing the power consumption of each arithmetic unit is the same as in the second embodiment.

  In the Super Scalar type microprocessor constituted by such an operation unit, when a conflict is detected, the operation is executed one machine cycle at a time, but the first or second operation unit which is not actually used is a signal line 1435 or 1436. This reduces the power consumption of those not using it. At this time, the first or second arithmetic unit actually used continues to supply a current of a value provided for performing a desired operation from the current source. That is, one of them controls so that a predetermined current continues to flow, and the other one reduces power consumption.

  As in the second embodiment, it is apparent that the power consumption can be reduced correspondingly in the configuration of the arithmetic unit by the combination of the circuit forms of FIGS.

In this embodiment, the conflict between the registers has been described. As other conflicts, those which cannot be processed simultaneously by the combination of instructions as described in the second embodiment (for example, a load instruction and a load instruction) And the like). FIG. 21 shows an example of the combination. However, the combination is determined by the hardware implementation and is not directly related to the present invention, as described in the second embodiment, and one or more combinations shown in FIG. When there is a restriction on the combination of the instructions, the competition by the combination of the instructions is established.

Furthermore, in this embodiment, the combination of basic instructions has been described. However, even when the data loaded by the instruction immediately following the branch, instruction, or load instruction is used (this is called load use), the operation unit is not used. There may be meaningful processing. The present invention is also effective in this case. FIG. 22 shows the case of a branch instruction, and FIG. 23 shows the case of load use. Note that these operations can be easily inferred, and thus will not be described.

  Furthermore, when an instruction that does not actually operate the arithmetic unit, such as a NOP instruction or a system control instruction, is detected, it is also possible to deactivate the detected arithmetic unit.

  In FIG. 14, a second decoder for first instruction 1408 and a second decoder for second instruction 1409 are circuits that detect whether each instruction actually operates the arithmetic unit by decoding the instruction.

  When detected by the second decoder 1408 for the first instruction, the first operation unit 1410 is inactivated via the signal line 1435. When detected by the second decoder 1409 for the second instruction, the second operation unit 1412 is disabled via the signal line 1436. Activate. This has the effect of reducing the power consumption of the arithmetic unit.

  Further, the present embodiment is effective in another Super Scalar type control system described for a two-instruction Super Scalar type microprocessor, and is not limited to two instructions but has a simultaneous processing function of a plurality of instructions. Useful for processors. Further, it is needless to say that the present invention is not limited to the RISC processor but can be applied to the CISC processor.

  Although a single-chip microprocessor has been described as an example in the present embodiment, a semiconductor integrated circuit device such as another one-chip LSI may be used to predict the start of the operation of each functional circuit block. A similar effect can be obtained by controlling the circuit current of the block. In this case, the method of predicting the operation start and the timing of the circuit current control depend on the configuration and application of the device to be applied. However, prior to the start of the operation, the operation start is predicted so that a malfunction due to current switching or the like does not occur. By activating the functional circuit block for a certain period of time prior to the start of the operation, power consumption and normal operation are ensured, and the essence of the present embodiment that the speed of the device is increased is not different at all.

  The present embodiment can be similarly realized not only in a semiconductor integrated circuit but also in a general electronic circuit.

FIG. 1 is a block diagram showing a configuration of a microprocessor according to a first embodiment of the present invention. FIG. 3 is an explanatory diagram showing an instruction execution stage of the microprocessor. FIG. 3 is a timing chart showing operation timing of a microprocessor. FIG. 3 is a diagram showing a block showing a configuration of an access notice signal generation circuit and a timing chart showing its operation. FIG. 2 is a block diagram showing a configuration of a cache memory. FIG. 4 is a diagram showing a circuit showing a current control signal generation circuit and a timing chart showing an operation thereof. The figure which shows the time chart which shows the relationship between an access notice signal and power supply current. FIG. 2 is a diagram showing a block illustrating a configuration of a current control signal generation circuit and a timing chart illustrating an operation thereof. FIG. 2 is a diagram showing a block showing a current control signal generation circuit and a timing chart showing its operation. A circuit showing the configuration of an address buffer. FIG. 4 is a block diagram showing a memory cell peripheral circuit. FIG. 3 is a circuit diagram showing an output drive circuit. The figure which shows a list of instructions. FIG. 6 is a block diagram illustrating a configuration of a microprocessor according to a second embodiment. FIG. 9 is an explanatory diagram showing an instruction execution stage of the microprocessor shown in the second embodiment. FIG. 4 is an explanatory diagram showing an instruction execution stage of the microprocessor when various types of conflicts occur. FIG. 3 is a diagram illustrating a circuit example in an arithmetic unit. FIG. 9 is a diagram illustrating another example of a circuit in the arithmetic unit. FIG. 9 is a diagram illustrating another example of a circuit in the arithmetic unit. FIG. 2 is a diagram illustrating a circuit of a distribution system of a clock signal supplied to an arithmetic unit. FIG. 4 is an explanatory diagram showing a combination rule between instructions in simultaneous processing of two instructions. FIG. 4 is an explanatory diagram showing an instruction execution stage of a branch instruction. FIG. 4 is an explanatory diagram showing an instruction execution stage at the time of load use. FIG. 4 is an explanatory diagram showing a relationship between a change in circuit current and a noise voltage.

Explanation of reference numerals

101: Program counter, 102: Memory address register, 103: Instruction cache memory, 104: Instruction data register, 111: Memory address register, 112: Data cache memory, 113: Memory data register, 120: First instruction decoder, 130 ... second instruction decoder, 140 ... calculator, 150 ... register file, 160 ... input / output control circuit, 410 ... memory access prediction circuit, 570 ... current control signal generation circuit,
940: active circuit, 1100: memory cell, 1150: sense amplifier.

Claims (4)

A functional circuit block having a power supply system inductance L, an allowable power supply noise V _n , and a switching width ΔI of a circuit current, and a means for generating an operation start notice signal for activating the functional circuit block in advance of the operation start time T. a, and the T, L, V _n and ΔI is

A semiconductor integrated circuit device satisfying the following relationship:   The operation mode is shifted from the low power consumption mode by receiving a notice signal for predicting the start of the operation, increasing the circuit current to a predetermined value over a predetermined time from the reception of the notice signal, and executing the operation. A function circuit block having a function of reducing the circuit current to the low power consumption mode over a predetermined period of time after completion of the operation and shifting to the low power consumption mode.   A memory which is activated by an access notice signal for giving notice of an access and executes a predetermined memory operation based on an address signal, a read / write control signal, and a data input / output signal. An information processing apparatus comprising at least one of the semiconductor integrated circuit device according to claim 1, the functional circuit block according to claim 2, and the memory according to claim 3.

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