JP2004158714A - Semiconductor manufacturing apparatus and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing apparatus that can form a Ti film to stabilize the orientation of the films, and to provide a method for manufacturing a semiconductor device. <P>SOLUTION: The semiconductor apparatus is provided with a chamber 50 for titanium sputtering, a cold trap 58 that is communicated with the chamber 50 to absorb the water vapor in the chamber 50, a quadrupole mass spectrometer (water vapor quantity monitoring part) 62 that monitors the quantity of the water vapor in the chamber 50 and outputs a monitor signal of the quantity of the water vapor, and a control unit 63 for controlling the temperature of the cold trap 58. The control unit 63 changes a set temperature of the cold trap 58 according to the monitor signal so that the value of the monitor signal may be within a specified range. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor manufacturing apparatus and a semiconductor device manufacturing method. More specifically, the present invention relates to a semiconductor manufacturing apparatus for manufacturing a semiconductor device having a capacitor, and a method for manufacturing the semiconductor device.
[0002]
[Prior art]
Flash memories and ferroelectric memories (FeRAM) are known as nonvolatile memories that can store information even when the power is turned off.
[0003]
Among them, a flash memory stores information by accumulating electric charges in a floating gate of an insulated gate field effect transistor (IGFET). When writing information, a tunnel current flows through a gate insulating film. Need, and require a relatively high voltage.
[0004]
On the other hand, as shown in FIG. 21, the FeRAM has a ferroelectric capacitor 107 for storing information using the hysteresis characteristic of the ferroelectric on the insulating film 101. The ferroelectric capacitor 107 has a dielectric film 105 made of a ferroelectric material interposed between a lower electrode 104 and an upper electrode 106, and spontaneous polarization occurs in the dielectric film 105 according to a potential difference between the electrodes. This spontaneous polarization is retained even after the power is turned off, and information is read out by detecting the magnitude and polarity of the spontaneous polarization.
[0005]
As shown in the drawing, the lower electrode 104 has a two-layer structure of a Pt (platinum) film 103 and a Ti (titanium) film 102, and the Pt film 103 has the crystallinity of the dielectric film 105 thereon. To improve the characteristics of the capacitor 107. The crystallinity of the dielectric film 105 is further improved by using a highly oriented Pt film 103, that is, a high-quality Pt film having a uniform orientation. Therefore, in order to strengthen the orientation of the Pt film 103, the Ti film 102 is usually formed thereunder.
[0006]
The Ti film is used not only for the capacitor of the FeRAM but also for a metal wiring having a multilayer structure. In this case, the orientation of the Ti film depends on the amount of water vapor in the film formation atmosphere. It is known that when a film is formed, the orientation of an Al film depends on the orientation of a Ti film (for example, see Patent Document 1).
[0007]
[Patent Document 1]
JP-A-10-41383
[0008]
[Problems to be solved by the invention]
By the way, the sputtering chamber for titanium has a higher degree of vacuum than other chambers due to the gettering effect of Ti, and the amount of water vapor in the chamber tends to wither as the number of processing lots increases.
[0009]
However, when the atmosphere in the chamber is unstable, the orientation of the Ti film 102 varies for each processing lot, and there is a problem that it is difficult to stably mass-produce the FeRAM.
[0010]
Further, in the method disclosed in Japanese Patent Application Laid-Open No. 10-41383, when the water stored in the cylinder is supplied into the film forming chamber, the supply amount is mechanically adjusted by a valve. There is a problem that it is difficult to control accurately.
[0011]
The present invention has been made in view of the problems of the conventional example, and has as its object to provide a semiconductor manufacturing apparatus and a semiconductor device manufacturing method capable of forming a Ti film so that the orientation of the film is stable. And
[0012]
[Means for Solving the Problems]
The above-mentioned problem is solved by providing a chamber for titanium sputtering, a cold trap provided in communication with the chamber and adsorbing water vapor in the chamber, and a monitor signal of the amount of water vapor by monitoring the amount of water vapor in the chamber. And a control unit for controlling the temperature of the cold trap, wherein the control unit changes the set temperature of the cold trap based on the monitor signal, and the value of the monitor signal is The problem is solved by a semiconductor manufacturing apparatus characterized in that it falls within a predetermined range.
[0013]
Next, the operation of the present invention will be described.
[0014]
According to the semiconductor manufacturing apparatus of the present invention, the control unit changes the set temperature of the cold trap based on the monitor signal output from the water vapor amount monitoring unit so that the value of the monitor signal falls within a predetermined range. In addition, the amount of water vapor in the chamber is always kept in a constant range, and the intensity of the orientation of the titanium film is prevented from fluctuating due to the ultimate vacuum pressure in the chamber and the number of processing lots.
[0015]
In addition, in this apparatus, water vapor originally present in the chamber is adsorbed to the cold trap, and the amount of water vapor adsorbed there is adjusted by changing the temperature of the cold trap. Therefore, mechanical means such as a valve is used. This makes it easier to fine-tune the amount of water vapor in the chamber than in a device that supplies water vapor into the chamber.
[0016]
In particular, by using a range that guarantees the standard value of the orientation strength of the titanium film as the predetermined range of the monitor signal, a titanium film with a strong orientation is stably mass-produced.
[0017]
When the amount of water vapor in the degas in the chamber is too small, a predetermined amount of water vapor may be mixed in advance into a sputter gas cylinder, and the water vapor may be introduced into the chamber together with the sputter gas.
[0018]
Alternatively, the above-described problem is that a step of forming a base film on a semiconductor substrate and a cold trap that adsorbs water vapor are provided in communication with each other, and a water vapor amount monitoring unit that monitors the amount of water vapor in a sputtering atmosphere is provided. A sputtering step of forming a titanium film on the base film by using a chamber for titanium sputtering, wherein the temperature of the cold head is controlled based on a monitoring result of the water vapor amount monitoring unit in the sputtering step. And the amount of water vapor in the chamber is kept within a predetermined range.
[0019]
Next, the operation of the present invention will be described.
[0020]
According to the method of manufacturing a semiconductor device according to the present invention, in the sputtering process, the temperature of the cold head is changed based on the monitoring result of the water vapor amount monitoring unit, and the water vapor amount in the chamber is suppressed within a predetermined range. The orientation strength is stabilized.
[0021]
Also, by adopting a range that guarantees the standard value of the orientation strength of the titanium film as the predetermined range of the amount of water vapor, a titanium film having a strong orientation is stably mass-produced.
[0022]
Further, by forming a platinum film on such a titanium film, a platinum film having a strong orientation can be stably mass-produced. Therefore, when the ferroelectric capacitor is formed by laminating the titanium film and the platinum film as the lower electrodes and laminating the capacitor dielectric film and the upper electrode thereon, the crystallinity of the capacitor dielectric film is improved and the high quality is obtained. A stable ferroelectric capacitor is mass-produced.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a semiconductor manufacturing apparatus used in the present embodiment.
[0024]
As shown in FIG. 1, the apparatus has a titanium sputtering chamber 50, in which a heater stage 51 for mounting a semiconductor wafer W is provided. The heater stage 51 plays a role of adsorbing the semiconductor wafer W by the electrostatic chuck and heating the semiconductor wafer W to a desired temperature by heat conduction. In order to prevent sputter atoms from depositing on the inner wall of the chamber 50 during sputtering, the inner wall of the chamber 50 is covered with shields 52a to 52e as shown in the figure.
[0025]
The Ti target 54 is provided above the chamber 50 so as to face the heater stage 51, and is electrically connected to a DC power supply 55 via a backing plate 53 made of, for example, copper.
[0026]
In this apparatus, Ar is used as a sputtering gas. The Ar is stored in an Ar cylinder 65 and is introduced into the chamber 50 via an opening / closing valve 66 and a pipe 56. Although not explicitly described, an MFC (Mass Flow Controller) for adjusting the flow rate of the Ar gas is provided in the middle of the pipe 56.
[0027]
At the time of sputtering, the Ar gas is supplied into the chamber 50 as described above, and the gate valve 57 is opened, and the turbo molecular pump 59 is operated to maintain the inside of the chamber 50 at a predetermined pressure. If the pressure on the exhaust side is not lower than a predetermined pressure, the turbo-molecular pump 59 may damage a turbine or the like in the pump. Therefore, when the turbo-molecular pump 59 is operated, the dry pump 60 is always operated. The gas in the chamber 50 is exhausted from the exhaust port 64 of the dry pump 60.
[0028]
Since the pumps 59 and 60 alone cannot provide a sufficient pumping speed, a cold trap 58 is provided in front of the turbo molecular pump 59 so as to communicate with the chamber 50 in order to effectively increase the pumping speed. The cold trap 58 has, for example, an adsorbent cooled to a sufficiently low temperature, and functions to increase the evacuation speed by adsorbing degas from the chamber 50 to the adsorbent. Water vapor is effectively adsorbed by the cold trap 58 among the degass, and the water pressure in the chamber is drastically reduced in a short time. As such a cold trap, for example, CRYO TRAP manufactured by Ebara Corporation can be used.
[0029]
At the bottom of the chamber 50, a quadrupole mass spectrometer (water vapor amount monitoring unit) 62 is provided via an opening / closing valve 61. The quadrupole mass analyzer 62 monitors the amounts of various elements contained in the sputtering atmosphere and outputs monitor signals corresponding to each element. In the present embodiment, Transpector II manufactured by Inficon Corporation is used as the quadrupole mass analyzer 62.
[0030]
FIG. 5 is a graph showing the intensity of each monitor signal when the set temperature of the cold trap 58 is changed. In the graph, “MASS X” indicates the amount of the element having the mass number X, and “MASS 18” particularly indicates a monitor signal corresponding to water vapor. Since the orientation of the Ti film formed by sputtering is considered to depend on the amount of water vapor contained in the sputtering atmosphere, the following focuses only on the MASS 18 signal among various signals.
[0031]
FIG. 2 is a graph obtained by investigating the relationship between the temperature of the cold trap 58 and the MASS 18 signal. As can be understood from the figure, when the temperature of the cold trap 58 becomes high, it becomes difficult for water vapor to be adsorbed to the cold trap, so that the amount of water vapor in the chamber increases and the MASS 18 signal becomes strong. This indicates that the amount of water vapor in the chamber can be controlled by changing the temperature of the cold trap 58.
[0032]
FIG. 3 is a graph obtained by investigating the relationship between the intensity of the MASS 18 signal and the intensity of the orientation of the formed Ti film. In this study, a silicon wafer was thermally oxidized to SiO 2 ₂ A film was formed to a thickness of 100 nm, and a Ti film having a thickness of 20 nm was formed thereon by sputtering using the apparatus shown in FIG. X-ray diffraction was used to measure the strength of the orientation of the Ti film.
[0033]
As shown in FIG. 3, as the MASS 18 signal increases, that is, as the amount of water vapor increases, the X-ray diffraction intensity of the Ti film in the (002) direction increases and the X-ray diffraction intensity in the (101) direction decreases. . This means that within the measurement range of FIG. 3, as the amount of water vapor increases, the Ti film is oriented in the (002) direction as a whole, and the orientation of the Ti film becomes stronger.
[0034]
It is considered that if the orientation of the Ti film becomes strong as described above, the orientation of the Pt film becomes stronger when a Pt film is formed thereon. In order to confirm this point, the present inventor conducted the investigation shown in FIGS. 4 (a) and 4 (b).
[0035]
FIG. 4A is a graph showing a change in the integrated intensity of the X-ray diffraction light in the (002) direction of the Ti film when the temperature of the heater stage 51 is changed. In this study, SiO 2 was deposited on a silicon wafer. ₂ A film was formed to a thickness of 100 nm, and a Ti film having a thickness of 80 nm was formed thereon by a sputtering method using the apparatus shown in FIG. Note that this investigation was performed in each case where the flow rate of the Ar gas for sputtering was 30 sccm, 50 sccm, and 70 sccm.
[0036]
FIG. 4 (b) shows an investigation of the integrated intensity in the (222) direction of the Pt film in the case where a Ti film is formed by shaking the temperature of the heater stage 51 and a Pt film is formed on the Ti film in the same manner as described above. The graph in the case of doing is shown. However, in this investigation, the thickness of the Ti film was set to 20 nm, and the thickness of Pt was set to 175 nm. Further, this investigation was performed in each case where the flow rate of Ar, which is a sputtering gas for the Ti film, was 30 sccm and 50 sccm.
[0037]
Comparing FIG. 4A and FIG. 4B, it can be seen that as the integrated intensity of the Ti film in the (002) direction increases, the integral intensity of the Pt film in the (222) direction also increases. This means, in other words, that the stronger the orientation of the Ti film, the stronger the orientation of the Pt film thereon.
[0038]
From these results, it is understood that in order to strengthen the orientation of the Pt film, the amount of water vapor in the titanium chamber should be set to an amount that makes the orientation of the Ti film as strong as possible, and the orientation of the Ti film should be enhanced. Is done. However, in the actual mass production process, it is not necessary to maximize the orientation of the Ti film, and a standard value of the strength of the orientation of the Ti film is determined in advance, and the above-mentioned water vapor amount and the MASS 18 signal are converted to the standard values. May be kept within a predetermined range that guarantees the following.
[0039]
Furthermore, if the amount of water vapor fluctuates during sputtering, or fluctuates depending on the ultimate vacuum pressure of the chamber or the number of processing lots, a Ti film of stable quality cannot be mass-produced. It also needs to be constantly stabilized.
[0040]
Therefore, in the present embodiment, as shown in FIG. 1, the MASS 18 signal is fed back to the control unit 63, and the control unit 63 determines whether or not the MASS 18 signal is within the above-described predetermined range. The controller 63 sequentially changes the temperature of the cold head 58 based on the above, so that the amount of water vapor in the chamber 50 always falls within a predetermined range. The predetermined range of the MASS 18 signal is, for example, 5 × 10 ^-9 It is preferable to adopt the above range, and in this case, it is preferable that the temperature of the cold trap 58 be in the range of -150 ° C to -100 ° C. Further, as such a control unit 63, for example, a commercially available PC (Personal Computer) can be used.
[0041]
As a result, a Ti film having a strong orientation can be formed, and the film quality of the Ti film can be prevented from fluctuating depending on the ultimate vacuum pressure of the chamber and the number of processing lots, thereby enabling stable mass production of semiconductor devices. Becomes possible.
[0042]
In addition, in this method, a small amount of water vapor contained in the degas in the chamber 50 is adsorbed on the cold trap 58, and the amount of adsorption is finely adjusted by the temperature of the cold trap 58. The amount of water vapor in the chamber 50 can be controlled more accurately than in the method of mechanically controlling the amount of water vapor with a valve.
[0043]
The cold trap 58 only adsorbs the water vapor in the chamber 50 and does not increase the water vapor. Therefore, if the amount of water vapor originally contained in the degas of the chamber 50 is less than the above-mentioned predetermined range, the cold trap 58 No matter how the temperature of the trap 58 is controlled, the inside of the chamber 50 does not have an optimal amount of water vapor.
[0044]
In this case, for example, a small amount of water may be previously filled together with Ar when filling the Ar cylinder 65 so that a certain amount of water vapor is supplied from the Ar cylinder 65 into the chamber 50. In this case, it is preferable to fill the Ar cylinder 65 with water so that Ar immediately before being introduced into the chamber 50 contains about 50% of water vapor in relative humidity.
[0045]
Next, a method of manufacturing the FeRAM to which the above method is applied will be described with reference to FIGS. 6 to 20 are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the present embodiment.
[0046]
First, steps required until a sectional structure shown in FIG.
[0047]
As shown in FIG. 6, LOCOS (Local Oxidation of Silicon) is formed as an element isolation insulating film 2 on a part of the surface of a p-type silicon (semiconductor) substrate 1. As the element isolation insulating film 2, another element isolation structure of LOCOS, for example, STI (Shallow Trench Isolation) may be adopted.
[0048]
After the element isolation insulating film 2 is formed, a p-type impurity and an n-type impurity are selectively introduced into predetermined active regions in the memory cell region A and the peripheral circuit region B of the silicon substrate 1 to form a p-well 3 and an n-well 4 is formed. Although not shown in FIG. 6, a p-well is also formed in the peripheral circuit region B in order to form a CMOS.
[0049]
Thereafter, the surface of the active region of the silicon substrate 1 is thermally oxidized to form a silicon oxide film as the gate insulating film 5.
[0050]
Next, an amorphous silicon film and a tungsten silicide film are formed on the entire upper surface of the silicon substrate 1, and the amorphous silicon film and the tungsten silicide film are patterned into a predetermined shape by photolithography to form gate electrodes 6a, 6b, 6c. And the wiring 7 are formed. Note that a polysilicon film may be formed instead of the amorphous silicon film.
[0051]
In the memory cell region A, two gate electrodes 6a and 6b are arranged substantially in parallel on one p-well 3, and these gate electrodes 6a and 6b constitute a part of the word line WL.
[0052]
Next, in the p well 3 of the memory cell region A, n-type impurities are ion-implanted on both sides of the gate electrodes 6a and 6b to form n-type impurity diffusion regions 8a and 8b serving as the source and drain of the n-channel MOS transistor. I do. At the same time, an n-type impurity diffusion region may be formed in a p-well (not shown) of the peripheral circuit region B. Subsequently, in the n-well 4 of the peripheral circuit region B, a p-type impurity is ion-implanted on both sides of the gate electrode 6c to form a p-type impurity diffusion region 9 serving as a source / drain of the p-channel MOS transistor. The implantation of the n-type impurity and the implantation of the p-type impurity are performed using a resist pattern.
[0053]
Thereafter, an insulating film is formed on the entire surface of the silicon substrate 1, and the insulating film is etched back to leave the sidewalls 10 only on both sides of the gate electrodes 6a, 6b, 6c and the wiring 7. As the insulating film, for example, silicon oxide (SiO 2) is formed by a CVD method. ₂ ) Is formed.
[0054]
Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed as a cover film on the entire surface of the silicon substrate 1 by a plasma CVD method. Thereafter, silicon oxide (SiO 2) is formed on the cover film by a plasma CVD method using TEOS gas. ₂ ) Is grown to a thickness of about 1.0 μm. These SiON film and SiO ₂ The film forms the first interlayer insulating film 11.
[0055]
Subsequently, as a densification treatment of the first interlayer insulating film 11, the first interlayer insulating film 11 is heat-treated at a temperature of 700 ° C. for 30 minutes in a nitrogen atmosphere at normal pressure. Thereafter, the first interlayer insulating film 11 is polished by a chemical mechanical polishing (hereinafter, referred to as CMP) method to flatten the upper surface of the first interlayer insulating film 11.
[0056]
Next, contact holes 11a having a depth reaching n-type impurity diffusion regions 8a and 8b on both sides of gate electrodes 6a and 6b in memory cell region A and p-type impurity diffusion layer 9 in peripheral circuit region B are respectively formed by photolithography. 11d and via holes 11e having a depth reaching the wiring 7 in the peripheral circuit region B are formed in the first interlayer insulating film 11, respectively. Thereafter, a 20 nm-thick Ti (titanium) thin film and a 50 nm-thick TiN (titanium nitride) thin film are sequentially formed on the upper surface of the first interlayer insulating film 11 and the inner surfaces of the holes 11a to 11f by a sputtering method. Further, tungsten (W) is grown on the TiN thin film by the CVD method. As a result, a tungsten film is buried in the contact holes 11a to 11d and the via holes 11e.
[0057]
Thereafter, the tungsten film, the TiN thin film and the Ti thin film are polished by the CMP method until the upper surface of the first interlayer insulating film 11 is exposed. Tungsten films and the like remaining in the holes 11a to 17e after the polishing are used as conductive plugs 13a to 13e for electrically connecting a wiring described later to the impurity diffusion regions 8a, 8b, 9 and the wiring 14.
[0058]
In one p-well 3 of memory cell region A, first conductive plug 13a on n-type impurity diffusion region 8a sandwiched between two gate electrodes 6a and 6b is connected to a bit line described later. The second conductive plugs 13b on both sides of the conductive plug are connected to a capacitor described later.
[0059]
Next, in order to prevent oxidation of the conductive plugs 13a to 13e, an SiON film 14 having a thickness of 100 nm is formed on the first interlayer insulating film 11 and the conductive plugs 13a to 13e by a plasma CVD method. Further, using TEOS as a film forming gas, ₂ A film (base film) 15 is formed to a thickness of 150 nm. Then, the SiON film 14, SiO ₂ The membrane 15 is heated at a temperature of 650-700C for degassing.
[0060]
Next, steps required until a structure illustrated in FIG.
[0061]
First, the p-type silicon substrate 1 is placed on the heater stage 51 of the semiconductor manufacturing apparatus shown in FIG. 1, the Ar flow rate is set to 100 sccm, and the power of the DC power supply 55 is set to 2.06 kW. However, the heater stage 51 is not heated and is kept at room temperature. At the same time, by sequentially controlling the temperature of the cold trap 58 while feeding back the MASS 18 signal to the control unit 63, the amount of water vapor in the chamber 50 can be controlled to ensure the standard value of the orientation strength of the Ti film. Keep within a predetermined range. At this time, the value of the MASS 18 signal is 5 × 10 ^-9 Preferably, the temperature of the cold trap 58 is in the range of −150 ° C. to −100 ° C.
[0062]
By maintaining the above-mentioned conditions for a predetermined time, as shown in FIG. ₂ A film is formed on the film 15 to a thickness of about 20 nm by a sputtering method.
[0063]
Next, as shown in FIG. 8, a Pt film 35 is formed to a thickness of about 175 nm on the Ti film 16 by a sputtering method under the conditions of a film forming temperature of 100 ° C., a power of 1.04 kW, and an Ar flow rate of 100 sccm for sputtering. It is used as the lower electrode conductive film 36 together with the Ti film 16. Since the orientation of the Ti film 16 is strong, the orientation of the Pt film 35 is also strong.
[0064]
Subsequently, steps required until a structure illustrated in FIG. 9 is formed will be described.
[0065]
First, the Ar flow rate for sputtering is set to 15 to 25 sccm, the power is set to 1.0 kw, and lead zirconate titanate (PZT; Pb (Zr _1-x Ti _x ) O ₃ ) Is formed to a thickness of about 200 nm at room temperature by an RF sputtering method, which is used as a PZT film 17. In order to keep the amount of Pb in the PZT film 17 within the standard, the relationship between the pb amount and the chamber pressure may be checked in advance, and the chamber pressure may be adjusted by adjusting the Ar flow rate.
[0066]
As a method of forming the ferroelectric material film, there are a spin-on method, a sol-gel method, a MOD (Metal Organo Deposition) method, and a MOCVD method in addition to the above-described sputtering method. In addition to PZT, ferroelectric materials include lanthanum lead zirconate titanate (PLZT) in which PZT is doped with La, and SrBi. ₂ (Ta _x Nb _1-x ) ₂ O ₉ (However, 0 <x <1), Bi ₄ Ti ₂ O ₁₂ and so on. Further, these materials may be doped with Ca or Sr.
[0067]
Then, as a crystallization process of the PZT film 17, RTA (Rapid Thermal Annealing) is performed in an atmosphere containing about 2.5% of oxygen in argon (Ar) at a temperature of 600 ° C. for 90 seconds.
[0068]
Furthermore, power 1.04kw, Ar / O ₂ Flow rate 100/100 sccm, film formation time 29 seconds, first step, power 2.05 kw, Ar / O ₂ By a sputtering method in which the flow rate is 100/100 sccm and the film formation time is 22 seconds as a second step, the total thickness of the IrO film is about 200 nm. _x A film is formed on the PZT film 17 at room temperature and is used as a conductive film 18 for an upper electrode. By forming the upper electrode conductive film 18 in two steps in this way, it is possible to prevent the upper electrode conductive film 18 from growing abnormally and generating hillocks.
[0069]
Next, steps required until a structure shown in FIG.
[0070]
First, after the upper electrode 18a is formed by patterning the conductive film 18 for the upper electrode, in order to remove the damage of the PZT film 17 which is a ferroelectric substance, the PZT film is formed at 650 ° C. for 60 minutes in an oxygen atmosphere. 17 is subjected to recovery annealing.
[0071]
Further, after patterning the PZT film 17 and leaving the dielectric film 17a of the capacitor at least under the upper electrode 18a, the dielectric film 17a is annealed in an oxygen atmosphere at, for example, 350 ° C. for 60 minutes.
[0072]
Subsequently, as shown in FIG. 11, aluminum oxide (Al) is formed on the upper electrode 18a, the dielectric film 17a, and the conductive film 36 for the lower electrode by sputtering. ₂ O ₃ ) Is formed to a thickness of 50 nm. Thereafter, in order to reduce damage to the dielectric film 17a caused by sputtering, the dielectric film 17a is annealed in an oxygen atmosphere at 550 ° C. for 60 minutes, for example.
[0073]
Thereafter, as shown in FIG. 12, the lower electrode conductive film 36 is patterned to form a lower electrode 36a. The first capacitor protection insulating film 19 is patterned together with the lower electrode conductive film 36.
[0074]
Thus, the ferroelectric capacitor 20 is constituted by the upper electrode 18a, the dielectric film 17a, and the lower electrode 36a. Subsequently, the ferroelectric capacitor 20 is annealed in an oxygen atmosphere at 350 ° C. for 30 minutes.
[0075]
Next, steps required until a structure illustrated in FIG.
[0076]
First, the ferroelectric capacitor 20 and SiO ₂ A second interlayer insulating film 21 is formed on the entire surface of the film 15. The second interlayer insulating film 21 is first formed in a two-layer structure of an insulating film having a thickness of about 480 nm formed using TEOS and an SOG film having a thickness of about 90 nm formed thereon. After that, the second interlayer insulating film 21 is etched back to a thickness of about 300 nm to a thickness of about 270 nm.
[0077]
Then, at a temperature of 350 ° C., N ₂ Plasma annealing is performed on the second interlayer insulating film 21 and various films thereunder using O gas. In this plasma annealing, a silicon substrate 1 is placed in a chamber of a plasma generator, and N 2 is placed in the chamber. ₂ O gas at 700 sccm, N ₂ A gas is introduced at a flow rate of 200 sccm, respectively, and the second interlayer insulating film 21 and various films thereunder are exposed to plasma at a substrate temperature of 450 ° C. or less for 1 minute or more. As a result, nitrogen penetrates from the surface of the second interlayer insulating film 21 to a deep position, thereby preventing the penetration of moisture. Hereafter, this process is called N ₂ Called O plasma treatment. In this embodiment, for example, 350 ° C. and 2 minutes are selected as the heating temperature and the heating time.
[0078]
Next, steps required until a structure illustrated in FIG.
[0079]
First, a first contact hole 21a is formed on the upper electrode 18a of the ferroelectric capacitor 20 in the second interlayer insulating film 21 by photolithography. At the same time, a contact hole (not shown) is formed also on the contact region of the lower electrode 36a arranged in a direction perpendicular to the figure. After that, recovery annealing is performed on the dielectric film 17a. Specifically, heating is performed at a temperature of 550 ° C. for 60 minutes in an oxygen atmosphere.
[0080]
Next, the second interlayer insulating film 21, SiO 2 ₂ The film 15 and the SiON film 14 are patterned by photolithography to form second contact holes 21b on the second conductive plugs 13b near both ends of the p-well 3 in the memory cell region A, respectively. The conductive plug 13b is exposed. Then, a TiN film having a thickness of 125 nm is formed on the second interlayer insulating film 21 and in the contact holes 21a and 21b by a sputtering method. Subsequently, by patterning the TiN film by photolithography, the second conductive plug 18b and the upper electrode 18a of the ferroelectric capacitor 20 are electrically connected through the contact holes 21a and 21b in the memory cell region A. Local wiring 22a is formed. After that, the second interlayer insulating film 21 is subjected to nitrogen (N ₂ ) Heat at 350 ° C. for 30 minutes in an atmosphere.
[0081]
Further, a second capacitor protection insulating film 23 made of aluminum oxide is formed to a thickness of 20 nm on the local wiring 22a and the second interlayer insulating film 21 by a sputtering method.
[0082]
Subsequently, a silicon oxide film having a thickness of about 300 nm is formed on the local wiring 22a and the second interlayer insulating film 21 by a plasma CVD method using TEOS gas, and this silicon oxide film is formed on the third interlayer insulating film 21. The insulating film 24 is used. Then, N ₂ The third interlayer insulating film 24 is modified by O plasma processing. This N ₂ The condition of the O plasma treatment is as follows. ₂ The conditions are the same as those of the O plasma treatment.
[0083]
Next, steps required until a structure illustrated in FIG.
[0084]
First, a portion from the third interlayer insulating film 24 in the memory cell region A to the SiON film 14 therebelow is patterned by photolithography, so that a contact is made on the first conductive plug 13a at the center position of the p-well 3. A hole 24a is formed. At the same time, contact holes 24c to 24e are also formed on the conductive plugs 13c to 13e in the peripheral circuit region B.
[0085]
Further, a 20-nm thick Ti film, a 50-nm thick TiN film, a 600-nm-thick Al-Cu film, a 5-nm-thick Ti film on the third interlayer insulating film 24 and in the contact holes 24c to 24e. By sequentially laminating five layers of 150-nm-thick TiN films and patterning these metal films, bit lines 25a are formed in the memory cell region A, and wires 25b, 25c, and 25d are formed in the peripheral circuit region B. I do. The Al-Cu film contains, for example, 0.5% of Cu. The bit line 25a and the wirings 25b, 25c, 25d are first-layer aluminum wirings.
[0086]
Next, a SiO 2 film having a thickness of about 2.3 μm was formed by a plasma CVD method using TEOS gas. ₂ Is formed on the third interlayer insulating film 24, the bit lines 25a, and the wirings 25b to 25d.
[0087]
Thereafter, in order to flatten the fourth interlayer insulating film 26, a step of polishing the upper surface by a CMP method is employed. The polishing amount is about 1.2 μm. Then, N ₂ The fourth interlayer insulating film 26 is modified by O plasma processing. This N ₂ The condition of the O plasma treatment is as follows. ₂ The conditions are the same as those of the O plasma treatment.
[0088]
Next, as shown in FIG. 16, a redeposited interlayer insulating film 27 is formed on the interlayer insulating film 26 to a thickness of about 300 nm by a plasma CVD method using TEOS. Then N ₂ The redeposition interlayer insulating film 27 is modified by O plasma processing. This N ₂ The condition of the O plasma treatment is as follows. ₂ The conditions are the same as those of the O plasma treatment.
[0089]
Next, steps required until a structure illustrated in FIG.
[0090]
First, the re-deposited interlayer insulating film 27 and the fourth interlayer insulating film 26 are patterned by photolithography to form a via hole 26a reaching the first-layer aluminum wiring, for example, the wiring 25c in the peripheral circuit region B.
[0091]
Subsequently, a 20-nm-thick Ti film and a 50-nm-thick TiN film are sequentially formed on the inner surface of the via hole 26a and the upper surface of the redeposited interlayer insulating film 27 by sputtering, and these films are used as a glue layer 29a. Then, WF ₆ (Tungsten hexafluoride) gas and SiH ₄ (Silane) gas and H ₂ A tungsten film 29b is formed on the glue layer 29a at a growth temperature of 370 ° C. using (hydrogen).
[0092]
Subsequently, the tungsten film 29b is removed by etch back, and is left only in the via hole 26a. At this time, the glue layer 29a is not removed. Here, the tungsten film 29b remaining in the via hole 26a is used as the conductive plug 28c.
[0093]
After that, an Al-Cu film 29c having a thickness of 600 nm and a TiN film 29d having a thickness of 150 nm are formed on the glue layer 29a and the conductive plug 28c. Here, the Al-Cu film 29c contains 3% of Cu.
[0094]
Next, a metal wiring 30 is formed in the peripheral circuit region B by patterning the multilayer metal film including the glue layer 29a, the Al—Cu film 29c, and the TiN film 29d.
[0095]
Next, as shown in FIG. 18, a first cover film 32 made of silicon oxide having a thickness of 100 nm is formed on the metal wiring 30 and the redeposited interlayer insulating film 27 by a plasma CVD method using a TEOS gas. After that, the first cover film 32 is ₂ O plasma treatment is performed. That N ₂ The condition of the O plasma treatment is as follows. ₂ The conditions are the same as those of the O plasma treatment.
[0096]
Next, as shown in FIG. 19, a second cover film 33 made of silicon nitride having a thickness of 350 nm is formed on the first cover film 32 by a CVD method. Subsequently, in a region near the outermost periphery of the chip region (semiconductor device chip region) of the silicon substrate 1, the first and second cover films 32 and 33 are patterned by photolithography to form a second-layer aluminum wiring (not shown). Is formed (not shown).
[0097]
Thereafter, as shown in FIG. 20, a polyimide resin 34 is applied on the second cover film 33 to prevent cracking during packaging, and a bonding opening (not shown) is formed in the polyimide resin 34. Thereafter, the polyimide resin 34 is cured at a temperature of 250 ° C. Thus, the FeRAM is completed.
[0098]
According to the manufacturing method of FeRAM described above, when forming the Ti film 16 for the lower electrode 36a, the amount of water vapor in the chamber is monitored, and the amount of water vapor is guaranteed to the standard value of the orientation strength of the Ti film. Since the control is performed so as to fall within a predetermined range as described above, the amount of water vapor in the chamber is stabilized, and the FeRAM can be stably mass-produced.
[0099]
In addition, since the orientation of the Ti film 16 becomes stronger, the orientation of the Pt film 35 thereon also becomes stronger, and the crystallinity of the dielectric film 17a on the Pt film 35 becomes better. Can be improved.
[0100]
Hereinafter, features of the present invention will be additionally described.
[0101]
(Supplementary Note 1) A chamber for titanium sputtering,
A cold trap provided in communication with the chamber and adsorbing water vapor in the chamber;
A water vapor amount monitoring unit that monitors the water vapor amount in the chamber and outputs a monitor signal of the water vapor amount;
A control unit for controlling the temperature of the cold trap,
With
The semiconductor manufacturing apparatus, wherein the control unit changes a set temperature of the cold trap based on the monitor signal so that a value of the monitor signal falls within a predetermined range.
[0102]
(Supplementary Note 2) The semiconductor manufacturing apparatus according to Supplementary Note 1, wherein the predetermined range of the value of the monitor signal is a range that guarantees a standard value of the strength of orientation of the titanium film.
[0103]
(Supplementary Note 3) The semiconductor manufacturing apparatus according to Supplementary Note 1 or 2, wherein the water vapor amount monitoring unit is a quadrupole mass analyzer.
[0104]
(Supplementary Note 4) A cylinder for a sputtering gas into which a predetermined amount of water vapor is previously mixed,
4. The semiconductor manufacturing apparatus according to any one of supplementary notes 1 to 3, further comprising a pipe for guiding the sputtering gas in the cylinder into the chamber.
[0105]
(Supplementary Note 5) A step of forming a base film on the semiconductor substrate;
A cold trap for adsorbing water vapor is provided in communication, and a titanium film is provided on the base film by using a chamber for titanium sputtering provided with a water vapor amount monitoring unit for monitoring the amount of water vapor in the sputtering atmosphere. A sputtering process for forming;
Has,
The method of manufacturing a semiconductor device, wherein, in the sputtering step, a temperature of the cold head is changed based on a monitoring result of the water vapor amount monitoring unit to suppress a water vapor amount in the chamber within a predetermined range.
[0106]
(Supplementary Note 6) The method for manufacturing a semiconductor device according to Supplementary Note 5, wherein a range that guarantees a standard value of the strength of orientation of the titanium film is adopted as the predetermined range of the amount of water vapor.
[0107]
(Supplementary Note 7) a step of forming a platinum film on the titanium film;
Forming a ferroelectric film on the platinum film,
Forming a conductive film on the ferroelectric film,
By patterning the titanium film, the platinum film, the ferroelectric film, and the conductive film, a lower electrode having the titanium film and the platinum film; a capacitor dielectric film made of the ferroelectric; 7. The method of manufacturing a semiconductor device according to Supplementary Note 5 or 6, further comprising a step of forming a ferroelectric capacitor including an upper electrode made of a conductive film.
[0108]
【The invention's effect】
As described above, according to the semiconductor manufacturing apparatus of the present invention, the control unit changes the set temperature of the cold trap based on the monitor signal output from the water vapor amount monitoring unit, and the value of the monitor signal falls within a predetermined range. Therefore, it is possible to prevent the strength of the orientation of the titanium film from fluctuating, and mass-produce a stable quality titanium film.
[0109]
In addition, in this device, the amount of water vapor in the chamber is finely adjusted by changing the temperature of the cold trap. Can be increased.
[0110]
Furthermore, by using a range that guarantees the standard value of the orientation strength of the titanium film as the predetermined range of the monitor signal, a titanium film having a strong orientation can be stably mass-produced.
[0111]
Further, according to the method of manufacturing a semiconductor device according to the present invention, when forming a titanium film by sputtering, the amount of water vapor in the chamber is suppressed within a predetermined range by changing the temperature of the cold head. In addition, the strength of the orientation of the titanium film can be stabilized.
[0112]
Further, since a range that guarantees the standard value of the orientation strength of the titanium film is adopted as the predetermined range of the amount of water vapor, a titanium film having a strong orientation can be stably mass-produced.
[0113]
Therefore, when a platinum film is formed on the titanium film and a ferroelectric capacitor using the titanium film and the platinum film as lower electrodes is manufactured, the characteristics of the ferroelectric capacitor are improved, and the ferroelectric capacitor is stabilized. And can be mass-produced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention.
FIG. 2 is a graph obtained by investigating a relationship between a temperature of a cold trap and a MASS 18 signal in the embodiment of the present invention.
FIG. 3 is a graph obtained by investigating the relationship between the intensity of a MASS 18 signal and the intensity of the orientation of a formed Ti film in the embodiment of the present invention.
FIG. 4A is a graph showing a change in the integrated intensity of the X-ray diffraction light of the Ti film in the (002) direction when the temperature of the heater stage is varied in the embodiment of the present invention. FIG. 4B is a graph showing a change in the integrated intensity of the X-ray diffraction light of the Pt film on the Ti film in the (222) direction when the temperature of the heater stage is varied.
FIG. 5 is a graph showing the intensity of each monitor signal when the set temperature of the cold trap is changed in the embodiment of the present invention.
FIG. 6 is a sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 7 is a sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 8 is a sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 9 is a sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 10 is a sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 11 is a sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 12 is a sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 13 is a sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 14 is a sectional view (No. 9) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 15 is a sectional view (part 10) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 16 is a sectional view (part 11) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 17 is a sectional view (part 12) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 18 is a sectional view (part 13) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 19 is a sectional view (part 14) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 20 is a sectional view (part 15) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 21 is a sectional view of a capacitor of a conventional FeRAM.
[Explanation of symbols]
A: memory cell region, B: peripheral circuit region, W: wafer, 1 ... silicon (semiconductor) substrate, 2 ... element isolation insulating film, 3 ... p well, 4 ... n well, 5 ... gate insulating film, 6a to 6c ... Gate electrode, 7 extraction electrode, 8a, 8b n-type impurity diffusion region, 9 p-type impurity diffusion region, 10 sidewall, 11 interlayer insulating film, 11a-11e hole, 13a-13e contact plug .. 14 SiON film, 15 SiO ₂ Film, 16 ... Ti film, 36a ... lower electrode, 17 ... ferroelectric film, 17a ... dielectric film, 18 ... conductive film for upper electrode, 18a ... upper electrode, 19 ... first capacitor protective insulating film, 20 ... Capacitor, 21: interlayer insulating film, 22a: local wiring, 23: second capacitor protective insulating film, 24: interlayer insulating film, 24a to 24f: hole, 25a: bit line, 25b to 25d: wiring, 26: interlayer insulation Film, 26c: hole, 27: redeposited interlayer insulating film, 28c: conductive plug, 30: metal wiring, 32, 33: cover film, 34: polyimide resin, 50: chamber, 51: heater stage, 52a to 52e Shield, 53 Backing plate, 54 Ti target, 55 DC power supply, 56 Piping, 57 Gate valve, 58 Cold trap, 59 Turbo molecular pump , 60: dry pump, 61, 66: open / close valve, 62: quadrupole mass spectrometer, 63: control unit, 64: exhaust port, 65: Ar cylinder.

Claims (5)

A chamber for titanium sputtering,
A cold trap provided in communication with the chamber and adsorbing water vapor in the chamber;
A water vapor amount monitoring unit that monitors the water vapor amount in the chamber and outputs a monitor signal of the water vapor amount;
A control unit for controlling the temperature of the cold trap,
With
The semiconductor manufacturing apparatus, wherein the control unit changes a set temperature of the cold trap based on the monitor signal so that a value of the monitor signal falls within a predetermined range. 2. The semiconductor manufacturing apparatus according to claim 1, wherein the predetermined range of the value of the monitor signal is a range that guarantees a standard value of the orientation strength of the titanium film. 3. The semiconductor manufacturing apparatus according to claim 1, wherein the water vapor amount monitoring unit is a quadrupole mass analyzer. A cylinder for a sputtering gas in which a predetermined amount of water vapor is previously mixed,
4. The semiconductor manufacturing apparatus according to claim 1, further comprising a pipe for guiding the sputtering gas in the cylinder into the chamber. Forming a base film on the semiconductor substrate;
A cold trap for adsorbing water vapor is provided in communication, and a titanium film is provided on the base film by using a chamber for titanium sputtering provided with a water vapor amount monitoring unit for monitoring the amount of water vapor in the sputtering atmosphere. A sputtering process for forming;
Has,
The method of manufacturing a semiconductor device, wherein, in the sputtering step, a temperature of the cold head is changed based on a monitoring result of the water vapor amount monitoring unit to suppress a water vapor amount in the chamber within a predetermined range.

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