JP2004158018A - レジスタ・リネーム回路の半導体フロアプランのレイアウト・システム - Google Patents
レジスタ・リネーム回路の半導体フロアプランのレイアウト・システム Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000011159 matrix material Substances 0.000 claims abstract 2
- 230000001419 dependent effect Effects 0.000 abstract description 3
- 239000000872 buffer Substances 0.000 description 11
- 230000006870 function Effects 0.000 description 4
- 101100238326 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SPO21 gene Proteins 0.000 description 2
- 101100317161 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS1 gene Proteins 0.000 description 2
- 101100150130 Schizosaccharomyces pombe (strain 972 / ATCC 24843) spo15 gene Proteins 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30141—Implementation provisions of register files, e.g. ports
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
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Abstract
【解決手段】 半導体チップ上に、チップ面積の省面積化を計るよう、レジスタ・リネーミング回路のフロアプランをレイアウトするためのシステムであって、前記システムが、データ従属性チェッカー108を行列状に配置する第1手段と、前記第1手段に関連し、ひとつもしくはそれ以上の前記行中に空間的にチャネルを規定するように、前記タグ・アサイメント・ロジック122を1つもしくはそれ以上の前記レイアウト領域中に配置するための第2手段と、前記第2手段に関連し、前記さらなる出力ラインを、その長さが最小になるように前記チャネル中に配線するための第3手段と、を有する。
【選択図】 図1
Description
*「スーパースケーラーRISC命令スケジューリング」、出願番号07/860,719、本出願と同時に出願 (Attorney Docket No. SPO35)、
*「高性能RISCマイクロプロセサ・アーキテクチャ」、出願番号07/817,810、1992年8月1日出願 (Attorney Docket No.SPO15)、
*「拡張性を持つRISCマイクロプロセサ・アーキテクチャ」、出願番号07/817,809、1992年8月1日出願(Attorney DocketNo.SPO21)。
上記出願の開示を参考文献として本明細書に含める。
Mike Johnson,Superscalar Microprocessor Design(Prentice−Hall, Inc., Englewood Cliffs, New Jersey, 1991) John L. Hennessy et al,.Computer Architecture−A Quantitative Approach (Morgan Kaufmann Publishers, Inc., San Mateo, California, 1990)
add R0,Rl,R2 (0)
add R0,R2,R3 (1)
add R4,R5,R2 (2)
add R2,R3,R4 (3)
命令0−3の各命令の最初の2つのレジスタはソース・レジスタで、各命令の最後のレジスタは宛先レジスタである。例えば、R0とR1は命令0に対するソース・レジスタで、R2は宛先レジスタである。命令0はレジスタ0とレジスタ1の内容を加算しその結果をR2に格納する。この例の命令1−3に対し、すべての従属性を評価するのに以下のような比較が必要となる:
I1S1,I1S2 vs. I0D
I2S1,I2S2 vs. I1D,I0D
13S1,13S2 vs. I2D,I1D,I0D
上の読み方は次のようである:IXRS1は命令Xのソース(入力)No.1のアドレスで;IXRS2は命令Xのソース(入力)No.2のアドレスで;IXDは命令Xの宛先(出力)アドレスである。
I5S1,I5S2 vs. I4D,I3D,I2D,I1D,I0D
I6S1,I6S2 vs.
I5D,I4D,I3D,I2D,I1D,I0D
I7S1,I7S2 vs.
I6D,I5D,I4D,I3D,I2D,I1D,I0D
従属性チェックを行うのにRRC112が取り扱わなくてはならないいくつかの特別の場合がある。最初のものは、同一のレジスタを入力と出力の双方に用いるような命令である。従ってRRC112はこのソース・レジスタ・アドレスを、それより以前のすべての命令の宛先アドレスと、比較しなくてはならない。従って、命令7に対して以下の比較が必要となる:
I7S1,I7S2,I7S/D vs.
I6D,I5D,I4D,I3D,I2D,I1D,I0D
他の特別のケースは、プログラムが64ビットの出力を発生する命令(ロングワード動作と呼ぶ)を含む場合である。この種の命令にはその結果を格納するのに2つのレジスタが必要となる。本実施例ではこれらのレジスタは逐次的であるとする。従って、例えば、RRCl12が命令4の従属性をチェックしており、命令1がロングワード動作であれば、以下の比較を行うこととなる:
I4S1,I4S2 vs.
I3D,I2D,I1D,I1D+1,I0D
時には命令に宛先レジスタがない場合がある。この場合RRC112は宛先レジスタを持たない命令とそれ以後の命令との間の従属性を無視しなくてはならない。さらに命令は、ただ1つの有効なソース・レジスタさえ持たない場合がある。その時にはRRC112は使用しないソース・レジスタ(普通S2)とそれ以前のすべての命令との間の従属性を無視しなくてはならない。
Claims (1)
- 半導体チップ上に、チップ面積の省面積化を計るよう、レジスタ・リネーミング回路のフロアプランをレイアウトするためのシステムであって、前記システムが、
(1)データ従属性チェッカーを行列状に配置する第1手段であって、前記配置が、前記行の前記データ従属性チェッカーの隣り合う領域の間にレイアウト領域を規定し、さらに、従属性情報をタグ・アサイメント・ロジックへ転送するための出力ラインが前記データ従属性チェッカーに含まれる、前記第1手段と、
(2)前記第1手段に関連し、ひとつもしくはそれ以上の前記行中に空間的にチャネルを規定するように、前記タグ・アサイメント・ロジックを1つもしくはそれ以上の前記レイアウト領域中に配置するための第2手段であって、前記チャネルが前記行とほぼ直角に走り、タグ情報を前記レイアウト領域から転送するためのさらなる出力ラインが前記タグ・アサイメント・ロジックに含まれる前記第2手段と、
(3)前記第2手段に関連し、前記さらなる出力ラインを、その長さが最小になるように前記チャネル中に配線するための第3手段と、
を有することを特長とする半導体フロアプランのレイアウト・システム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/860,718 US5371684A (en) | 1992-03-31 | 1992-03-31 | Semiconductor floor plan for a register renaming circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP51729593A Division JP3555140B2 (ja) | 1992-03-31 | 1993-03-26 | レジスタリネーム回路の半導体フロアプランと方法 |
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JP2003428567A Division JP3724582B2 (ja) | 1992-03-31 | 2003-12-25 | 命令実行ユニットのためのレジスタ・リネーミング回路 |
Publications (2)
Publication Number | Publication Date |
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JP2004158018A true JP2004158018A (ja) | 2004-06-03 |
JP3755604B2 JP3755604B2 (ja) | 2006-03-15 |
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Application Number | Title | Priority Date | Filing Date |
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JP51729593A Expired - Lifetime JP3555140B2 (ja) | 1992-03-31 | 1993-03-26 | レジスタリネーム回路の半導体フロアプランと方法 |
JP2003393276A Expired - Fee Related JP3755604B2 (ja) | 1992-03-31 | 2003-11-25 | レジスタ・リネーム回路の半導体フロアプランのレイアウト・システム |
JP2003428567A Expired - Lifetime JP3724582B2 (ja) | 1992-03-31 | 2003-12-25 | 命令実行ユニットのためのレジスタ・リネーミング回路 |
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JP51729593A Expired - Lifetime JP3555140B2 (ja) | 1992-03-31 | 1993-03-26 | レジスタリネーム回路の半導体フロアプランと方法 |
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JP2003428567A Expired - Lifetime JP3724582B2 (ja) | 1992-03-31 | 2003-12-25 | 命令実行ユニットのためのレジスタ・リネーミング回路 |
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US (9) | US5371684A (ja) |
JP (3) | JP3555140B2 (ja) |
WO (1) | WO1993020506A1 (ja) |
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Also Published As
Publication number | Publication date |
---|---|
JP3724582B2 (ja) | 2005-12-07 |
JP3755604B2 (ja) | 2006-03-15 |
US6782521B2 (en) | 2004-08-24 |
WO1993020506A1 (en) | 1993-10-14 |
US6401232B1 (en) | 2002-06-04 |
JP3555140B2 (ja) | 2004-08-18 |
JPH07505495A (ja) | 1995-06-15 |
US20020129324A1 (en) | 2002-09-12 |
US7555738B2 (en) | 2009-06-30 |
US7174525B2 (en) | 2007-02-06 |
US5734584A (en) | 1998-03-31 |
US20040243961A1 (en) | 2004-12-02 |
US5371684A (en) | 1994-12-06 |
US5831871A (en) | 1998-11-03 |
US20070113214A1 (en) | 2007-05-17 |
US5566385A (en) | 1996-10-15 |
US6083274A (en) | 2000-07-04 |
JP2004234642A (ja) | 2004-08-19 |
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