JP2004153553A - Motion picture decoder and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by dynamically controlling an operational voltage or a clock signal according to the characteristic of an MPEG stream in decoding the MPEG stream. <P>SOLUTION: A decoding block 2 decides a picture type PT. A processing amount decider 23 receives the picture type PT and a decoding time DT, finds an average processing time NT for each picture type, and stores it in a storage memory 18. A processing load analyzer 24 on the basis of the picture type PT refers to information stored in the memory 18, and finds a voltage/clock control value CV. A voltage/clock controller 15 receives the voltage/clock control value CV, and controls at least one of the operational voltage and operational clock frequency of the decoder 1. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to moving picture decoding for reproducing an MPEG stream, and particularly to a technique for reducing power consumption in decoding processing.
[0002]
[Prior art]
2. Description of the Related Art In a reproduction system of an MPEG stream represented by digital TV broadcasting, AV data (audio (Audio) and video (Video)) is packet-coded based on the MPEG standard on a transmission side, and a decoding process is performed on a reception side for reproduction. I do.
[0003]
As a conventional technique, Patent Document 1 discloses a method for reducing the power consumption of an apparatus by controlling an optimum frequency from bit rate information of an MPEG stream.
[0004]
[Patent Document 1]
JP-A-11-68881
[0005]
[Problems to be solved by the invention]
By the way, as the reception side device becomes mobile, the necessity of further reducing power consumption in the reproduction of an MPEG stream has been further increased. On the other hand, in the method disclosed in Patent Document 1, the optimum frequency is simply controlled based on the bit rate information, and it cannot be said that the power consumption reduction is still sufficient.
[0006]
In view of the above problems, it is an object of the present invention to reduce power consumption by dynamically controlling an operating voltage and a clock frequency in accordance with the characteristics of an MPEG stream in decoding an MPEG stream.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention provides a moving picture decoding apparatus for decoding an MPEG stream, which decodes an MPEG stream and determines a picture type for each picture; An accumulation memory for accumulating accumulation information indicating a past average processing time for each picture type, and a voltage / clock control unit for controlling at least one of an operation voltage and an operation clock frequency of the video decoding device. Receiving a picture type from the decoding block, and referring to the storage information stored in the storage memory based on the picture type, a voltage / clock for instructing the voltage / clock control unit to perform control. And a processing load analysis unit for obtaining a control value.
[0008]
According to the present invention, a voltage / clock control value for instructing at least one of the control contents of the operation voltage and the operation clock frequency of the video decoding device is processed by the processing load analysis unit based on the picture type. It is obtained by referring to accumulated information indicating the past average processing time for each picture type. That is, it becomes possible to dynamically control the operation voltage and the clock frequency of the device according to various picture configurations in the MPEG stream, and thus it is possible to more accurately reduce power consumption.
[0009]
The moving image decoding apparatus according to the present invention further includes a processing amount determination unit that receives a picture type and a decoding time of the picture from the decoding block, and updates stored information stored in the storage memory. It is provided with.
[0010]
Preferably, the picture types in the video decoding device according to the present invention are I picture, P picture, and B picture.
[0011]
The moving picture decoding apparatus according to the present invention further includes a stream analyzing unit that detects switching of the MPEG stream, and when the switching of the MPEG stream is detected by the stream analyzing unit, the stream stored in the storage memory. It is preferable to delete the accumulated information. This makes it possible to prevent processing load analysis based on incorrect accumulated information when switching of the MPEG stream occurs.
[0012]
According to the present invention, there is provided a moving picture decoding apparatus for decoding an MPEG stream, comprising: a decoding block; and a storage memory for storing storage information indicating a history of processing time per predetermined unit time in the decoding block. A processing amount determining unit that determines the processing amount in the decoding block, and updates the storage information stored in the storage memory based on the processing amount; and an operating voltage and an operating clock frequency of the video decoding device. A voltage / clock control unit that performs at least one of the control operations, and a voltage for instructing the voltage / clock control unit to specify control contents with reference to the storage information stored in the storage memory for each predetermined unit time. A processing load analysis unit for obtaining a clock control value;
[0013]
According to the present invention, the voltage / clock control value for instructing at least one of the operation voltage and the operation clock frequency of the moving picture decoding apparatus is processed by the processing load analysis unit by the processing time per predetermined unit period. Is obtained by referring to the accumulated information indicating the history. That is, it becomes possible to dynamically control the operation voltage and the clock frequency of the device in accordance with the change in the amount of processing in the decoding processing of the MPEG stream, and thus it is possible to more accurately reduce the power consumption.
[0014]
It is preferable that the processing load analysis unit in the video decoding device according to the present invention obtains the voltage / clock control value using an increase / decrease value and a fluctuation value of the processing time per predetermined unit time.
[0015]
Further, the moving picture decoding apparatus according to the present invention monitors a buffer memory for temporarily storing an MPEG stream before decoding, and a data amount of the MPEG stream stored in the buffer memory. It is preferable that the voltage / clock control unit includes a buffer monitoring unit that instructs the voltage / clock control unit to increase at least one of an operation voltage and an operation clock frequency of the video decoding device when the threshold value is exceeded. . Thereby, when the data amount of the MPEG stream stored in the buffer memory exceeds the threshold, the operation voltage and the operation clock frequency of the device are increased, so that the overflow of the buffer memory can be avoided beforehand. The MPEG stream can be reliably reproduced without causing data loss.
[0016]
Further, the moving picture decoding apparatus according to the present invention monitors a buffer memory for temporarily storing an MPEG stream before decoding, and a data amount of the MPEG stream stored in the buffer memory. Preferably, a buffer monitoring unit is provided which instructs the processing load analysis unit to obtain a new voltage / clock control value when a predetermined threshold value is exceeded. Accordingly, when the data amount of the MPEG stream stored in the buffer memory exceeds the threshold, a new voltage / clock control value is obtained by the processing load analysis unit, so that the buffer memory can be prevented from overflowing. Therefore, it is possible to reliably reproduce the MPEG stream without causing data loss.
[0017]
Also, the present invention provides a method for decoding an MPEG stream in a video decoding apparatus, comprising the steps of: determining a picture type for each picture while decoding the MPEG stream; Accumulating the past average processing time for each picture type as accumulation information based on the decoding time of the picture type, and referring to the accumulation information to determine the operating voltage and the operating clock frequency of the video decoding apparatus. Performing at least one control.
[0018]
Also, the present invention provides a method for decoding an MPEG stream in a moving picture decoding apparatus, wherein the step of accumulating a history of processing time per predetermined unit time as accumulation information while decoding the MPEG stream; Referring to the accumulated information and controlling at least one of an operation voltage and an operation clock frequency of the video decoding device.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
(1st Embodiment)
FIG. 1 is a diagram showing an example of a hardware configuration of a video decoding device according to the present invention. Specifically, for example, it corresponds to a mobile phone with a moving image display function, a PDA (Personal Digital Assistant), a digital TV, or the like.
[0021]
As shown in FIG. 1, the moving picture decoding apparatus 1 includes an input unit (StreamIn) 11 for inputting an MPEG stream from the outside, a CPU 12 for controlling the entire apparatus 1, a memory 13, and an external display device. A display processor 14 for performing output processing of AV signals (audio (Audio) signal and video (Video) signal), and a voltage / clock control unit 15 for performing designated voltage / clock control processing. The memory 13 includes a frame buffer 13 for storing video data after decoding, a VBB (Video Bit Buffer) 17 for storing an MPEG stream before decoding, and a storage memory 18 for storing storage information for MPEG stream load analysis, depending on the application. Is configured. Further, the voltage / clock control unit 15 controls at least one of the operation voltage and the operation clock frequency of the device 1. In the specification of the present application, the term “voltage / clock” refers to at least one of an operation voltage and an operation clock frequency to be controlled.
[0022]
In the configuration of FIG. 1, the relationship between the data flow and each component will be described in numerical order. In FIG. 1, the data flow is indicated by broken lines. When an MPEG stream is input from the outside, the input unit 11 transfers this to the VBB 17 ((1)). The data stored in the VBB 17 is subjected to a parser process (analysis of a header portion) by the CPU 12, and further subjected to a decoding process, and then transferred to the frame buffer 16 as video signal data ((2)). The picture type information and decoding time information of the MPEG stream obtained in the processing of the CPU 12 are stored as storage information in the storage memory 18 ((3)), and the CPU 12 performs load analysis with reference to the storage information and performs voltage analysis. Instruct the clock control unit 15 to change the voltage and clock (4). The display processor 14 outputs the video signal stored in the frame buffer 16 to the outside ([5]).
[0023]
By such an operation, it is possible to convert the MPEG stream input from the outside into a video signal and output it, and to appropriately control the voltage and clock of the device 1 itself.
[0024]
FIG. 2 is a block diagram functionally showing the configuration of the video decoding device according to the present embodiment. FIG. 2 has the hardware configuration of FIG. 1, and the same components as those in FIG. 1 are denoted by the same reference numerals as in FIG. 2, a parser unit 21, a decoding unit 22, a processing amount determination unit 23, and a processing load analysis unit 24 are realized by the CPU 12 and a program. The parsing unit 21 and the decoding unit 22 constitute a decoding block 2.
[0025]
The parser unit 21 analyzes the header of the MPEG stream sent from the VBB 17, extracts picture data, and sends the picture data to the decoding unit 22. Further, the picture type PT obtained by the header analysis is notified to the processing amount determination unit 23 and the processing load analysis unit 24.
[0026]
The decoding unit 22 decodes the picture data sent from the parser unit 21 and sends the decoded data to the frame buffer 16. Further, it notifies the processing amount determination unit 23 of the processing time required for decoding, that is, the decoding time DT.
[0027]
The processing amount determination unit 23 calculates a past average processing time for each picture type based on the picture type PT notified from the parser unit 21 and the decoding time DT notified from the decoding unit 22. The processing time here is a value obtained by converting the decoding time actually required for the processing into a time when the present apparatus is operated in an ideal state, that is, when the operating voltage is the maximum and the clock frequency is the maximum. I do.
[0028]
The storage memory 18 stores the average processing time NT for each picture type calculated by the processing amount determination unit 23 as storage information.
[0029]
Upon receiving the notification of the picture type PT from the parser unit 21, the processing load analysis unit 24 performs a processing load analysis with reference to the accumulated information AI stored in the accumulation memory 18. Then, based on the analysis result, the voltage / clock control value CV is sent to the voltage / clock control unit 15.
[0030]
The operation of the video decoding device 1 shown in FIG. 2 will be described with reference to the flowchart in FIG. First, in step S11, the input unit 11 inputs an MPEG stream from outside. Next, in step S12, it is determined whether a sufficient amount of MPEG stream for decoding the picture data is accumulated in the VBB 17. If a sufficient amount of the MPEG stream is stored (Yes), the process proceeds to step S13. If not (No), the VBB 17 is filled with the MPEG stream input from the input unit 11 (S13).
[0031]
Next, in step S14, the parser unit 21 analyzes the header information of the MPEG stream stored in the VBB 17, and determines the picture type PT of the picture to be decoded. Then, in step S15, the processing load analysis unit 24 acquires the access right to the storage memory 18, and then refers to the storage information AI stored in the storage memory 18 based on the picture type PT determined by the parser unit 21. Then, the voltage / clock control value CV is calculated.
[0032]
The processing in step S15 will be specifically described. FIG. 4 is a diagram showing an example of the relationship between the stored information AI in the storage memory 18 and the voltage / clock control value CV. In the example of FIG. 4, as the accumulation information AI, not only the average processing time for each picture type but also the number of arrivals of each picture type is accumulated. Of course, other information may be stored together. For example, when the processing load analysis unit 24 performs the processing load analysis with reference to the accumulated information AI shown in FIG. 4A, when the P picture is notified as the picture type PT, the average processing time of the P picture 290 ”and the average processing time“ 362 ”of the I picture that maximizes the average processing time. As a result of the analysis, a relative ratio of the average processing time of the P picture to the average processing time of the I picture, that is, 290 ÷ 362 = 0.80 (= 80 (%)) is obtained. It instructs the voltage / clock control unit 15 as the control value CV.
[0033]
Note that the voltage / clock control value CV is also required to convert the decoding time DT to a value in an ideal state when determining the processing amount. Therefore, the processing load analysis unit 24 also notifies the processing amount determination unit 23 of the voltage / clock control value CV.
[0034]
Then, in step S16, the voltage / clock control unit 15 receives the voltage / clock control value CV obtained in step S15, and supplies the operating voltage supplied to the video decoding device 1 and / or the supplied operation. Control the frequency of the clock.
[0035]
In step S17, the decoding unit 22 decodes the picture data sent from the parser unit 21. The decoding time DT at this time is sent to the processing amount determination unit 23. Then, in step S18, after obtaining the access right to the storage memory 18, the processing amount determination unit 23 uses the decoding time DT received from the decoding unit 22 to calculate the average processing time included in the storage information of the storage memory 18. Calculate and update. In addition, as shown in FIG. 4, when the number of arrivals for each picture type is stored in the storage information, the number of arrivals for each picture type is counted up according to the picture type PT received from the parser unit 21.
[0036]
As described above, according to the present embodiment, it is possible to perform appropriate voltage / clock control based on the average processing time for each picture type, and therefore, it is possible to reduce the power consumption of the device.
[0037]
Note that, in the present embodiment, the processing amount determination unit 23 always operates, but the processing amount determination does not always need to be performed, but may be performed only temporarily. For example, at the time of the initial operation when the power of the apparatus is turned on, the apparatus is executed for a predetermined time, is executed at a predetermined timing in a sampling manner, or detects when a scene represented by a moving image changes and executes the apparatus. You may. When the processing amount determination is not performed, the operation of the processing amount determination unit 23 may be stopped, so that the power consumption can be further reduced.
[0038]
Further, the processing amount determination may not be performed in parallel with the decoding processing. In this case, for example, the stored information may be directly read from the past operation result data, or data attached to the MPEG stream may be used.
[0039]
(Second embodiment)
FIG. 5 is a block diagram functionally showing the configuration of the video decoding device according to the second embodiment of the present invention. 5, the same components as those of FIG. 2 are denoted by the same reference numerals as those of FIG. When FIG. 5 is compared with FIG. 2, the moving picture decoding apparatus 1A according to the present embodiment includes a parser unit 21A having a function different from the parser unit 21 in place of the parser unit 21; The point provided newly is different from the first embodiment.
[0040]
As in the first embodiment, the parser unit 21A analyzes the header of the MPEG stream sent from the VBB 17, notifies the obtained picture type PT to the processing amount determination unit 23 and the processing load analysis unit 24, and , And extracts the picture data and sends it to the decoding unit 22. The parser unit 21A further notifies the stream analysis unit 25 of the MPEG stream switching information SC. The MPEG stream switching information SC is information relating to a change in the size or aspect ratio of the MPEG stream data, or a change in the profile. Examples of the change of the aspect ratio include a change from 16: 9 to 4: 3, and examples of the change of the profile include a change from HD to SD.
[0041]
The stream analysis unit 25 receives the MPEG stream switching information SC and detects switching of the MPEG stream. That is, when a change in the size of the MPEG stream data, a change in the aspect ratio, or a change in the profile occurs, it is determined that switching of the MPEG stream has occurred. When the switching of the MPEG stream is detected, the storage information stored in the storage memory 18 is deleted. Here, the reset signal RS is sent to the storage memory 18 by switching the memory access switch 18a of the storage memory 18.
[0042]
The operation of the video decoding device 1A shown in FIG. 5 will be described with reference to the flowchart in FIG. Note that steps common to those in FIG. 3 are denoted by the same reference numerals as those in FIG. 3, and description thereof is omitted here.
[0043]
When there is a sufficient amount of MPEG streams in the VBB 17 (Yes in S12), in step S21, the stream analysis unit 25 determines whether switching of the MPEG streams has occurred. If no error has occurred (No in S21), the process proceeds to step S14, and the same processing as in the first embodiment is performed.
[0044]
On the other hand, when the switching of the MPEG stream has occurred (Yes in S21), the process proceeds to step S22, where the stream analysis unit 25 sends a reset signal RS after acquiring the access right to the storage memory 18, and deletes the storage information. . Further, in step S23, the voltage / clock control value CV is set to the maximum. As a result, even when the stream is changed to another MPEG stream, the decoding process can be performed in time.
[0045]
FIGS. 7A and 7B show an example of a change in the accumulated information AI in the present embodiment, in which FIG. 7A is a graph showing a temporal change in the amount of the accumulated information AI, and FIG. (Arrival number and average processing time) and voltage / clock control value CV transition. In FIG. 7, the profile is changed at the time Sn, and the aspect ratio is changed at the time Sm. Therefore, the switching of the MPEG stream is detected at times Sn and Sm, all the accumulated information accumulated so far is deleted, and the maximum value “100” is given as the voltage / clock control value CV. After the switching of the MPEG stream, information on the number of arrivals of pictures and the average processing time is accumulated again, and the voltage / clock control value CV for the next picture is obtained based on the accumulated information.
[0046]
As described above, according to the present embodiment, when the stream analysis unit 25 detects the occurrence of the switching of the MPEG stream, the past accumulated information is deleted. Therefore, when the stream is switched, the load analysis based on the erroneous accumulated information is performed. Can be prevented.
[0047]
(Third embodiment)
FIG. 8 is a block diagram functionally showing the configuration of the video decoding device according to the third embodiment of the present invention. 8, the same components as those in FIG. 5 are denoted by the same reference numerals as in FIG. In the present embodiment, the contents of the storage information stored in the storage memory 18A are different from those in the first and second embodiments. Therefore, the processing amount determination for performing an operation different from the first and second embodiments is performed. A unit 23A and a processing load analysis unit 24A are provided.
[0048]
In the present embodiment, the accumulation memory 18A accumulates, as accumulation information, a history of processing time per unit time in the past decoding processing of the decoding block 2A. The processing time in this case is the same as in the first and second embodiments, except that the decoding time actually required for the processing is set to the ideal state of the apparatus, that is, the operation voltage is the maximum and the clock frequency is the maximum. It is the value converted to the time when operating in the state (absolute processing time). Further, in the present embodiment, as the accumulated information, a plurality of processing times per unit time including the latest processing time are held, and for each processing time, the difference from the previous processing time is set as an increase / decrease value. Shall be retained.
[0049]
The processing amount determination unit 23A calculates the absolute processing time based on the decoding time DT notified from the decoding unit 22, calculates the total sum of the absolute processing time at regular time intervals T, and stores the sum as the storage information in the storage memory 18A. I do. Here, the fixed time T is, for example, about 1 sec. The processing load analysis unit 24A acquires the storage information AI stored in the storage memory 18A and performs the processing load analysis. Then, based on the analysis result, the voltage / clock control value CV is sent to the voltage / clock control unit 15. The processing amount determination unit 23A and the processing load analysis unit 24A perform time management using an internal timer.
[0050]
The operation of the video decoding device 1B shown in FIG. 8 will be described with reference to the flowchart in FIG. Note that the same steps as those in FIG. 3 are denoted by the same reference numerals as those in FIG. 3, and description thereof is omitted here. Also, steps relating to the stream analysis unit 25 are omitted for simplification of description.
[0051]
When there is a sufficient amount of MPEG stream in the VBB 17 (Yes in S12), in step S31, the processing amount determination unit 23A determines whether or not a predetermined time T has elapsed. If not, the process proceeds to step S17, where the decoding process is executed.
[0052]
After the decoding process, the processing amount determination unit 23A receives the decoding time DT from the decoding unit 22, obtains the right to access the storage memory 18A, and then calculates the latest processing time per unit time included in the storage information. Update is performed using the absolute processing time converted from the decoding time DT. Further, the difference from the previous processing time per unit time is recalculated to update the increase / decrease value.
[0053]
On the other hand, if the predetermined time T has elapsed (Yes in S31), the process proceeds to step S32, in which the processing load analysis unit 24A acquires the right to access the storage memory 18A, and then obtains the latest unit time included in the storage information AI. The voltage / clock control value CV is calculated based on the hit processing time and the increase / decrease value thereof. In step S33, the voltage / clock control unit 15 receives the voltage / clock control value CV obtained in step S32, and changes the operation voltage supplied to the moving picture decoding device 1B and the frequency of the supplied operation clock. Control.
[0054]
The processing in step S32 will be specifically described. FIG. 10A is a diagram showing an example of the relationship between the stored information AI in the storage memory 18 and the voltage / clock control value CV, and FIG. 10B is a graph showing the time change of the voltage / clock control value CV. The processing load analysis unit 24A calculates the voltage / clock control value CV, for example, as follows with reference to the accumulated information AI. An increase / decrease value α, that is, a difference value from the previous time, and a value corresponding to three times the standard deviation value σ of the past n processing times per unit time are added to the latest processing time γn per unit time, and the sum thereof is calculated. Is the next estimated processing time per unit time γn + 1. That is,
γn + 1 = γn + α + 3σ
And Then, the ratio of the processing time estimated value γn + 1 to the maximum absolute processing time MAX in the fixed time T, that is,
CV = γn + 1 / MAX
Is obtained as a voltage / clock control value. In this case, α and 3σ correspond to an increase / decrease value and a fluctuation value of the processing time per unit time, respectively.
[0055]
As described above, according to the present embodiment, appropriate voltage and clock control can be performed based on the history of the processing time per predetermined unit time, and therefore, the power consumption of the device can be reduced.
[0056]
(Fourth embodiment)
FIG. 11 is a block diagram functionally showing the configuration of the video decoding device according to the fourth embodiment of the present invention. 11, the same components as those in FIG. 8 are denoted by the same reference numerals as those in FIG. In the present embodiment, a buffer monitoring unit 31 that monitors the data amount of the MPEG stream stored in the VBB 17 as a buffer memory is provided.
[0057]
When the data amount of the MPEG stream stored in the VBB 17 exceeds a predetermined threshold value, the buffer monitoring unit 31 instructs the voltage / clock control unit 15 to maximize the voltage / clock (MAX). Here, the access switch 15a is switched to invalidate the output of the processing load analysis unit 24A, and the voltage / clock control unit 15 is instructed. Further, the memory access switch 18b of the storage memory 18A is switched to delete unnecessary information from the storage information of the storage memory 18A.
[0058]
The operation of the video decoding device 1C shown in FIG. 11 will be described with reference to the flowchart in FIG. Note that the same steps as those in FIG. 9 are denoted by the same reference numerals as in FIG. 9, and the description thereof will not be repeated. Also, steps relating to the stream analysis unit 25 are omitted for simplification of description.
[0059]
In step S41, the buffer monitoring unit 31 determines whether or not the data amount of the MPEG stream stored in the VBB 17 has exceeded a threshold. If the data amount has exceeded the threshold (Yes), the process proceeds to step S42, and the voltage / clock control unit For 15, the voltage / clock control value CV is set to the maximum. As a result, it is possible to prevent the decoding process of the MPEG stream from being out of time. Note that the voltage / clock does not necessarily need to be maximized, and an effect can be obtained if an instruction is given to increase the voltage / clock from the current value.
[0060]
FIG. 13A is a graph showing the data amount of the MPEG stream stored in the VBB 17 and the transition of the voltage / clock control value CV. When the amount of data stored in the MPEG stream is equal to or smaller than the threshold value, the voltage / clock control value CV is instructed by the processing load analysis unit 24A at regular time intervals T, as in the third embodiment. However, when the amount of data stored in the MPEG stream exceeds the threshold value (time Tr), the voltage / clock control value CV becomes maximum according to an instruction from the buffer monitoring unit 31. FIG. 13B shows changes in the voltage / clock control value CV and the stored information AI (processing time per unit time and increase / decrease amount) stored in the storage memory 18A before and after the time Tr.
[0061]
As described above, according to the present embodiment, when the amount of data stored in the MPEG stream exceeds the threshold value, the voltage and clock can be increased, so that the MPEG stream can be reliably reproduced without data loss. become.
[0062]
(Fifth embodiment)
FIG. 14 is a block diagram functionally showing the configuration of the video decoding device according to the fifth embodiment of the present invention. 14, the same components as those in FIG. 11 are denoted by the same reference numerals as those in FIG. In the present embodiment, a processing load analysis unit 24B and a buffer monitoring unit 31A that perform operations different from those of the fourth embodiment are provided.
[0063]
When the data amount of the MPEG stream stored in the VBB 17 exceeds a predetermined threshold, the buffer monitoring unit 31A notifies the processing load analysis unit 24B of a decrease in processing. When notified of the processing drop from the buffer monitoring unit 31A, the processing load analysis unit 24B immediately executes the load analysis without waiting for the next load analysis timing, that is, without waiting for a predetermined unit time T to elapse. I do. In other words, the buffer monitoring unit 31A instructs the processing load analysis unit 24B to obtain a new voltage / clock control value CV.
[0064]
The operation of the video decoding device 1D shown in FIG. 14 will be described with reference to the flowchart in FIG. Steps common to those in FIG. 12 are denoted by the same reference numerals as those in FIG. 12, and detailed description thereof will be omitted. Also, steps relating to the stream analysis unit 25 are omitted for simplicity of description.
[0065]
When the buffer monitoring unit 31A determines that the data amount of the MPEG stream stored in the VBB 17 has exceeded the threshold (Yes in S41), the process proceeds to step S51, and the processing load analysis unit 24B acquires the access right to the storage memory 18A. Thereafter, load analysis is performed with reference to the stored information AI in the storage memory 18A, and the voltage / clock control value CV is calculated.
[0066]
FIG. 16A is a graph showing the data amount of the MPEG stream stored in the VBB 17 and the transition of the voltage / clock control value CV. When the amount of data stored in the MPEG stream is equal to or smaller than the threshold value, the voltage / clock control value CV is instructed by the processing load analysis unit 24B at regular time intervals T as in the third embodiment. However, when the amount of data stored in the MPEG stream exceeds the threshold value at the time Tr, the processing load analysis unit 24B traces back the stored information from the time Tr and returns from the time Tr-1 to the time Tr from the current time Tr by the time T. The processing time per unit period up to and the increase / decrease value with respect to the processing time per unit period before that are obtained, and the voltage / clock control value CV at the next time Tr to Tr + 1 is obtained from these values. At this time, similarly to the third embodiment, the standard deviation σ of the processing time for each unit time T in the past based on the time Tr may be used. FIG. 16B shows an example of changes in the voltage / clock control value CV and the accumulated information AI {sum of processing time and increase / decrease} before and after time Tr. As described above, in the present embodiment, the load analysis is started from the time Tr at which the accumulated data amount exceeds the threshold.
[0067]
Then, in step S52, the voltage / clock control unit 15 receives the voltage / clock control value CV obtained in step S51, and supplies the operation voltage supplied to the video decoding device 1D and the frequency of the supplied operation clock. Control. Further, in step S53, the measurement timing is reset for a predetermined time T at the time of the determination by the processing amount determination unit 23A, and the time Tr is set as a starting point.
[0068]
As described above, according to the present embodiment, when the amount of data stored in the MPEG stream exceeds the threshold value, load analysis can be performed, so that it is possible to reliably perform MPEG stream reproduction processing without data loss. become.
[0069]
【The invention's effect】
As described above, according to the present invention, the operating voltage and the clock frequency of the device are dynamically controlled according to the picture type and the processing time per unit period. Processing with low power consumption.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a hardware configuration of a video decoding device according to the present invention.
FIG. 2 is a block diagram functionally showing a configuration of a video decoding device according to the first embodiment of the present invention.
FIG. 3 is a flowchart illustrating an operation of the video decoding device of FIG. 2;
FIG. 4 is a diagram illustrating a relationship between accumulated information and a voltage / clock control value according to the first embodiment of the present invention.
FIG. 5 is a block diagram functionally showing a configuration of a video decoding device according to a second embodiment of the present invention.
FIG. 6 is a flowchart showing an operation of the moving picture decoding apparatus of FIG. 5;
FIG. 7 is a diagram illustrating a change in accumulated information according to a second embodiment of the present invention.
FIG. 8 is a block diagram functionally showing the configuration of a video decoding device according to a third embodiment of the present invention.
FIG. 9 is a flowchart showing the operation of the video decoding device of FIG. 8;
FIG. 10 is a diagram showing changes in accumulated information and voltage / clock control values according to a third embodiment of the present invention.
FIG. 11 is a block diagram functionally showing the configuration of a video decoding device according to a fourth embodiment of the present invention.
FIG. 12 is a flowchart showing the operation of the video decoding device of FIG. 11;
FIG. 13 is a diagram showing changes in the amount of data stored in an MPEG stream and voltage / clock control values according to a fourth embodiment of the present invention.
FIG. 14 is a block diagram functionally showing a configuration of a video decoding device according to a fifth embodiment of the present invention.
FIG. 15 is a flowchart showing the operation of the video decoding device of FIG. 14;
FIG. 16 is a diagram illustrating changes in the amount of data stored in an MPEG stream and voltage / clock control values according to a fifth embodiment of the present invention.
[Explanation of symbols]
1,1A, 1B, 1C, 1D video decoding device
2,2A decoding block
15 Voltage / clock control unit
17 VBB (buffer memory)
18, 18A storage memory
23, 23A processing amount determination unit
24, 24A, 24B Processing load analysis unit
25 Stream analysis unit
31, 31A buffer monitoring unit
PT picture type
DT decoding time
AI accumulated information
CV voltage / clock control value

Claims (10)

A moving picture decoding apparatus for decoding an MPEG stream,
A decoding block for decoding an MPEG stream and determining a picture type for each picture;
A storage memory for storing storage information indicating a past average processing time for each picture type in the decoding block;
A voltage / clock control unit that controls at least one of an operation voltage and an operation clock frequency of the video decoding device;
A voltage / clock control for instructing the voltage / clock control unit to control contents by receiving a picture type from the decoding block, referring to the storage information stored in the storage memory, based on the picture type. A moving picture decoding apparatus comprising: a processing load analysis unit for obtaining a value. In claim 1,
A moving picture decoding apparatus, comprising: a processing amount determining unit that receives a picture type and a decoding time of the picture from the decoding block and updates accumulated information stored in the accumulation memory. In claim 1,
The picture decoding device is characterized in that the picture types are an I picture, a P picture, and a B picture. In claim 1,
A stream analysis unit for detecting switching of the MPEG stream;
A moving picture decoding apparatus characterized in that when the switching of an MPEG stream is detected by the stream analyzer, the storage information stored in the storage memory is deleted. A moving picture decoding apparatus for decoding an MPEG stream,
A decryption block;
A storage memory for storing storage information indicating a history of processing time per predetermined unit time in the decoding block;
A processing amount determining unit that determines a processing amount in the decoding block, and updates a storage information stored in the storage memory based on the processing amount;
A voltage / clock control unit that controls at least one of an operation voltage and an operation clock frequency of the video decoding device;
A processing load analysis unit for obtaining a voltage / clock control value for instructing the voltage / clock control unit to control the content by referring to the storage information stored in the storage memory for each predetermined unit time; A moving picture decoding apparatus characterized in that: In claim 5,
The moving picture decoding apparatus according to claim 1, wherein the processing load analysis unit obtains the voltage / clock control value using an increase / decrease value and a fluctuation value of a processing time per a predetermined unit time. In claim 5,
A buffer memory for temporarily storing an MPEG stream before decoding,
The amount of data of the MPEG stream stored in the buffer memory is monitored, and when the amount of data exceeds a predetermined threshold, the voltage / clock control unit informs the voltage / clock control unit of the operating voltage and operating clock frequency of the video decoding device. A moving picture decoding apparatus comprising: a buffer monitoring unit that instructs at least one of them to be raised. In claim 5,
A buffer memory for temporarily storing an MPEG stream before decoding,
A buffer monitoring unit that monitors a data amount of the MPEG stream stored in the buffer memory and, when the data amount exceeds a predetermined threshold, instructs the processing load analysis unit to obtain a new voltage / clock control value; And a moving picture decoding apparatus. A method for decoding an MPEG stream in a video decoding device, comprising:
Determining a picture type for each picture while decoding the MPEG stream;
Storing the past average processing time for each picture type as storage information based on the picture type and the decoding time of the picture;
Performing a control of at least one of an operation voltage and an operation clock frequency of the video decoding device with reference to the accumulated information. A method for decoding an MPEG stream in a video decoding device, comprising:
Storing a history of processing time per unit time as storage information while decoding the MPEG stream;
Performing a control of at least one of an operation voltage and an operation clock frequency of the video decoding device with reference to the accumulated information.

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