JP2004153329A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display capable of preventing deterioration in an opening ratio and a manufacturing yield. <P>SOLUTION: The display comprises a glass substrate 1 and a semiconductor substrate 2. On the glass substrate 1, there are a pixel array 3 in which a signal line and a scan line are provided in a row, a signal line drive circuit 4 for driving the signal line, a scan line drive circuit 5 for driving the scan line, and an output signal processing section 6 for capturing an image for outputting. Each pixel at the pixel array 3 comprises a capacitor C3 connected between a power supply line L1 and a control line L2, a buffer 13 for storing binary data corresponding to the accumulation charge of the capacitor C3, a transistor Q3 for performing write control to the buffer 13, and a transistor Q4 for resetting for initializing the buffer 13 and the capacitor C3. The capacitor C3, buffer 13, and transistors Q3, Q4 are shared by three subpixels in the pixel. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device having an image capturing function.
[0002]
[Prior art]
The liquid crystal display device includes an array substrate on which signal lines, scanning lines, and pixel TFTs are arranged in rows, and a driving circuit that drives the signal lines and scanning lines. With the recent advancement and development of integrated circuit technology, a process technology for forming a part of a drive circuit on an array substrate has been put to practical use, and the entire liquid crystal display device can be made lighter, thinner and shorter. Accordingly, liquid crystal display devices are now widely used as display devices for various portable devices such as mobile phones and notebook computers.
[0003]
Meanwhile, a display device with an image capturing function in which a contact area sensor for capturing an image is arranged on an array substrate has been proposed (for example, see Patent Documents 1 and 2).
[0004]
Conventional display devices equipped with this type of image capture function change the amount of charge in a capacitor connected to the sensor in accordance with the amount of light received by the sensor, and detect the voltage across the capacitor to capture the image. It is carried out.
[0005]
[Patent Document 1]
JP 2001-292276 A [Patent Document 2]
JP 2001-339640 A
[Problems to be solved by the invention]
When performing fingerprint authentication using this type of image capturing function, a resolution of about 500 dpi is required. However, if the image capturing function is incorporated in a display device, the resolution of about 200 dpi is limited.
[0007]
In addition, since the display device has a large wiring load, it is necessary to provide not only the photoelectric conversion element but also a buffer circuit for amplifying the output of the photoelectric conversion element in the pixel. Will drop.
[0008]
Further, since the image capturing sensor must be arranged in the pixel, the structure of the pixel is complicated, and the manufacturing yield is reduced.
[0009]
The present invention has been made in view of such a point, and an object of the present invention is to provide a display device that can prevent a decrease in aperture ratio and manufacturing yield.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a display element formed near each intersection of a signal line and a scanning line arranged in a first direction and a second direction, and a display element corresponding to each of the display elements. A photoelectric conversion unit that receives one of the incident lights and outputs an electric signal corresponding to the amount of received light; and a photoelectric conversion unit that includes two or more photoelectric conversion units. A charge accumulating unit that accumulates an electric charge corresponding to an electric signal output from the photoelectric conversion unit, and an electric charge corresponding to an amount of light received by the two or more photoelectric conversion units of each set is sequentially accumulated in the charge accumulation unit. And a drive control unit for sequentially driving the two or more photoelectric conversion units of each set.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings.
[0012]
(1st Embodiment)
FIG. 1 is a schematic configuration diagram of a first embodiment of a display device according to the present invention, which is characterized by having an image capturing function. 1 includes a glass substrate 1 and a semiconductor substrate 2.
[0013]
On the glass substrate 1, a pixel array unit 3 in which signal lines and scanning lines are arranged in a row, a signal line driving circuit 4 for driving signal lines, a scanning line driving circuit 5 for driving scanning lines, and an image And an output signal processing unit 6 (having a detection circuit and an output circuit). Each circuit on the glass substrate 1 is formed of, for example, a polysilicon TFT.
[0014]
The signal line driving circuit 4 includes a D / A conversion circuit that converts digital pixel data into an analog voltage suitable for driving a display element. A known D / A conversion circuit is used.
[0015]
On the semiconductor substrate 2, a logic IC 7 for performing display control and image capture control is mounted. The glass substrate 1 and the semiconductor substrate 2 transmit and receive various signals via, for example, an FPC.
[0016]
FIG. 2 is a block diagram showing a part of the pixel array unit 3 in detail. Each portion surrounded by a dotted line in FIG. 2 is one pixel, and each pixel is composed of three sub-pixels of three colors of RGB.
[0017]
Each of the three sub-pixels includes a pixel TFT 11 formed near each intersection of signal lines and scanning lines arranged vertically and horizontally, a liquid crystal capacitor C1 and an auxiliary capacitor C2 connected to one end of the pixel TFT 11, And a sensor 12. The sensor 12 is connected to a power supply line and a control line not shown in FIG.
[0018]
FIG. 3 is a circuit diagram showing the configuration of one pixel in detail. One pixel is provided with one sensor 12 composed of a photodiode corresponding to each of the three pixel TFTs 11. The anode terminal of each sensor 12 is connected to the power supply line L1, and the cathode terminal is connected to the control line L2. Hereinafter, the sensors 12 corresponding to the pixel TFTs 11 for red, green, and blue are referred to as sensors 12a, 12b, and 12c, respectively.
[0019]
The sensor 12a corresponding to the pixel TFT 11 for red display is formed adjacent to the pixel electrode connected to this pixel TFT 11, and the sensor 12b corresponding to the pixel TFT 11 for green display is connected to the pixel electrode connected to this pixel TFT 11. The sensor 12c formed adjacent to and corresponding to the pixel TFT 11 for blue display is formed adjacent to the pixel electrode connected to the pixel TFT 11.
[0020]
In addition, in each pixel, a capacitor C3 connected between the power supply line L1 and the control line L2, a buffer 13 for storing binary data corresponding to the charge stored in the capacitor C3, and a write control to the buffer 13 And a reset transistor Q4 for initializing the buffer 13 and the capacitor C3. The capacitor C3, the buffer 13, and the transistors Q3, Q4 are shared by three sub-pixels in the pixel.
[0021]
The buffer 13 is composed of a static RAM (SRAM), for example, as shown in FIG. 4, two inverters IV1 and IV2 connected in series, an output terminal of the succeeding inverter IV2, and an input terminal of the preceding inverter IV1. And an output transistor Q6 connected to the output terminal of the subsequent inverter IV2.
[0022]
When the signal SPOLB is at a high level, the transistor Q5 is turned on, and the two inverters IV1 and IV2 perform a holding operation. When the signal OUTi is at a high level, the held data is output to the detection line. The detection line may be provided separately from the signal line, or any of the signal lines may be used. In FIG. 3, a signal line of a blue pixel is used. It is not necessary to separately provide a detection line other than the signal line.
[0023]
The display device of the present embodiment can perform a normal display operation, and can also perform image capture similar to a scanner. When a normal display operation is performed, the transistor Q3 is turned off, and no valid data is stored in the buffer 13. Conversely, the data held in the buffer 13 does not affect the signal line potential and the pixel potential. In this case, a signal line voltage is supplied from the signal line driving circuit 4 to the signal line, and display according to the signal line voltage is performed.
[0024]
On the other hand, when performing image capturing, an image capturing object (for example, a paper surface) 22 is arranged on the upper surface side (opposite to the film forming surface) of the array substrate 21 as shown in FIG. Is irradiated on the paper surface 22 via the counter substrate 24 and the array substrate 21. The light reflected on the paper surface 22 (the amount of light changes according to the reflectance of the paper surface 22) is received by the sensors 12a and 12b on the array substrate 21, and the image is captured.
[0025]
Before starting the image capture, the transistor is set to the ON state, and the initial charge is stored in the capacitor C3. Thereafter, image capture is started, and the charge corresponding to the amount of light received by the sensor 12 is discharged (leaked) from the capacitor C3, and the charge stored in the capacitor C3 changes. That is, the amount of light received by the sensor 12 can be detected based on the magnitude of the charge stored in the capacitor C3 (the potential level of the capacitor C3).
[0026]
After the potential of the capacitor C3 is amplified by the buffer 13, it is sent to the logic IC 7 shown in FIG. 1 via the detection line and the output signal processing unit 6 formed integrally with the frame portion of the array substrate. The logic IC 7 receives digital signals output from the display device of the present embodiment and performs arithmetic processing such as rearrangement of data and removal of noise in data.
[0027]
This embodiment is characterized in that there is no switching means for switching the connection relationship between each sensor 12 and the capacitor C3. Instead, the image is captured by changing the display color, so that only the amount of light received by the sensor 12 corresponding to an arbitrary color is detected by the capacitor C3. Since the remaining two sensors belong to a pixel having almost no light transmittance, there is no leakage current, and thus no switching means is required. Such a configuration is made possible by integrally forming the display element and the optical sensor (in a general CMOS sensor or the like, it is not possible to provide means for shielding the unused sensor from light).
[0028]
For example, in order to take out the imaging result of the sensor 12a corresponding to the pixel TFT 11 for red, only the pixel TFT 11 for red is turned on (light transmitting state), and the pixel TFT 11 for green and blue is turned off ( An image is captured while the entire screen is displayed in red. In this case, the reflected light from the imaging target is input only to the sensor 12a corresponding to the pixel TFT 11 for red, and is not input to the sensors 12b and 12c corresponding to the pixel TFT 11 for green and blue. Therefore, no light leakage current occurs in the sensors 12b and 12c corresponding to green and blue, and the increase or decrease in the accumulated charge in the capacitor C3 mainly depends on the light leakage in the sensor 12a corresponding to red. .
[0029]
The output signal of the buffer 13 that amplifies the potential of the capacitor C3 is supplied to the output signal processing unit 6 in the frame portion via a signal line. The output signal processing unit 6 performs signal amplitude conversion, data output order change, parallel-serial conversion, and the like, and outputs an image capture result to a logic IC 7 such as an external CPU.
[0030]
FIG. 6 is a diagram schematically illustrating the timing of image capture according to the first embodiment. The image capture is performed three times. First, as shown in FIG. 6A, all the pixel TFTs 11 for one frame for red are turned on (in a transmission state), and the entire screen is displayed in red, and according to the charge accumulated in the capacitor C3. The stored binary data is stored in the buffer 13. In this case, only the sensor 12 corresponding to the pixel TFT 11 for red display receives the reflected light from the imaging target, and the amount of the received light is detected by the logic IC 7 via the capacitor C3 and the buffer 13.
[0031]
Next, as shown in FIG. 6 (b), all the green pixel TFTs 11 for one frame are turned on, and in a state where the entire screen is displayed in green, binary data corresponding to the accumulated charge of the capacitor C3 is stored. The data is stored in the buffer 13. In this case, only the sensor 12 corresponding to the pixel TFT 11 for green display receives the reflected light from the imaging target, and the received light amount is detected by the logic IC 7 via the capacitor C3 and the buffer 13.
[0032]
Next, as shown in FIG. 6C, all the pixel TFTs 11 for one frame for blue are turned on, and binary data corresponding to the accumulated charge of the capacitor C3 is stored in a state where the entire screen is displayed in blue. The data is stored in the buffer 13. In this case, only the sensor 12 corresponding to the pixel TFT 11 for blue display receives the reflected light from the imaging target, and the amount of the received light is detected by the logic IC 7 via the capacitor C3 and the buffer 13.
[0033]
FIG. 7 is a timing chart showing an example of the timing of image capture. First, from time t1 to t2, the scanning lines are sequentially turned on, and all pixels for one frame are displayed in red by a normal method of writing the signal line potential to each pixel. Next, from time t3 to t4, the sensor 12 is precharged. Here, an initial value is written into the buffer 13 and an initial charge is stored in the capacitor C3.
[0034]
Next, from time t4 to t5, the sensor 12 captures an image. During this period, the charge stored in the capacitor C3 changes according to the amount of light received by the sensor 12. Next, at time t5, the transistor Q3 turns on, and the buffer 13 amplifies the potential of the capacitor C3. Then, the transistor Q5 shown in FIG. 4 in the buffer 13 is turned on (time t5 to t6), and the buffer 13 performs an output holding operation.
[0035]
Thereafter, from time t7 to t8, the output of the buffer 13 of each pixel is sequentially output to the outside of the array substrate row by row.
[0036]
Thereafter, from time t9 to t10, all the pixels for one frame are displayed in green, and the same processing as at time t1 to t8 is performed. Thereafter, at times t11 to t12, all the pixels for one frame are displayed in blue, and the same processing as at times t1 to t8 is performed.
[0037]
As described above, in the first embodiment, one sensor 12 is provided for each of a plurality of sub-pixels in one pixel, and the image is captured a plurality of times while changing the display color, so that the output of the sensor 12 is switched. Even if no switching means is provided, it is possible to individually accumulate charges in the capacitor C3 according to the amount of light received by the sensor 12 corresponding to each display color. Therefore, switching means for switching the connection between each sensor 12 and the capacitor C3 becomes unnecessary, and the structure of the array substrate can be simplified, and the aperture ratio and the manufacturing yield can be improved. When the aperture ratio can be increased, the luminance of the backlight can be reduced, so that power consumption can be reduced and the battery can last longer.
[0038]
(Second embodiment)
In the second embodiment, one capacitor C3 is shared by a plurality of pixels that are adjacent in the vertical direction of the screen.
[0039]
FIG. 8 is a circuit diagram showing in detail a configuration for one pixel in the second embodiment of the display device according to the present invention. In FIG. 8, the same components as those in FIG. 3 are denoted by the same reference numerals, and the following description will focus on differences.
[0040]
Each pixel has three sub-pixels, and each sub-pixel has a pixel TFT 11 and a sensor 12. In the display device of FIG. 8, two pixels adjacent in the vertical direction share the capacitor C3, the buffer 13, and the transistors Q3 and Q4.
[0041]
The cathode terminals of all sensors 12 of two pixels adjacent in the vertical direction are connected to the same control line L2. A capacitor C3 is connected between the control line L2 and a power supply line L1 to which the anode terminal of each sensor 12 is connected.
[0042]
FIG. 9 is a diagram schematically showing the timing of image capture in the second embodiment. Image capture is performed in six parts. First, in a state where all the pixel TFTs 11 for red of the odd pixels in the vertical direction for one frame are turned on and all the odd pixels in the vertical direction for one frame are displayed in red, the binary data according to the accumulated charge of the capacitor C3 is stored. The data is stored in the buffer 13. In this case, only the sensor 12a corresponding to the pixel TFT 11 for red display of the odd pixels in the vertical direction receives the reflected light from the imaging target, and the received light amount is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0043]
Next, the binary data corresponding to the charge stored in the capacitor C3 is stored in the buffer 13 in a state where all the odd pixels in the vertical direction for one frame are displayed in green. In this case, only the sensor 12b corresponding to the pixel TFT 11 for green display of odd-numbered pixels in the vertical direction receives the reflected light from the imaging target, and the received light amount is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0044]
Next, in a state where all the odd pixels in the vertical direction for one frame are displayed in blue, binary data corresponding to the accumulated charge of the capacitor C3 is stored in the buffer 13. In this case, only the sensor 12c corresponding to the pixel TFT 11 for blue display of odd pixels in the vertical direction receives the reflected light from the imaging target, and the amount of the received light is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0045]
Next, in a state where all the even pixels in the vertical direction for one frame are displayed in red, binary data corresponding to the charge stored in the capacitor C3 is stored in the buffer 13. In this case, only the sensor 12a corresponding to the pixel TFT 11 for red display of the even-numbered pixel in the vertical direction receives the reflected light from the imaging target, and the received light amount is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0046]
Next, in a state where all the even pixels in the vertical direction for one frame are displayed in green, the binary data corresponding to the accumulated charge of the capacitor C3 is stored in the buffer 13. In this case, only the sensor 12b corresponding to the pixel TFT 11 for green display of the even-numbered pixel in the vertical direction receives the reflected light from the imaging target, and the amount of received light is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0047]
Next, in a state where all the even pixels in the vertical direction for one frame are displayed in blue, binary data corresponding to the accumulated charge of the capacitor C3 is stored in the buffer 13. In this case, only the sensor 12c corresponding to the blue pixel TFT 11 of the even-numbered pixel in the vertical direction receives the reflected light from the imaging target, and the amount of the received light is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0048]
FIG. 10 is a timing chart showing an example of the timing of image capture. First, from time t1 to t2, all the odd pixels in the vertical direction for one frame are displayed in red. Next, between times t3 and t4, the capacitor C3 and the buffer 13 are initialized, and between times t4 and t5, the imaging result of the sensor 12a is stored in the capacitor C3. The binary data is stored in the buffer 13. Thereafter, between times t7 and t8, the output of the buffer 13 is sequentially output line by line.
[0049]
Next, from time t9 to time t10, all the vertical odd pixels of one frame are displayed in green, and the same processing as that of time t1 to t8 is performed. The image capturing result of the sensor 12b corresponding to the TFT 11 is output.
[0050]
Next, at times t11 to t12, all the vertical odd pixels of one frame are displayed in blue, and the same processing as at times t1 to t8 is performed, and the vertical odd pixels of one frame are displayed in blue. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0051]
Next, from time t13 to time t14, all the vertical even pixels of one frame are displayed in red, and the same processing as that of time t1 to t8 is performed. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0052]
Next, from time t15 to t16, all the vertical even pixels of one frame are displayed in green, and the same processing as in time t1 to t8 is performed, and the green display pixels of one frame of vertical even pixels are performed. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0053]
Next, from time t17 to t18, all of the vertical even pixels of one frame are displayed in blue, and the same processing as in time t1 to t8 is performed, and the blue display pixels of one frame of vertical even pixels are performed. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0054]
As described above, in the second embodiment, since the capacitor C3 and the buffer 13 are shared by a plurality of pixels adjacent in the vertical direction of the screen, the pixel structure can be further simplified as compared with the first embodiment, and the aperture ratio and The manufacturing yield can be further improved.
[0055]
Although FIG. 10 illustrates an example in which the capacitor C3 and the buffer 13 are shared by two vertically adjacent pixels of the screen, the capacitor C3 and the buffer 13 may be shared by three or more vertically adjacent pixels. .
[0056]
(Third embodiment)
In the third embodiment, one capacitor C3 is shared by a plurality of pixels adjacent in the horizontal direction of the screen.
[0057]
FIG. 11 is a circuit diagram showing in detail a configuration for one pixel in the third embodiment of the display device according to the present invention. In FIG. 11, the same components as those in FIG. 3 are denoted by the same reference numerals, and the following description will focus on the differences.
[0058]
Each pixel has three sub-pixels, and each sub-pixel has a pixel TFT 11 and a sensor 12. In the display device of FIG. 11, two pixels adjacent in the horizontal direction share the capacitor C3, the buffer 13, and the transistors Q3 and Q4.
[0059]
The anode terminals of all the sensors 12 of two pixels adjacent in the horizontal direction are connected to the same power supply line L1, and the cathode terminals are also connected to the same control line L2. A capacitor C3 is connected between the power supply line L1 and the control line L2.
[0060]
FIG. 12 is a diagram schematically showing the timing of image capture in the third embodiment. Image capture is performed in six parts. First, as shown in FIG. 12A, the capacitor C3 is turned on in a state where all the pixel TFTs 11 for the horizontal odd pixels for one frame for red are turned on and all the horizontal odd pixels for one frame are displayed in red. Is stored in the buffer 13 in accordance with the stored charge. In this case, only the sensor 12 corresponding to the pixel TFT 11 for red display of the odd pixels in the horizontal direction receives the reflected light from the imaging target, and the received light amount is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0061]
Next, as shown in FIG. 12B, the binary data corresponding to the charge stored in the capacitor C3 is stored in the buffer 13 in a state where all the horizontal odd pixels of one frame are displayed in green. In this case, only the sensor 12 corresponding to the pixel TFT 11 for green display of the odd pixels in the horizontal direction receives the reflected light from the imaging target, and the received light amount is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0062]
Next, as shown in FIG. 12C, the binary data corresponding to the charge stored in the capacitor C3 is stored in the buffer 13 in a state where all the horizontal odd pixels of one frame are displayed in blue. In this case, only the sensor 12 corresponding to the pixel TFT 11 for blue display of the odd pixels in the horizontal direction receives the reflected light from the imaging target, and the received light amount is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0063]
Next, as shown in FIG. 12D, the binary data corresponding to the charge accumulated in the capacitor C3 is stored in the buffer 13 in a state where all the horizontal even pixels for one frame are displayed in red. In this case, only the sensor 12 corresponding to the pixel TFT 11 for red display of the even-numbered pixel in the horizontal direction receives the reflected light from the imaging target, and the amount of received light is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0064]
Next, as shown in FIG. 12E, the binary data corresponding to the charge accumulated in the capacitor C3 is stored in the buffer 13 in a state where all the horizontal even pixels for one frame are displayed in green. In this case, only the sensor 12 corresponding to the pixel TFT 11 for green display of the even-numbered pixel in the horizontal direction receives the reflected light from the imaging target, and the received light amount is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0065]
Next, as shown in FIG. 12F, the binary data corresponding to the charge stored in the capacitor C3 is stored in the buffer 13 in a state where all the horizontal even pixels for one frame are displayed in blue. In this case, only the sensor 12 corresponding to the blue display pixel TFT 11 of the even pixel in the horizontal direction receives the reflected light from the imaging target, and the amount of the received light is detected by the logic IC 7 via the capacitor C3 and the buffer 13. .
[0066]
FIG. 13 is a timing chart showing an example of the timing of image capture. First, from time t1 to t2, all horizontal odd pixels of one frame are displayed in red. Next, from time t3 to t4, the capacitor C3 and the buffer 13 are initialized, from time t4 to t5, imaging is performed by the sensor 12a, and from time t5 to t6, binary data corresponding to the accumulated charge of the capacitor C3 is buffered. 13 is stored. Thereafter, between times t7 and t8, the output of the buffer 13 is sequentially output line by line.
[0067]
Next, from time t9 to t10, all the horizontal odd pixels of one frame are displayed in green, and the same processing as in time t1 to t8 is performed, and the horizontal odd pixels of one frame are displayed in green. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0068]
Next, at times t11 to t12, all the horizontal odd pixels of one frame are displayed in blue, and the same processing as at times t1 to t8 is performed, and the horizontal odd pixels of one frame are displayed in blue. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0069]
Next, from time t13 to time t14, all the horizontal even pixels of one frame are displayed in red, and the same processing as that of time t1 to t8 is performed. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0070]
Next, from time t15 to t16, all the horizontal even pixels of one frame are displayed in green, and the same processing as that of time t1 to t8 is performed. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0071]
Next, from time t17 to time t18, all the horizontal even pixels for one frame are displayed in blue, and the same processing as in time t1 to t8 is performed. The image capturing result of the sensor 12 corresponding to the TFT 11 is output.
[0072]
As described above, in the third embodiment, since the capacitor C3 and the buffer 13 are shared by a plurality of pixels adjacent in the horizontal direction of the screen, the pixel structure can be further simplified as compared with the first embodiment, and the aperture ratio and The manufacturing yield can be further improved.
[0073]
Although FIG. 13 illustrates an example in which the capacitor C3 and the buffer 13 are shared by two pixels adjacent in the horizontal direction of the screen, the capacitor C3 and the buffer 13 may be shared by three or more pixels adjacent in the horizontal direction. .
[0074]
【The invention's effect】
As described above in detail, according to the present invention, since a plurality of photoelectric conversion units share the same charge accumulation unit, the configuration of the pixel can be simplified, and the aperture ratio and the manufacturing yield can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a first embodiment of a display device according to the present invention.
FIG. 2 is a block diagram showing a part of a pixel array section 3 in detail.
FIG. 3 is a circuit diagram showing a configuration of one pixel in detail.
FIG. 4 is a circuit diagram showing a detailed configuration of an SRAM.
FIG. 5 is a diagram illustrating an image capturing method.
FIG. 6 is a diagram schematically illustrating image capture timing according to the first embodiment.
FIG. 7 is a timing chart showing an example of image capture timing.
FIG. 8 is a circuit diagram showing in detail a configuration for one pixel in a second embodiment of the display device according to the present invention.
FIG. 9 is a diagram schematically illustrating image capture timing according to the second embodiment.
FIG. 10 is a timing chart showing an example of image capture timing.
FIG. 11 is a circuit diagram showing in detail a configuration for one pixel in a third embodiment of the display device according to the present invention.
FIG. 12 is a diagram schematically showing image capture timing according to the third embodiment.
FIG. 13 is a timing chart showing an example of image capture timing.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Semiconductor substrate 3 Pixel array part 4 Signal line drive circuit 5 Scan line drive circuit 6 Output signal processing part 7 Logic IC
11 pixel TFT
12, 12a, 12b, 12c Sensor 13 Buffer

Claims (8)

A display element formed near each intersection of a signal line and a scanning line arranged in columns in the first and second directions;
A photoelectric conversion unit that is provided one by one corresponding to each of the display elements, each of which receives incident light and outputs an electric signal according to a received light amount;
A charge accumulating unit that is provided for each set of two or more photoelectric conversion units and accumulates charges corresponding to electric signals output from the two or more photoelectric conversion units in each set;
A drive control unit that sequentially drives the two or more photoelectric conversion units of each set so that electric charges corresponding to the amounts of light received by the two or more photoelectric conversion units of each set are sequentially accumulated in the charge accumulation unit. A display device comprising: The display element is provided one for each of the three color sub-pixels in the same pixel,
The photoelectric conversion unit is provided one by one corresponding to each of the three display elements in the same pixel,
The display device according to claim 1, wherein the charge storage unit is provided for each of the three photoelectric conversion units in the same pixel. While the drive control unit is sequentially driving all the display elements for the first color for one frame, the charge accumulation unit accumulates charges according to the amount of light received by the corresponding photoelectric conversion unit, Thereafter, while the drive control unit sequentially drives all the display elements for the second color for one frame, the charge accumulation unit accumulates charges according to the amount of light received by the corresponding photoelectric conversion unit. Then, while the drive control unit sequentially drives all the display elements for the third color for one frame, the charge storage unit stores the charge corresponding to the amount of light received by the corresponding photoelectric conversion unit. 3. The display device according to claim 2, wherein the display device is stored. 2. The display device according to claim 1, wherein the charge storage unit is provided for each of a plurality of photoelectric conversion units corresponding to a plurality of pixels arranged adjacent in the first direction. 3. The photoelectric conversion unit is provided one for each of the plurality of photoelectric conversion units corresponding to two pixels arranged adjacent to each other in the first direction,
While the drive control unit is sequentially driving all of the display elements for one frame arranged in one of the odd-numbered and even-numbered ones in the first direction, the charge accumulation unit operates in accordance with the corresponding photoelectric conversion. The drive control unit sequentially drives all the display elements for one frame arranged at the other of the odd-numbered and even-numbered in the first direction. 5. The display device according to claim 4, wherein the charge storage unit stores a charge corresponding to an amount of light received by the corresponding photoelectric conversion unit. The display device according to claim 1, wherein the charge storage unit is provided for each of a plurality of photoelectric conversion units corresponding to a plurality of pixels arranged adjacent to each other in the second direction. The photoelectric conversion unit is provided one for each of the plurality of photoelectric conversion units corresponding to two pixels arranged adjacent to each other in the second direction,
While the drive control unit is sequentially driving all the display elements for one frame arranged in one of the odd-numbered and even-numbered ones in the second direction, the charge accumulating unit performs the corresponding photoelectric conversion. After accumulating charges corresponding to the amount of light received by the unit, the drive control unit sequentially drives all of the display elements for one frame arranged on the other of the odd and even numbers in the second direction. 7. The display device according to claim 6, wherein the charge storage unit stores a charge corresponding to an amount of light received by the corresponding photoelectric conversion unit. 8. The display device according to claim 1, wherein the charge storage section includes a refresh circuit.

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