JP2006244407A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device with an image capturing function with high manufacture yield for complementing image data where there is any dot-like defect or linear defect, and for suppressing the increase of the circuit scale and costs of an external IC. <P>SOLUTION: This display device includes a plurality of scanning lines X arrayed in parallel, a plurality of scanning lines Y arrayed so that they can cross the plurality of scanning lines X, a plurality of pixel circuits 122 arranged at intersecting portions 120 between the plurality of scanning lines X and the plurality of scanning lines Y, at least one sensor circuit 124 arranged at one or each of those plurality of pixel circuits 122, a signal line drive circuit 134 and a scanning line drive circuit 132 for driving the plurality of pixel circuits 122 through the plurality of scanning lines X and the plurality of scanning lines Y and a control means for controlling the sensor circuit 124. The control means is provided with a filter 152 for complementing the gradation value of an image to be displayed by at least the pixel circuit 122. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device having an image capturing function.

  In recent years, liquid crystal display devices and organic EL displays have been developed as display devices for various devices such as mobile phones and notebook computers.

  In general, a liquid crystal display device includes an array substrate in which display pixels having thin film transistors (TFTs), liquid crystal capacitors, and auxiliary capacitors are arranged at intersections of a plurality of scanning lines and a plurality of signal lines, and scanning lines and signal lines. And a drive circuit for driving. In recent years, with the development of integrated circuit technology and the practical application of process technology, a part of the drive circuit can be formed on the array substrate, and the entire liquid crystal display device has been reduced in size and thickness.

  On the other hand, a display device with an image capturing function in which a contact area sensor having an image capturing function is arranged on an array substrate has been proposed as a display device with an optical input function.

  A conventional liquid crystal display device having this type of image capturing function includes a display unit including, for example, a liquid crystal pixel unit arranged at each intersection of a plurality of scanning lines and a plurality of signal lines, and a photodiode, for example. The image data is obtained by detecting the voltage at both ends of the capacitor by changing the amount of charge of the capacitor connected to the photodiode constituting the light detecting means according to the amount of light received by the photodiode. Generate and capture images.

  In a display device having such an image capturing function, a method for obtaining multi-gradation image data corresponding to the irradiation intensity of incident light from image data obtained under a plurality of imaging conditions by image processing has been proposed.

  There has also been proposed a method for capturing an image while displaying an image by inserting an imaging frame between display frames for displaying the image. When this method is used, it can be used as a coordinate input device for a display device by touching the display screen of the display device with a finger or irradiating light on the display screen using, for example, a pen-type light source. Coordinate calculation algorithms and click detection algorithms have been proposed.

  In the above-described conventional display device with an image capturing function, image data having a dot defect or a line defect generated due to a manufacturing process is output to the outside as it is, so that the defect is compensated by using an external IC. Image processing is required. In order to perform this image processing, a memory corresponding to several lines of image data is usually required in the IC, so that there is a problem that the circuit scale of the IC increases and the cost also increases.

Conversely, when complement processing is not performed by an external IC, it is necessary to select only a display device with an image capturing function that is free from defects, resulting in a decrease in manufacturing yield.
JP 2002-182839 A

  The present invention has been made in view of the above-described problems, and complements a part that is partially lost due to a point defect or a line defect, and suppresses an increase in circuit scale and cost of an external IC, and It is an object of the present invention to provide a display device with an image capturing function having a high manufacturing yield.

  A display device according to one embodiment of the present invention includes a plurality of scanning lines arranged in parallel, a plurality of signal lines arranged to intersect the plurality of scanning lines, the plurality of scanning lines, and the plurality of signals. A plurality of display pixels arranged at intersections with the lines, at least one photodetecting unit provided for each one or a plurality of the display pixels, the plurality of scanning lines, and the plurality of signal lines, Driving means for driving the plurality of display pixels via an output controller, and an output control unit for controlling the light detection unit, wherein the output control unit determines at least a gradation value of an image displayed on the display pixel. It has a complementary filter.

  According to the present invention, it is possible to provide a display device with an image capturing function that complements image data having a point defect or a line defect, suppresses an increase in circuit scale and cost of an external IC, and has a high manufacturing yield. Is possible.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings.

  FIG. 1 is a block diagram for explaining the operations of the array substrate 100 of the display device with an image capturing function and the external IC 200 that controls the imaging operation of the array substrate 100 and receives and processes imaging data. As shown in FIG. 1, the display device 10 with an image capturing function is, for example, a liquid crystal display driven by a polysilicon thin film transistor circuit on a glass substrate.

  The external IC 200 is a dedicated ASIC, digital signal processor DSP, central processing unit CPU, etc., and coordinates are input by redisplaying the captured image on a display, storing it in a storage device, or processing the captured image. It performs various processes such as. However, the description of the portion for controlling the display operation by the external IC 200 is omitted here.

  In the display area 110 on the array substrate 100, a plurality of scanning lines X arranged in parallel and a plurality of signal lines Y arranged so as to intersect the plurality of scanning lines X are formed. FIG. 1 shows one scanning line X (n) and one signal line Y (m). At intersections 120 of the plurality of scanning lines X and the plurality of signal lines Y, a pixel circuit 122 as a display unit and a sensor circuit 124 as a light detection unit are arranged. In FIG. 1, one pixel circuit 122 and one sensor circuit 124 are shown as representatives.

  Around the display area 110 on the array substrate 100, a drive circuit for driving the image circuit 122 via the plurality of scanning lines X and the plurality of signal lines Y is formed. This driving circuit includes a scanning line driving circuit 132 that drives the plurality of pixel circuits 122 in units of rows, and a signal line driving circuit 134 that supplies respective image signals to the driven pixel circuits 122.

  A control means for controlling the plurality of sensor circuits 124 is provided around the display area 110 on the array substrate 100. This control means includes a precharge circuit 138 for precharging the sensor circuit 124, a sensor control circuit 136 for designating the sensor circuit 124 in units of rows, and an A / D for analog / digital conversion of the output from the sensor circuit 124. A conversion unit 140 and an output control unit 150 that receives digital data output from the A / D conversion unit 140 and outputs the digital data to the external IC 200 are included. The output control unit 150 includes a filter 152 and a data transfer unit 154.

  In the array substrate 100, first, incident light intensity information is converted into an analog signal using a sensor circuit 124 provided in the intersection 120, and the analog signal is converted by an A / D converter 140 provided around the array substrate 100. Convert to digital image data. The digital image data is output to the external IC 200 by the imaging data output controller 150 provided around the array substrate 100. The output control unit 150 includes a filter 152 and a data transfer unit 154. Data output from the A / D conversion unit 140 is filtered by the filter 152 of the output control unit 150 and is serially output to the external IC 200 by the data transfer unit 154.

  2A and 2B illustrate basic circuit configuration examples of the pixel circuit 122 and the sensor circuit 124 illustrated in FIG. As shown in FIG. 2A, light input is made to the array substrate 100 by a light pen 700. A transparent film 102 is coated or attached to the outside of the array substrate (glass substrate) 100 for protecting the glass. On the inner surface side of the array substrate 100, a plurality of scanning lines X, a plurality of signal lines Y, a pixel circuit 122, and a sensor circuit 124, which are not shown here, are formed using a printing technique and a vapor deposition technique.

  The PIN diodes D1, D2, and D3 formed on the inner surface side of the array substrate 100 each function as a photosensitive element in the sensor circuit 124. The periphery of the PIN diodes D1, D2, and D3 is surrounded by the insulating layer 103. In addition, light shielding films SH1, SH2, and SH3 are formed on the insulating layer 103 so as to face the PIN diodes D1, D2, and D3.

  A counter substrate 105 is disposed at a distance from the array substrate 100. The counter substrate 105 has a common electrode (transparent electrode) and faces the array substrate 100. A liquid crystal layer 104 is sandwiched between the array substrate 100 and the counter substrate 105. A backlight 106 is disposed outside the counter substrate 105. When the light emitted from the backlight 106 passes through the counter substrate 105, the liquid crystal layer 104, and the array substrate 100, the transmission state is controlled, and an image is obtained on the display screen.

  FIG. 2B illustrates a basic circuit configuration example of one sensor circuit 124. The source of the switch (thin film transistor) TR2 is connected to the signal line Y (m). The drain of the switch TR2 is connected to the cathode of the photodiode PD and to one electrode of the sensor capacitor CP. The anode of the photodiode PD and the other electrode of the sensor capacitor CP are connected to a ground line having a predetermined potential. The gate of the switch TR2 is connected to the reset control line CRT (n).

  In the sensor circuit 124, the sensor capacitor CP is precharged in the second half of the specific horizontal blanking period, and reading is performed in the first half of the specific horizontal blanking period of the next cycle (after one vertical period). When the amount of light applied to the photodiode PD after the precharge is large, the discharge amount of the sensor capacitor CP is large. Conversely, when the amount of light applied to the photodiode PD is small, the discharge amount of the sensor capacitor CP is small. A light shielding process is performed between the photodiode PD and the backlight. Therefore, the sensor output can be obtained by outputting the voltage of the sensor capacitor CP through the amplifier during the readout period.

  FIG. 3A illustrates a configuration example of the pixel circuit 122 and the sensor circuit 124 described above. As shown in FIG. 3A, the voltage line Cs is a voltage line that applies a predetermined potential to the one electrode of the auxiliary capacitor Csk and the liquid crystal LC at a predetermined cycle. The gate line Gate (n) is a gate line for performing on / off control of the driving transistor TR1 of the pixel circuit 122.

  The reset control line CRT (n) is a control signal line for ON / OFF control of the switch TR2 constituting the sensor circuit 124. When the switch TR2 is turned on, the sensor capacitor CP is precharged. GND is a ground line. SFB (n) is a sensor output control line that turns on the thin film transistor TR4 when reading the potential of the sensor capacitor CP. The thin film transistor TR3 functions as an amplifying element. The photodiode PD is sensitive to light and passes a current corresponding to the amount of light. Thereby, the charge precharged in the sensor capacitor CP can be released.

  The signal lines Y (m−1), Y (m), and Y (m + 1) are connected to the signal line driver circuit 134 and the A / D converter 140 shown in FIG. The power supply line Cs and the gate line Gate (n) are connected to the scanning line driving circuit 132 shown in FIG. 1, and the reset control line CRT (n), the ground line GND, and the sensor control line SFB (n) are The sensor control circuit 136 is connected.

  FIG. 3B is a timing chart for explaining the operation of the above circuit. In the above circuit, one specific horizontal period within one vertical period (one frame period) is set as follows. In the pixel circuit 122, one horizontal period (1H) is divided into a first blank period, a common inversion blank period, a writing period, and a second blank period. In correspondence with these four periods, the sensor circuit 124 is divided into an output period, a common inversion timing period, and a precharge period. Except for the above four periods within one vertical period (one frame period), the pixel circuit 122 is a display period, and the sensor circuit 124 is an imaging period.

  In the pixel circuit 122, an image signal is written to the auxiliary capacitance Csk via the signal line Y (m + 1) through a path indicated by an arrow a1 during the writing period. The liquid crystal LC is driven in accordance with the voltage value generated between both ends of the capacitor Csk, and gradation display is performed.

  In the sensor circuit 124, following the writing period, the transistor TR2 is turned on, and the capacitor CP is precharged. At this time, the capacitor CP is precharged through the signal line Y (m + 1) through the path shown by the arrow b1 and the arrow c1. That is, the writing period and the precharge period are shifted, and the signal line Y is effectively used. When a current flows through the photodiode PD during the imaging period, the precharge voltage changes.

  In the next one frame cycle, when the transistor TR4 is turned on during the output period, the voltage of the sensor capacitor CP is amplified by the transistor TR3 and taken out via the signal line Y (m) (paths of arrows d1 and e1). The same operation is also performed in the next horizontal period in the pixels and sensor units of the adjacent horizontal line. The voltage extracted from the sensor capacitor CP changes in accordance with the time during which the photodiode PD is shielded from light after precharge until read start. When the light is not shielded at all, the read voltage is sufficiently low, and when the light is shielded for a long time, a high voltage is obtained. Thereby, it is determined whether or not an input is made by the light pen 700.

  FIG. 4 is an explanatory diagram showing the above operation in units of frames. FIG. 4 shows, for example, the Nth frame and the (N + 1) th frame. The above processing is performed during a specific horizontal period of the Nth frame, and during the period up to the specific horizontal period of the (N + 1) th frame, the pixel circuit 122 displays an image and the sensor circuit 124 captures light.

  Next, filter processing for the output from the sensor circuit 124 will be described. As illustrated in FIG. 1, when a certain scanning line X (n) is activated, an analog signal for one row of pixels output from the sensor circuit 124 is input to the A / D converter 140. The output of the A / D conversion unit 140 is input to the output control unit 150 as digital image data.

  FIG. 5 shows an example of the operation of the apparatus of the present invention. FIG. 5 illustrates the gradation value F (x, y) of the target pixel at the position (x, y) and the gradation value F (x−1, For example, a total of nine gradation values (left side in the figure) such as y-1), F (x, y-1),... The rank order filter processing in the vicinity of 3 × 3 is shown in which the larger one is adopted as the new gradation value G (x, y) (right side of the drawing) of the pixel of interest (x, y). A circuit that realizes such processing is a circuit as described below.

  FIG. 6 shows a circuit configuration example for processing an output signal from the sensor circuit 124. When a certain scanning line X (n) is activated, the sensor circuit 124 connected to the scanning line X (n) outputs the detected light intensity to the A / D converter 140 as an analog signal. The A / D conversion unit 140 includes an A / D conversion circuit ADC corresponding to each signal line, and a delay flip-flop D-FF1. The A / D conversion circuit ADC converts the analog signal input from the sensor circuit 124 into digital data. The delay flip-flop D-FF1 takes in the output of the A / D conversion circuit ADC at a predetermined timing once in one horizontal period.

  In the present embodiment, the A / D conversion circuit ADC corresponds to, for example, 1-bit data, and 1-bit image data of pixels for one row is captured in each delay flip-flop D-FF1.

  The adder circuit SUM3 is a combinational circuit that outputs the sum of 1-bit image data for three pixels adjacent in the row direction. The adder circuit SUM3 outputs an input value as in the truth table shown in FIG.

  The output from the adder circuit SUM3 is input to three delay flip-flops D-FF2 connected in series. The delay flip-flop D-FF2 transfers the output of the adder circuit SUM3 at a predetermined timing every horizontal period, and can thereby hold the output of the adder circuit SUM3 for three rows. The two adders PL1 and PL2 take the sum of the data for the above three rows, and the sum is taken into the delay flip-flop D-FF3 at a predetermined timing every horizontal period.

  From the above, the delay flip-flop D-FF3 takes in the gradation values for three stages of three pixels adjacent in the row direction, that is, the sum of the gradation values in the vicinity of 3 × 3 every horizontal period. It will be.

  The output from the delay flip-flop D-FF3 is input to the comparator COMP4. The comparator COMP4 circuit is a 4-bit comparator that compares the value of the delay flip-flop D-FF3 with the specified rank value r. FIG. 7B shows the input / output relationship. This corresponds to replacing the gradation value of the target pixel with 1 when the sum of gradation values in the vicinity of 3 × 3 is greater than or equal to the rank value, and 0 when the sum is less than the rank value.

As a result, in the filter 152, for example, the gradation value F (x, y) of the target pixel shown in FIG. Convert to gradation value. That is, the rank order filter process of the rank value r is performed. If the image data is 1 bit,

As described above, the filter 152 converts the gradation value F (x, y) of the target pixel to 1 when the value of all neighboring pixels is added and is equal to or higher than the rank value r, and is converted to 0 when it is lower than the rank value r. To do.

  The output line of the comparator COMP4 is connected to the data transfer unit 154. The data transfer unit 154 has a delay flip-flop D-FF4 connected to each filter circuit via a switch HSW. The delay flip-flop D-FF4 is a shift register for serially outputting data to the outside.

  First, at a predetermined timing every horizontal period, the switch HSW is turned on and the switch TSK is turned off. During this time, the transfer clock rises (or falls) once, whereby the delay flip-flop D-FF4 receives the pixel 1 Lines of data are retained. Thereafter, the switch TSK is turned on and the switch HSW is turned off, and data is sequentially transferred according to the transfer clock.

  FIG. 8 shows an example of a result obtained by performing the filtering process on the pixels in the vicinity of 3 × 3 by the filter 152 described above. The image shown in FIG. 8A is an image when no filter processing is performed, and is output to the external IC 200 when coordinates are input by irradiating the array substrate 100 with light from the light pen 700 or the like. Binary image data. The white circle on the left side of the image corresponds to the pointing unit of the light pen 700, and the white line running vertically on the right side of the image corresponds to a linear defect caused by a defect in the A / D conversion circuit ADC.

  FIG. 8B, FIG. 8C, and FIG. 8D show an example of results when the rank order r values of the rank order filters are different. FIG. 8B shows the result when the rank value r is set to 5. This is a case where the rank order filter is a median filter, which is a special case thereof, and complements the point defect and the line defect. FIG. 8C shows the result when the rank value r is set to 9. In this case, the pointing portion of the light pen 700 and the white area of the linear defect are contracted (contraction processing). FIG. 8D shows the result when the rank value r is set to 1. In this case, the pointing portion of the light pen 700 and the white area of the linear defect are expanded (expansion process).

  As described above, the effect of complementing the point defect or the line defect or expanding / contracting the white region is obtained by the value of the rank value r set by the rank order filter circuit.

  The rank value of the rank order filter circuit may be determined by the external IC 200 or a circuit on the array substrate 100. The rank value may be a fixed value, or may be dynamically changed by being controlled by the external IC 200 or the circuit on the array substrate 100.

  Since the rank order filter circuit is formed on the array substrate 100, the circuit scale of the external IC 200 is not increased, and an increase in cost can be suppressed. In addition, it is not necessary to select a display device with an image capturing function that is free from defects, and the manufacturing yield is increased. Furthermore, by forming a rank order filter circuit on the array substrate 100, it is possible to efficiently capture image data.

  Further, since the rank order filter circuit is formed corresponding to each signal line, rank order filter processing for one row of pixels can be performed in parallel. Further, the filtering process can be performed with a clock of one horizontal cycle, and a high-speed clock is not required.

  Next, a second embodiment of the present invention will be described. The circuit shown in FIG. 9 uses, as the filter 152, a median filter circuit that is a special case of a rank order filter circuit (a rank order filter circuit near 3 × 3 and a rank value r is 5). In this case, the circuit can be implemented by changing the rank value r in the rank order filter circuit described above, but a more simplified circuit configuration is also possible. FIG. 9 shows a detailed circuit configuration example.

  Only the circuit portion of the filter 152 shown in FIG. 9 is different from FIG. The sort circuit SORT3 is a combination circuit that sorts and outputs three input values in ascending order, and the sort circuit SORT2 is a combination circuit that sorts and outputs two input values in ascending order. The sort circuit SORT3 and the sort circuit SORT2 output signals as shown in the truth tables of FIGS. 10A and 10B, respectively.

  Among the values sorted by the sort circuit SORT3 or the sort circuit SORT2, the minimum value, the intermediate value, and the maximum value are output to the nodes S, M, and L. The four-stage delay flip-flop D-FF5 fetches three rows of pixels having the smallest gradation value among the adjacent three columns of pixels, and outputs the largest one of the three rows to the final stage. Similarly, the delay flip-flop D1FF6 takes in three rows of pixels with intermediate gradation values among the three columns of pixels, and outputs the intermediate one of the three rows to the final stage. The delay flip-flop D-FF7 takes in three rows of pixels with the maximum gradation value among the pixels in the three columns, and outputs the smallest one of the three rows to the final stage.

  Finally, the output of the final stage of the delay flip-flop D-FF5, the delay flip-flop D-FF6, and the delay flip-flop D-FF7 is input to the sort circuit SORT3, and the gradation value at the center order thereof is displayed. The data is output to the data transfer unit 154. As a result, among the gradation values of pixels in the vicinity of 3 × 3 of the target pixel, the gradation value of the pixel whose rank value r is 5 is output to the data transfer unit 154. That is, the filter 152 performs median filter processing.

  Also for the median filter circuit described above, the image shown in FIG. 8B can be obtained by performing the filtering process. Further, as in the case of using the rank order filter circuit described above, the circuit scale of the external IC 200 is not increased, and an increase in cost can be suppressed. Furthermore, it is not necessary to select a display device with an image capturing function that is free from defects, and the manufacturing yield is increased. Further, by forming the median filter circuit on the array substrate, it is possible to efficiently capture image data.

  Further, since the median filter circuit is formed corresponding to each signal line, parallel processing is possible with a clock of one horizontal cycle, and a high-speed clock is not required.

  Next, a third embodiment of the present invention will be described. FIG. 11 is a block diagram of an example of an embodiment that executes filter processing serially.

  In the present embodiment, the output control unit 150 includes a data transfer unit 154 that serially outputs data for three rows of pixels. The analog signal output from the sensor circuit 124 is converted into digital image data by the A / D converter 140 and input to the output controller 150. In the output control unit 150, digital image data transferred by the data transfer unit 154 for three rows is serially filtered by the filter 152 connected to the final stage of the output control unit 150 and output to the outside.

  FIG. 12 shows an example of a detailed circuit configuration when a rank order filter, for example, is used as the filter 152. The delay flip-flop D-FF4 is a shift register that transfers data in the right direction in the figure according to the transfer clock when the switch TSK is in the ON state as described above. On the other hand, the delay flip-flop D-FF8 is a shift register that transfers data downward in the figure in accordance with a transfer clock while the switch HSW is in an ON state.

  First, the switch HSW is turned on and the switch TSK is turned off at a predetermined timing every one horizontal period, and the vertical transfer clock rises (or falls) once during that time, whereby the delay flip-flop D-FF8 generates a pixel. One row of data is transferred and held in the downward direction in the figure. At the same time, when the horizontal transfer clock rises (or falls) once, data for one row of pixels is held in the delay flip-flop D-FF4. Thereafter, the switch TSK is turned on and the switch HSW is turned off, and data is transferred in the right direction in the figure according to the horizontal transfer clock.

  That is, three rows of data are transferred by the delay flip-flop D-FF4 during one horizontal period. Therefore, processing is executed serially by connecting a rank order filter circuit to the final stage of the delay flip-flop D-FF4.

  Even in the case of a circuit configuration that performs serial filter processing as described above, images after filter processing as shown in FIGS. 8B to 8D are obtained according to the set value of the rank value r of the rank order filter. be able to. Further, in addition to the same effect as the case of performing the filter processing in parallel shown in FIG. 6, if the circuit is configured to perform the filter processing serially as described above, the occupation area of the rank order filter circuit is the same as the parallel processing described above. It can be made smaller than the case of performing.

  Note that the image data for three rows may be directly output to the external IC 200 as three signals. In this case, it is necessary to form a rank order filter circuit in the external IC 200. However, since a line memory is unnecessary, the circuit scale and cost of the external IC 200 are hardly affected. As in the case of parallel processing, the rank value r of the rank order filter circuit may be determined by the external IC 200 or the circuit on the array substrate 100. The rank value r may be a fixed value or may be changed dynamically.

  FIG. 13 shows a case where a median filter circuit is used as the filter circuit. In this case, the same effect as that shown in FIG. 12 can be obtained.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

1 is a block diagram of an array substrate and an external IC of a display device according to an embodiment of the present invention. FIG. 2 is a diagram showing a basic circuit configuration example of a pixel circuit and a sensor circuit shown in FIG. 1. FIG. 2 is a diagram illustrating a configuration example of a pixel circuit and a sensor circuit illustrated in FIG. 1 and a timing chart thereof. FIG. 4 is a diagram for explaining an operation example of the circuit shown in FIG. 3 in units of frames. The figure which shows the circuit structural example for the process with respect to the output of the sensor circuit shown in FIG. The figure which shows the circuit structural example which performs the process with respect to the output of the sensor circuit shown in FIG. FIG. 7 is a diagram illustrating an input / output example of an addition circuit and a comparator illustrated in FIG. 6. The figure which shows an example of the result of having performed the filter process by the circuit shown in FIG. The figure which shows the circuit structural example which performs the process with respect to the output of the sensor circuit of the display apparatus which concerns on 2nd Embodiment of this invention. FIG. 10 is a diagram showing an input / output example of the sort circuit shown in FIG. 9. The block diagram of the array board | substrate and external IC of the display apparatus which concern on 3rd Embodiment of this invention. The figure which shows an example of the circuit structure which performs the process with respect to the output of the sensor circuit shown in FIG. FIG. 12 is a diagram showing another example of a circuit configuration that performs processing on the output of the sensor circuit shown in FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Display apparatus, 100 ... Array substrate, 110 ... Display part, 122 ... Pixel circuit, 124 ... Sensor circuit, 132 ... Scanning line drive circuit, 134 ... Signal line drive circuit, 136 ... Sensor control circuit, 138 ... Precharge circuit 140 ... A / D conversion unit, 150 ... output unit, 152 ... filter, 154 ... data transfer unit, 200 ... external IC, X ... scan line, Y ... signal line,

Claims (6)

A plurality of scan lines arranged in parallel;
A plurality of signal lines arranged to intersect the plurality of scanning lines;
A plurality of display pixels arranged at intersections of the plurality of scanning lines and the plurality of signal lines;
A light detection unit provided at least one for each one or a plurality of the display pixels;
Driving means for driving the plurality of display pixels via the plurality of scanning lines and the plurality of signal lines;
An output control unit for controlling the light detection unit,
The output control unit is a display device having an image capturing function having a filter that complements at least a gradation value of an image displayed on the display pixel.   The display device having an image capturing function according to claim 1, wherein the output control unit further includes an A / D conversion unit that generates digital image data from a light detection signal of the light detection unit.   The filter rearranges the gradation values of the digital image data corresponding to the predetermined display pixels and at least one display pixel in the vicinity thereof in ascending or descending order, and converts the gradation values of a designated order. The display device having an image capturing function according to claim 2, wherein a gradation value of the predetermined display pixel is used.   The display device having an image capturing function according to claim 3, wherein the designated order can be dynamically changed.   The filter rearranges the gradation values of the digital image data corresponding to the predetermined display pixel and at least one display pixel in the vicinity thereof in ascending or descending order, and sets the gradation value of the middle order to a predetermined value. The display device according to claim 2, further comprising an image capturing function for setting a gradation value of the display pixel.   The display device having an image capturing function according to claim 2, wherein the A / D conversion unit corresponds to 1-bit data, and the digital image data is 1-bit digital image data.

Images