JP2004153291A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that there is a possibility such that a parasitic capacity is added to a gate electrode if a dummy-active is present at the lower part of the gate electrode and that an actual active and the dummy active is short-circuited electrically if particles are mixed in the manufacturing process. <P>SOLUTION: The semiconductor device comprises a gate electrode layer formed on a semiconductor substrate, an element isolation region formed by a trench, and a dummy active region, and the distance between the dummy active region and the gate electrode layer is greater than or equal to 0.5 μm. With this configuration, it is possible to suppress the parasitic capacity, faults due to the influence of the particles, etc. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a semiconductor device, and more particularly to a dummy active pattern in a semiconductor device in which an active region is formed by trench element isolation.

  2. Description of the Related Art As a technique for forming an element isolation region in a semiconductor device, an element isolation technique using a trench has attracted attention. Usually, in element isolation using a trench, an oxide film embedded in the trench is polished by chemical mechanical polishing (CMP). In the polishing step, the polishing rate of the buried oxide film varies depending on the pattern of the trench. Therefore, in order to average the overall polishing rate in the polishing step, a dummy active pattern is appropriately arranged even in a region where a normal active is not formed.

  However, if a dummy active exists below the gate electrode, a parasitic capacitance may be added to the gate electrode. Further, there is a possibility that the actual active and the dummy active may be electrically short-circuited due to mixing of particles in the manufacturing process.

  In order to solve the above problems, a semiconductor device of the present invention has a gate electrode layer formed on a semiconductor substrate, an element isolation region formed by a trench, and a dummy active region. The distance between the region and the gate electrode layer is 0.5 μm or more.

  According to the present invention, it is possible to reduce a parasitic capacitance and a defect due to the influence of particles.

  Hereinafter, the semiconductor device of the present invention will be described in detail with reference to the drawings. In each of the drawings, the same components are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Hereinafter, Embodiment 1 of the present invention will be described with reference to FIG. Note that the cross-sectional view shown in FIG. 1 is basically a cross-sectional view in a region where a dummy active is to be formed. It is natural to be done.
First, a PAD oxide film 2 having a thickness of about 2000 mm is formed on a semiconductor substrate 1 by using a CVD method, and thereafter, a SiN film 3 which is a nitride film having a thickness of about 500 to 5000 mm is formed by the CVD method. (FIG. 1-A) A resist is applied to the entire surface, and the resist 4 is patterned using a mask having a pattern of a trench formation portion. (FIG. 1-B) Using the resist 4 as a mask, the SiN film 3 and the PAD oxide film 2 are etched by plasma etching to open a portion where a trench is to be formed. Thereafter, the silicon substrate 1 is further etched to form the trench portions 5.
The trench formed at this time has a depth of 2500 to 5000 degrees, and has a shape having a slight taper angle of about 70 to 90 degrees near the substrate surface. That is, in the trench 5, the width of the opening is slightly wider than the width of the bottom. The reason for providing the taper angle in the trench portion 5 in this manner is to ensure that the oxide film is sufficiently buried near the bottom of the trench in the subsequent oxide film burying step.

In a region where a dummy active is to be formed, the trench is formed according to the size of the dummy active. In the present embodiment, the width of the trench is 0.5 μm to 10 μm at the opening, and is formed every 0.5 μm to 1 μm. (FIG. 1-C) Thereafter, a buried oxide film 6 is formed on the entire surface of the wafer. By this step, trench portion 5 is filled with oxide film 6. This oxide film is formed by an HDP (High Density Plasma) -CVD method. This is a technique of forming a film by a CVD method while applying high-density plasma, and it is possible to form an oxide film with good film quality. (FIG. 1-D) The buried oxide film 6 remaining on the trench is polished to the surface of the SiN film 3 by chemical mechanical polishing (CMP). (Fig. 1-E)
Thereafter, the SiN film 3 and the PAD oxide film 2 are removed, and the step of forming the trench isolation is completed. (FIG. 1-F) At this stage, the area surrounded by the trench isolation groove becomes the dummy active area 7 of the present invention. In the present invention, the shape of the dummy active 7 is formed based on rules described in detail below.

In the first embodiment, the active shape of the dummy is basically a rectangle. At this time, the portion corresponding to the short side of the rectangle is patterned so that the length is 0.5 μm or more and 1 μm or less. The portion corresponding to the long side of the rectangle is formed so that its length is at least 0.5 μm or more. This top view is schematically shown in FIG. In the present invention, the reason why the length of the side of the dummy active pattern is 0.5 μm or more and the length of the short side of the dummy active rectangle is 1 μm or less will be described below.
First, it is assumed that the length of each side of the dummy active is 0.5 μm or less. In the case of a positive resist generally used for fine processing, in a resist exposure / development step, an exposed portion of the resist is removed by ashing. In order to form a fine dummy active shape, the width of the resist remaining in the resist patterning step (see FIG. 1-B) must be 0.5 μm or less on each side. However, when using a mask with a fine pattern of 0.5 μm or less on each side to expose the resist other than the necessary parts, the resist at the parts that you do not want to expose due to phenomena such as light wraparound is also exposed. In some cases. When such light wraparound occurs, the entire pattern of 0.5 μm or less on each side is exposed, and the risk that the entire resist corresponding to the desired active pattern is exposed is greatly increased. When the entire resist is exposed, naturally, the desired dummy active is not formed.
In order to prevent the dummy active pattern from disappearing during exposure due to such light wraparound, it is necessary to define the minimum dimension of the side of the dummy active pattern.
According to the experiments by the present inventors, at least one side of the dummy active pattern needs to be 0.5 μm or more in order to eliminate the possibility that the entire resist is exposed. Thus, such a problem can be avoided.

  It is assumed that the short side of an active dummy to be formed next is 1 μm or more. In this embodiment, the oxide film embedded in the trench is an oxide film embedded by the HDP-CVD method as described above. When an oxide film is formed by the HDP-CVD method, the cross-sectional shape of the oxide film changes depending on the underlying pattern. This will be described in detail with reference to FIG. FIG. 3 is a cross-sectional view during the formation of an oxide film by the HDP-CVD method. In this case, it is known that the oxide film tends to be deposited at a predetermined angle with respect to the dummy active substrate surface. Generally, this angle is formed at an angle in the range of 45 ° ± 10 ° with respect to the substrate surface as shown in FIG. When the length of the short side of the dummy active is 1 μm or more, as shown in FIG. 3, the oxide film is formed in a portion having a thickness of about 1 μm and a shape having a flat surface at the top.

As described above, when the flat portion exists on the top portion, the HDP oxide film itself is easily deposited on the flat portion. On the other hand, as shown in FIG. 3, when the active width is 1 μm or less and the vertex exists in the cross-sectional shape of the oxide film, the oxide film is less likely to be deposited above the vertex. As a result, a difference in thickness of the oxide film is generated based on the active shape of the dummy. If a difference in the thickness of the oxide film occurs, it is extremely difficult to make the polishing uniform in the subsequent CMP process.
If a peak exists, the pressure during polishing by CMP concentrates on the peak. On the other hand, when the top of the oxide film is flat, the pressure is dispersed. As a result, there is a difference in the polishing rate based on the shape of the top of the oxide film, that the shape having the apex is polished faster. Therefore, in order to uniformly polish the oxide film, it is necessary to make the shapes of the apexes coincide. According to a detailed experiment by the present inventors, an oxide film having a vertex in a cross-sectional shape can be formed when the short side of the dummy active is set to 1 μm or less. Therefore, by setting the length of at least the short side to 1 μm or less, an oxide film having a uniform thickness can be obtained, the shape of the top portion of the oxide film is stabilized, and stable CMP polishing can be performed.
As described above in detail, the shape of the dummy active in the first embodiment is such that the dummy active has a rectangular shape, the dimension of the side is 0.5 μm or more, and the dimension of the short side is 1 μm or less. Averaging becomes possible.

Embodiment 2 is shown in FIG. FIG. 4 shows an example in which dummy active patterns are arranged on a chip or the like.
On the actual chip 40, a region 41 where an original element is formed, a first-layer gate electrode 42 crossing over the active, a dummy active 43, and the like are formed.
When the dummy active 43 exists below the gate electrode 42, a parasitic capacitance is added to the gate electrode. In particular, in the case where the dummy active 43 is formed under the gate electrode 42 of the first layer (the layer closest to the substrate), the speed of the transistor is reduced. The lower part is arranged so that the dummy active 43 is not formed.

Also, when a dummy active pattern is formed in the vicinity of the active 41 where the element is actually formed, the actual active 41 and the dummy active 43 are electrically short-circuited due to mixing of particles or the like in a manufacturing process. There is.
According to the detailed experiments of the present inventors, in order to reduce the above-mentioned parasitic capacitance and to reduce defects due to the influence of particles, the distance between the dummy active 43 and the active 41 (L1 in FIG. 4) and the dummy active 43 The distance between the gate electrodes 41 (L2 in FIG. 4) needs to be 0.5 μm or more.
This is because the size of the particles in the manufacturing plant is almost 0.5 μm or less, and if the above-mentioned distance is 0.5 μm or less, the possibility of the above-mentioned short circuit caused by only one dust or the like increases.
On the other hand, if it is separated from the actual active by several tens μm or more, a trench having a side of several tens μm or more must be formed. When a large-sized trench is formed, a phenomenon called dishing occurs in which only an oxide film in a wide trench is quickly polished by CMP. When dishing occurs, the thickness of the oxide film is reduced only in the wide trench portion, which affects flatness and the like.

FIG. 5 is a view for explaining this pattern. In this figure, the depth of the formed trench is set to 4000 °, and how much dishing occurs when the width of the trench is changed is shown.
As shown in FIG. 5, up to around 100 μm, dishing sharply increases even if the width of the trench is slightly increased. In general, the variation in polishing by CMP polishing is about 500 mm, and the variation in the thickness of oxide film removal when removing the PAD oxide film is about 300 mm, depending on the CMP apparatus and processing time. In other words, if the dishing depth is at most 800 °, the buried oxide film can be left in a portion higher than the semiconductor substrate surface even in the portion where the oxide film has been cut most due to the variation. For this reason, by setting the interval between the actives to 10 μm or less, it is possible to prevent the buried oxide film from becoming lower than the substrate surface due to deep dishing.

FIG. 6 is a top view of a preferred arrangement example of dummy actives arranged based on the rules described above. The hatched area in the figure is a dummy active area, and the other area is an element isolation area formed by a trench.
In this example, the active areas of the hatched square dummy are formed at 1 μm on each side, have a size large enough not to cause the problem at the time of exposure as described above, and at the time of polishing the oxide film. It is a width that does not cause problems. At this time, the width of the trench is 0.5 μm. In such an arrangement, the shape of the dummy active can be formed in a square, so that the degree of freedom in arranging the dummy active is improved, and appropriate arrangement can be made at necessary portions. In such an arrangement, the active density with respect to the area is (1 * 1) / (1.5 * 1.5), which is about 44%. Since the actual active density of a memory cell used in a DRAM has a value of about 40 to 50%, a dummy pattern as shown in FIG. Although a square dummy pattern has been described as an actual example, the effects of the present application can be obtained by forming a dummy active such as a line pattern based on the above rules.
According to the present invention, the polishing process is made uniform, and a dummy active without giving a parasitic capacitance to a gate wiring or the like can be formed.

FIG. 4 is a process chart showing the steps of the first embodiment of the present invention. FIG. 1 is a top view showing a first embodiment of the present invention. FIG. 4 is a view showing a state of deposition of an oxide film of the present invention. FIG. 6 is a diagram showing a second embodiment of the present invention. The figure which shows the relationship between the width | variety of a trench, and the depth of dishing. FIG. 4 is a layout view of dummy actives according to the present invention.

Explanation of reference numerals

1 ... Silicon substrate
5 ... Trench
6 ... oxide film
7 ... Dummy active

Claims (8)

A gate electrode layer formed on a semiconductor substrate, an element isolation region formed by a trench, and a dummy active region, wherein a distance between the dummy active region and the gate electrode layer is 0.5 μm or more A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein a distance between the dummy active region and an active region where an element is formed is 10 μm or less. 3. The semiconductor device according to claim 1, wherein the dummy active region is formed in a substantially rectangular shape, and a dimension of a short side of the rectangle is 1 μm or less. 4. The semiconductor device according to claim 1, wherein the dimension of the short side is 0.5 μm or more. The semiconductor device further includes an active region in which an element is formed, and a distance between the dummy active region and the active region in which the element is formed is 0.5 μm or more. 6. The semiconductor device according to claim 5, wherein a distance between the dummy active region and an active region where an element is formed is 10 μm or less. 7. The semiconductor device according to claim 5, wherein the dummy active region is formed in a substantially rectangular shape, and a dimension of a short side of the rectangle is 1 μm or less. 8. The semiconductor device according to claim 5, wherein the dimension of the short side is 0.5 μm or more.

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