JP2004153140A - Semiconductor device and its fabricating method - Google Patents

Semiconductor device and its fabricating method Download PDF

Info

Publication number
JP2004153140A
JP2004153140A JP2002318352A JP2002318352A JP2004153140A JP 2004153140 A JP2004153140 A JP 2004153140A JP 2002318352 A JP2002318352 A JP 2002318352A JP 2002318352 A JP2002318352 A JP 2002318352A JP 2004153140 A JP2004153140 A JP 2004153140A
Authority
JP
Japan
Prior art keywords
trench
forming
region
semiconductor substrate
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002318352A
Other languages
Japanese (ja)
Other versions
JP4288925B2 (en
Inventor
Naoto Fujishima
直人 藤島
Masaaki Ogino
正明 荻野
Hideaki Teranishi
秀明 寺西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2002318352A priority Critical patent/JP4288925B2/en
Publication of JP2004153140A publication Critical patent/JP2004153140A/en
Application granted granted Critical
Publication of JP4288925B2 publication Critical patent/JP4288925B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its fabricating method in which high integration is improved and a warpage of wafer is reduced by shortening a distance between a gate and a drain and reducing the width of a wide isolation region. <P>SOLUTION: A trench is formed on a (p) substrate 1, (n) epitaxial layers are formed within the trench and heat treatment is applied in a reduction atmosphere, such that impurities in the (n) epitaxial layers are diffused over the (p) substrate to form (n) drift regions 2. Then, a silicon in the opening of the trench is contacted by heat treatment to internally form a void 3. By forming the void 3, the inside of the trench is made into low dielectric constant, such that the distance between the gate and the drain is shortened to reduce the warpage of the wafer. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は、電源、モータおよび自動車などに適用され、横型高耐圧パワーデバイスを内蔵集積したパワーＩＣ（集積回路）などの半導体装置に関し、特に、トレンチ溝を充填する絶縁膜に空孔を形成する高耐圧横型ＭＯＳデバイスに関する。
【０００２】
【従来の技術】
パワーＩＣに集積される従来の横型パワーＭＯＳＦＥＴの構造としては、トレンチを形成し、このトレンチに沿って長いドリフト領域を形成し耐圧を確保する構造が報告されている（例えば、特許文献１など参照）。
図２７は、従来の横型パワーＭＯＳＦＥＴの要部断面図である。ｐ基板８１にトレンチ９５を形成し、このトレンチ９５内壁にリンを斜めイオン注入をする。その後熱酸化してトレンチ９５内に酸化膜８３を充填し、且つ、ｎドリフト領域８２を形成する。酸化膜８３上にＬＯＣＯＳ酸化膜８４を形成し、ｐ基板８１の表面層にｐウエル領域８５とｎウエル領域８６を形成する。ｐウエル領域８５の表面層にｎソース領域８９とｐコンタクト領域９１を形成し、ｎドリフト領域８２の表面層とｎウエル領域８６の表面層にｎドレイン領域９０を形成する。ｎソース領域８９とｎドリフト層に挟まれたｐウエル領域８５上にゲート酸化膜８７を介してゲート電極８８を形成し、ｎソース領域８９上とｐコンタクト領域９１上にソース電極９２を形成し、ｎドレイン領域９０上にドレイン電極９３を形成する。図中の９４は層間絶縁膜である。
【０００３】
集積回路として他の低耐圧制御用素子と同一半導体基板に形成することから、このソース電極９２、ゲート電極８８、ドレイン電極９３の各電極は、ｐ基板１の表面に設けられている。また、高耐圧化を行うため、電圧を支持するゲート・ドレイン間のドリフト形成領域に前記したようにトレンチ９５を形成し、トレンチ周囲に斜めイオン注入法でｎドリフト領域８２を形成し、そのトレンチ９５を酸化膜８３で充填することで、短い距離でもｐ基板１内で十分な電界緩和を図っている。
６０〜７００Ｖの耐圧クラスに応じてトレンチの形状が異なり、６０Ｖではトレンチ幅３μｍ、深さ３μｍ程度である。また、７００Ｖではトレンチ幅２０μｍ、深さ２０μｍが必要となる。トレンチに酸化膜を充填するために、酸化膜の最大臨界電界強度が、半導体基板であるシリコンより３０倍程度高いため、ゲート・ドレイン間隔を小さくすることができ（７００Ｖの耐圧クラスでは約３分の１）、高集積化を可能とした。
【０００４】
また、近年、ＬＳＩの高集積化を図るために、素子分離をトレンチを形成し、このトレンチに絶縁膜を充填する誘電体分離構造が多用されている。このように素子分離を溝分離（トレンチ分離）で行う構造では、充填する絶縁膜と、半導体基板との熱膨張係数差で、トレンチ部に応力ストレスが発生して分離特性を悪化させたり、また、充填絶縁膜の誘電率が高いために、寄生容量が大きくなりゲート配線遅延を生じるなど不都合を生じる。これらを解決するために、トレンチ内の充填絶縁膜に空孔を形成し、トレンチ内の充填絶縁膜量を減らして、絶縁膜と半導体基板との熱膨張係数差による応力ストレスを減じて、半導体基板に結晶欠陥が入ることを防止することや、トレンチ内の充填絶縁膜の誘電率を低下させてゲート配線遅延を防止することなどが開示されている（例えば、特許文献２など参照）。
【０００５】
また、別の文献には、フラッシュメモリの集積回路を構成するＭＯＳデバイスのフローティングゲート配線で挟まれたトレンチ分離酸化膜の溝を埋める酸化膜に空孔を形成することで、トレンチ分離溝直下に形成されるソース領域に結晶欠陥が導入されることを防止することが開示されている（例えば、特許文献３など参照）。
これらの特許文献２、３では、溝分離構造の充填絶縁膜に空孔を形成するものであり、その目的は、結晶欠陥の発生を防止することや充填絶縁膜の平均的な誘電率を低下させて、ゲート配線遅延を防止することなどである。
【０００６】
また、前記の空孔を形成する方法として、ＳＩＭＯＸ（Ｓｉｌｉｃｏｎ Ｉｍｐｌａｎｔａｔｉｏｎ Ｏｘｉｄｅ）プロセスで形成した酸化膜の近傍にＨｅイオンを打ち込み、この打ち込みで形成されたダメージ箇所に隣接する酸化膜を空孔に変換することが報告されている（例えば、非特許文献１ ２５ｐ−Ｇ−４）。
【０００７】
【特許文献１】
米国特許第５８４４２７５号明細書
【特許文献２】
特開２０００−１８３１４９号公報
【特許文献３】
特開２００２−７６２９９号公報
【０００８】
【非特許文献１】
第６３回応用物理学関係連合講演会 講演予稿集、２００２．９
【０００９】
【発明が解決しようとする課題】
トレンチ内に絶縁膜を充填した場合、半導体基板（ここではシリコン）の熱膨張係数は酸化膜に比べ７倍と大きく、８００〜１０００℃での酸化膜充填工程後、充填した酸化膜とシリコン基板の熱膨張係数差により、ウエハの反りが大きく、内部応力で前記した結晶欠陥の発生の他に、ウエハの反り大きくなり後工程でのウエハの装置ステージへの吸着が困難になるなどの問題が生じる。
このウエハの反り量は、酸化膜を充填するトレンチのウエハ面内の面積比率に依存するが、例えば、トレンチ面内比率が６０％の場合、６インチ径ウエハの場合には、その反り量は５００μｍにもなる。
【００１０】
また、ドリフト領域をトレンチに沿って形成する構造では、トレンチを充填する酸化膜の最大臨界電界強度が、半導体基板であるシリコンより３０倍程度く、また、比誘電率がシリコンと比べて小さいため、耐圧をトレンチ内の酸化膜に保持させることができて、ゲート・ドレイン間隔を小さくすることができ（７００Ｖの耐圧クラスでは約３分の１）、高集積化できる。
しかし、一層の高集積化を図るためには、高耐圧横型ＭＯＳデバイスのゲート・ドレイン間隔をさらに短縮する必要がある。
また、前記の空孔を有する分離構造は、空孔を１個有する比較的分離幅が狭い場合であるが、幅の広い溝分離構造の場合でもその分離幅を低減して、高集積化を図ることが求められている。
【００１１】
この発明の目的は、ウエハの反り量の低減と、ゲート・ドレイン間の距離の短縮および幅の広い分離領域の分離幅の低減による高集積化とを図ることができる半導体装置とその製造方法を提供することにある。
【００１２】
【課題を解決するための手段】
前記の目的を達成するために、
（１）半導体基板の表面層に形成されるソース領域と、該ソース領域と離して半導体基板の表面層に形成されるドレイン領域と、該ドレイン領域と前記ソース領域に挟まれた前記半導体基板に形成され上部が絶縁膜で分離された空孔と、前記ドレイン領域と前記ソース領域の間の前記空孔に沿う前記半導体基板に形成され、前記ドレイン領域と接して形成されるドリフト領域と、前記ソース領域と前記ドリフト領域に挟まれた前記半導体基板上にゲート絶縁膜を介して形成されるゲート電極と、前記ソース領域上に形成されるソース電極と、前記ドレイン領域上に形成されるドレイン電極と、を有する構成とする。
（２）半導体基板の表面層に形成されるソース領域と、該ソース領域と離して半導体基板の表面層に形成されるドレイン領域と、該ドレイン領域と前記ソース領域に挟まれた前記半導体基板に形成されたトレンチと、該トレンチに充填された絶縁膜と、該絶縁膜内部に形成された空孔と、前記ドレイン領域と前記ソース領域の間の前記トレンチに沿う前記半導体基板に形成され、前記ドレイン領域と接して形成されるドリフト領域と、前記ソース領域上に形成されるソース電極と、前記ドレイン領域上に形成されるドレイン電極と、を有する構成とする。
（３）前記空孔が、半導体基板の表面と平行な方向に複数個形成されるとよい。（４）前記空孔の平面形状が格子状であるとよい。
（５）誘電体分離領域を有する半導体装置において、該誘電体分離領域が、半導体基板に形成されたトレンチと、該トレンチ内に形成された絶縁膜と、該絶縁膜内部に半導体基板の表面と平行な方向に複数個形成された空孔とを有する構成とする。
（６）誘電体分離領域を有する半導体装置において、該誘電体分離領域が、半導体基板に形成されたトレンチと、該トレンチ内に形成された絶縁膜と該絶縁膜内部に平面形状が格子状の空孔とを有する構成とする。
（７）（１）の半導体装置の製造方法において、第１導電形半導体基板にトレンチを形成する工程と、該トレンチと前記半導体基板表面に第２導電形不純物をドープしたエピタキシャル層を形成する工程と、還元雰囲気で熱処理し、トレンチ開口部を閉塞し、前記半導体基板に第２導電形ドリフト領域と、該ドリフト領域で囲まれた空孔とを同時に形成する工程と、前記空孔の上部の前記ドリフト領域を絶縁化し、該絶縁膜で前記ドリフト領域の上部を分離する工程と、を有する製造方法とする。
（８）（１）の半導体装置の製造方法において、第１導電形半導体基板にトレンチを形成する工程と、該トレンチと前記半導体基板表面に第２導電形不純物をイオン注入する工程と、還元雰囲気で熱処理し、トレンチ開口部を閉塞し、前記半導体基板に第２導電形ドリフト領域と、該ドリフト領域で囲まれた空孔とを同時に形成する工程と、前記空孔の上部の前記ドリフト領域を絶縁化し、該絶縁膜で前記ドリフト領域の上部を分離する工程と、を有する製造方法とする。
（９）（２）〜（４）のいずれかの半導体装置の製造方法において、半導体基板にトレンチを形成する工程と、該トレンチに沿うようにドリフト領域を形成する工程と、前記トレンチ内に熱酸化膜を形成し、トレンチ開口部を該熱酸化膜で閉塞し、該熱酸化膜の内部に空孔を形成する工程と、を有する製造方法とする。
（１０）（２）〜（４）のいずれかの半導体装置の製造方法において、半導体基板にトレンチを形成する工程と、該トレンチに沿うようにドリフト領域を形成する工程と、前記トレンチ内に化学気相成長法で絶縁膜を形成し、トレンチ開口部を該絶縁膜で閉塞し、該熱絶縁膜の内部に空孔を形成する工程と、を有する製造方法とする。
（１１）（２）の半導体装置の製造方法において、半導体基板にトレンチを形成する工程と、還元雰囲気で熱処理し、トレンチ開口部を狭める工程と、酸化してトレンチ内に熱酸化膜を形成し、トレンチ開口部を該熱酸化膜で閉塞し、空孔を形成する工程と、を有する製造方法とする。
（１２）半導体基板にトレンチを形成し複数の半導体柱を形成する工程と、熱酸化により、前記半導体柱を酸化するとともに前記トレンチ内に熱酸化膜を形成する工程と、前記トレンチ内に化学気相成長法で絶縁膜を形成し前記トレンチの開口部を該絶縁で閉塞し、該絶縁膜の内部に空孔を形成する工程と、を有する製造方法とする。
（１３）半導体基板にトレンチを形成し複数の半導体柱を形成する工程と、熱酸化により、前記半導体柱を酸化するとともに前記トレンチ内に熱酸化膜を形成し、前記複数個のトレンチの開口部を熱酸化膜で閉塞し、該酸化膜の内部に空孔を形成する工程と、を有する製造方法とする。
（１４）（１２）および（１３）の製造方法において、半導体柱を形成する工程の後に、還元雰囲気で熱処理しトレンチ開口部を狭める工程を有する製造方法とする。
（１５）半導体基板にトレンチを形成する工程と、還元雰囲気で熱処理しトレンチ開口部を狭める工程と、熱酸化してトレンチ内に熱酸化膜を形成し、トレンチ開口部を該熱酸化膜で閉塞し、該熱酸化膜の内部に空孔を形成する工程と、を有する製造方法とする。
（１６）（７）、（８）、（１４）および（１５）の製造方法において、前記還元雰囲気が、アルゴンガス、水素ガスもしくはアルゴンガスに水素を混合したガスのいずれか一つであることよい。
〔作用〕
この構造では、空孔（空気である場合）の比誘電率（＝１）は酸化膜の比誘電率（＝４）より小さいため、Ｇａｕｓｓの法則より印加された電位はこの比の空孔で支持されるので従来の酸化膜でトレンチを充填する場合に比べ、耐圧を確保しつつ、トレンチ幅（空孔幅）を３〜４分の１に縮小できるので、素子ピッチを縮小できてコスト的に有利となる。
【００１３】
図２８に本発明品の電位分布図、図２９に従来品の電位分布図を示す。ソース・ドレイン間に７０Ｖ印加した場合であり、本発明品は空孔部に等電位線を密集させることができて、ゲートとドレイン間の距離を従来品より短縮できることが分かる。
また、従来はトレンチを全て酸化膜で充填していたので、シリコンと熱膨張率の大きく異なる酸化膜の体積が大きかったが、本発明構造では、トレンチ幅が狭くなることに加え、トレンチ内部が空孔（空気や不活性ガスが充満している）となるので製造途中でのウエハの反りを大きくすることは無くなる。従って、トレンチ形成面積比率の大きい大電流（低オン抵抗）の半導体装置への適用が可能となる。また、従来構造に対し、デバイスピッチが縮小するため、同一オン抵抗でのチップサイズ縮小、また同一チップサイズでの低オン抵抗化が可能となる。
【００１４】
【発明の実施の形態】
図１は、この発明の第１実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。同図（ａ）は、同図（ｂ）の断面図のＹ−Ｙ面から見た平面図である。以下の説明において、ｐ基板を用いた場合を示しているが、ｎ基板を用いて、各領域の導電形を逆としてもよいし、基板のみをｎ基板としてもよい。また、ｎはｎ形導電形を表し、ｐはｐ形導電形を表す。
ｐ基板１（シリコン基板）に図示しないストライプ状のトレンチを形成し、このトレンチ内で、空孔３に沿うようにｎドリフト領域２（ｎオフセットドレイン領域ともいう）を形成する。この空孔１の上部に酸化膜４を形成し、ｐ基板１の表面層にｐウエル領域５とｎウエル領域６を形成する。ｐウエル領域５の表面層にｎソース領域９とｐコンタクト領域１１を形成し、ｎウエル領域６の表面層にｎドレイン領域１０を形成する。ｎソース領域９とｎドリフト領域２に挟まれたｐウエル領域５上にゲート酸化膜７を介してゲート電極８を形成し、その上に層間絶縁膜１４を形成する。ｎソース領域９上とｐコンタクト領域１１上にソース電極１２を形成し、ｎドレイン領域１０上にドレイン電極１３を形成する。尚、前記ｎウエル領域６はｎドレイン領域１０を補完する領域であり、形成しなくても構わない。
【００１５】
この構造では、前記したように、空孔３（空気である場合）の比誘電率（＝１）は酸化膜の比誘電率（＝４）より小さいため、Ｇａｕｓｓの法則より印加された電位は、この比で空孔側で支持されるので従来の酸化膜でトレンチを充填した場合に比べ、トレンチ幅（空孔幅）を３〜４分の１に縮小できる。そのため、素子ピッチを縮小できて低コスト化を図ることができる。
７０Ｖの耐圧クラスの高耐圧横型ＭＯＳＦＥＴを製作したところ、従来、オン抵抗が７０ｍΩｍｍ２ であったものが、５０ｍΩｍｍ２ に低減できた。これは、空孔を形成することで、耐圧を維持しながらゲート・ドレイン間の距離を短縮することで、ＭＯＳＦＥＴのセルの集積密度を高める（高集積化する）ことができたためである。
【００１６】
また、従来はトレンチをすべて酸化膜で充填していたので、シリコンと熱膨張率の大きく異なる酸化膜の体積が大きかったが、この構造では、トレンチ幅が狭くなることに加え、トレンチ内部が空孔となり、酸化膜の体積を減少させることができるため、ウェハの反り量を大幅に減少させることができる。
具体的には、工程終了時のウェハ反り量は、従来５００μｍもあったものが本構造では２０μｍと小さくできた。そのため、製造工程中でのウエハの反りに起因するトラブルが防止できるようになった。
空孔の形成とウエハの反り量の低減により、従来よりトレンチ形成面積比率を大きくできて、高耐圧で大電流（低オン抵抗）の半導体装置を製作できるようになった。
【００１７】
図２から図４は、この発明の第２実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。これは図１の半導体装置の製造方法である。
比抵抗１５Ωｃｍのｐ基板１（シリコン基板）に、開口部の幅１μｍ、深さ３μｍのトレンチ１５を形成し、リン原子の不純物濃度が１×１０１７ｃｍ−３で厚さ１μｍのｎエピタキシャル層１６を成長させる（図２）。
つぎに、Ａｒガス９６％、Ｈ２ ガス４％の還元雰囲気（水素雰囲気）で４０Ｔｏｒｒ（４０×１３３Ｐａ）の減圧で１１００℃１０分アニールすることで、表面のシリコンを接触させ、内部に空孔３（幅１μｍ、空孔上部と基板表面の間のシリコン幅０．５μｍ）を形成する。このとき、ｐ基板１表面とトレンチ１５内部に形成されたｎエピタキシャル層１６からリンが再拡散し、表面濃度５×１０１６ｃｍ−３、深さ３μｍのｎ形拡散層１７が形成される（図３）。
【００１８】
つぎに、チャネル形成部に表面濃度が５×１０１６ｃｍ−３で、深さ３μｍのｐ形拡散層であるｐウェル領域５を形成し、ドレイン形成部に表面濃度が５×１０１６ｃｍ−３で、深さ３μｍのｎ形拡散層であるｎウェル領域６を形成する。この場合、空孔３を深い箇所に形成し、ｐ基板１の表面層に形成されたｎ拡散層１７を空孔３に達しないように除去してからｐウエル領域５、ｎウエル領域６を形成してもよい。続いてｎソース、ゲート、ドレイン各領域形成部に図示しない窒化膜を形成し、熱酸化を行うことで表面のゲート―ドレイン間の窒化膜が存在しない部分に厚さ１．０μｍの酸化膜４（ＬＯＣＯＳ酸化膜）を形成する。この時、空孔３上部と基板表面の間のシリコンは完全に酸化され酸化膜となる。この後、窒化膜を除去し、厚さ０．０２５μｍのゲート酸化膜７を形成し、このゲート酸化膜７上にゲート電極８を形成し、ソース形成部にｎ＋ 拡散を行ってｎソース領域９を形成し、ｐウェルコンタクト用のｐ＋ 拡散層（ｐコンタクト領域１１）とｎウェル領域６の表面層にｎドレイン領域１０を形成する。ゲート電極８上に層間絶縁膜１４を形成し、ｎソース領域９上とｐコンタクト領域１１上にソース電極１２を形成し、ｎドレイン領域１０上にドレイン電極１３を形成する（図４）。尚、前記の還元雰囲気は、Ａｒガスのみ、Ｈ２ ガスのみであっても構わない。
【００１９】
図５、図６は、この発明の第３実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。図１の半導体装置の製造方法で第２実施例とは違う製造方法である。
第２実施例と異なるのは、トレンチ形成後にエピタキシャル成長をする代わりに、トレンチ１５の側壁および底面にｎ形不純物をイオン注入してイオン注入層１８を形成した点である。
トレンチ１５内にイオン注入層１８を形成する（図５）。つぎに、図３と同様に熱処理して、空孔３とｎ拡散層１９を形成する（図６）。その後の工程は図４と同じである。
【００２０】
具体的には、８０ｋｅＶでリンドーズ量１×１０１３ｃｍ−２のイオン注入（ドープ）を行いイオン注入層１８を形成し、その後、１１５０℃で２００分の熱処理（ドライブ）を行い表面濃度５×１０１６ｃｍ−３で、深さ３μｍのｎ拡散層１９を形成する。このｎ拡散層１９が空孔３の周囲に形成されるｎドリフト領域２となる。
前記のトレンチ１５の形成にはマスクとして酸化膜を使用するがそれを除去する前にイオン注入を行えば、トレンチ１５の側壁と底面のみにｎ拡散層１９を形成できる。こうすることで、図３のように、ｐ基板１の表面層に形成されるｎ拡散層１７の除去工程が不要となる。
【００２１】
図７は、この発明の第４実施例の半導体装置の要部断面図である。図１との違いは、空孔２２が酸化膜２１で覆われている点である。この酸化膜２１がｎドリフト領域２０と空孔２２の間に介在することで、比誘電率がシリコンから空孔に向かって緩やかに小さくなるため、図１と比べると、電位分布の詰まりが緩くなり、電界集中が起こり難くなる。前記した図２７が本発明品（７０Ｖ耐圧品）に７０Ｖ印加した場合の等電位線の様子を示す図である。また、第１実施例と同様にゲート・ドレイン間の間隔を短縮できて、高集積化を図ることができる。その結果、低オン抵抗の高耐圧横型ＭＯＳＦＥＴを製作できる。また、空孔を形成するために、ウエハの反り量も第１実施例と同等にできる。尚、図中のＤ２は空孔長、Ｗ２は空孔幅、Ｗｏｘ２ は酸化膜厚さである。
【００２２】
図８から図１０は、この発明の第５実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図ある。これは図７の半導体装置の製造方法であり、ここでは、第２実施例と異なるのは、空孔の上部に空隙を形成する点である。
図２と同様に、比抵抗１５Ωｃｍのｐ基板１に、開口部の幅１μｍ、深さ３μｍの図示しないトレンチを形成し、リン原子の不純物濃度が１×１０１７ｃｍ−３で厚さ１μｍのｎ形エピタキシャル層を成長させる。
つぎに、Ａｒガス９６％、Ｈ２ ガス４％の還元雰囲気（水素雰囲気）で４０Ｔｏｒｒの減圧で１１００℃１０分アニールすることで、表面のシリコンを互いに近接させ、上部が隙間２６を有する空隙２５（幅１μｍ、空孔上部と基板表面の間のシリコン幅０．５μｍ）を形成する。このとき、ｐ基板１の表面とトレンチ内部に形成されたｎエピタキシャル層からリンが再拡散し、表面濃度５×１０１６ｃｍ−３、深さ３μｍのｎ形拡散層２４が形成される（図８）。
【００２３】
つぎに、熱酸化によりシリコン基板表面とトレンチ表面を酸化し、最初はｐ基板１表面とトレンチ表面に酸化膜が成長し、やがてトレンチの入り口で酸化膜が接触し、表面とトレンチ側壁に酸化膜２１を有し、トレンチ中央に空孔２２が形成される。このトレンチ内部の酸化膜厚は０．５μｍで、空孔幅は０．５μｍである（図９）。
つぎに、ゲート、ソースおよびドレイン部分の酸化膜２１をマスクを用いて除去する。その後、チャネル形成部に表面濃度が５×１０１６ｃｍ−３で、深さ３μｍのｐ形拡散層であるｐウェル領域５を形成し、ドレイン形成部に表面濃度が５×１０１６ｃｍ−３で、深さ３μｍのｎ形拡散層であるｎウェル領域６を形成する。続いてソース、ゲート、ドレイン各領域形成部に図示しない窒化膜を形成し、熱酸化を行うことで表面のゲート―ドレイン間の窒化膜が存在しない部分に厚さ１．０μｍの酸化膜２３を形成する。この時、空孔上部と基板表面の間のシリコンは完全に酸化され酸化膜２３となる。この後、窒化膜を除去し、厚さ０．０２５μｍのゲート酸化膜７を形成し、このゲート酸化膜７上にゲート電極８を形成し、ソース形成部にｎ＋ 拡散を行ってｎソース領域９を形成し、ｐウェルコンタクト用のｐ＋ 拡散層であるｐコンタクト領域１１を形成し、ｎウェル領域６の表面層にｎドレイン領域１０を形成する。ゲート電極８上に層間絶縁膜１４を形成し、ｎソース領域９上とｐコンタクト領域１１上にソース電極１２を形成し、ｎドレイン領域１０上にドレイン電極１３を形成する。尚、前記ｎウエル領域６はｎドレイン領域１０を補完する領域であり、形成しなくても構わない（図１０）。
【００２４】
尚、第５実施例のトレンチ酸化において、熱酸化による体積膨張でトレンチ上部の酸化膜が接続するが、接合面は物理的接合であり、後工程のウェットエッチングにより、容易に空孔２２への経路が生じ、薬液の空孔への出入りが懸念される。
これを防止するために高温での短時間アニ―ル（１３００℃、１０秒）が考えられるが、さらに好まれる方法として、図１１に示すように、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）酸化膜２７を酸化膜２１上に堆積することで、空孔２２への経路上に良質な酸化膜を形成することで空孔２２に通じる隙間２６の形成を防止できる。
【００２５】
この実施例では、空隙２５を還元雰囲気のアニールによって形成したが、トレンチを形成する際にトレンチの開口部より底部の方が幅が広いトレンチを形成することでも構わない。この場合還元雰囲気でのアニールは行わなくてもよく、窒素雰囲気のアニールなどでよい。また、以下の実施例において、トレンチを形成するものは同様のことが言える。
図１２と図１３は、この発明の第６実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。これは、第５実施例をさらに発展させたものである。
【００２６】
還元雰囲気でのアニール後、チャネル形成部に表面濃度が５×１０１６ｃｍ−３で、深さ３μｍのｐ形拡散層であるｐウェル領域５を形成し、ドレイン形成部に表面濃度が５×１０１６ｃｍ−３で、深さ３μｍのｎ形拡散層であるｎウェル領域６を形成し、ソース、ゲート、ドレイン各領域形成部に窒化膜２９を形成する（図１２）。
つぎに、熱酸化を行うことで表面のゲート―ドレイン間の窒化膜２８が存在しない部分に厚さ１．０μｍの酸化膜２９を形成する。トレンチ上部とトレンチ側壁は酸化され、特にトレンチ上部は完全に酸化膜２８が接続される。この後、窒化膜２８を除去する（図１３）。
【００２７】
つぎに、窒化膜２８を除去し、図１０の工程のように、厚さ０．０２５μｍのゲート酸化膜７を形成し、このゲート酸化膜７上にゲート電極８を形成し、ソース形成部にｎ＋ 拡散を行ってｎソース領域９を形成し、ｐウェルコンタクト用のｐ＋ 拡散層であるｐコンタクト領域１１を形成し、ｎウェル領域６の表面層にｎドレイン領域１０を形成する。ゲート電極８上に層間絶縁膜１４を形成し、ｎソース領域９上とｐコンタクト領域１１上にソース電極１２を形成し、ｎドレイン領域１０上にドレイン電極１３を形成する。この構造では、図示しないＣＭＯＳ回路素子のＬＯＣＯＳ酸化膜を形成するときにマスクとして用いる窒化膜と同一の窒化膜２８を用いて、前記した図１０の酸化膜２３と酸化膜２２とを同時に形成できる利点がある。
【００２８】
前記した各実施例の半導体装置では、素子耐圧（ＢＶｄｓ）が７０Ｖの例について述べたが、同様の構造が１２０Ｖ耐圧さらには７００Ｖ耐圧の場合にも成り立ち、スケーリングにより表１に示すパラメータ（諸元）となる。尚、表中のＤ１、Ｗ１は図１に記載したＤ１、Ｗ１であり、Ｄ２、Ｗ２、Ｗｏｘ２は図７に記載したＤ２、Ｗ２、Ｗｏｘ２である。
【００２９】
【表１】

Figure 2004153140
図１４は、この発明の第７実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。同図（ａ）は、同図（ｂ）のＹ−Ｙ面から見た平面図である。
図１との違いは、トレンチ幅３０が広い場合で、空孔３３の数が複数個となっている点である。この図では、空孔３３を３個有する場合を示したが、素子耐圧が高い場合はトレンチ幅３０が広くなり空孔３３の数を増加させ、低い場合は減少させる。つまり、素子耐圧により空孔３３の数を選定するとよい。
【００３０】
図１５から図１７は、この発明の第８実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。これは複数個の空孔を形成するために、複数個のトレンチを形成する工程が第２実施例と異なる点である。
比抵抗１５Ωｃｍのｐ形シリコン基板に幅１μｍ、深さ２０μｍのトレンチ３４を等ピッチで３個形成する。つまり、トレンチ間にはシリコン柱３５（半導体柱）が２個形成される。また、トレンチ間隔は０．５μｍとする。つぎに減圧ＣＶＤ法によりリンを含むポリシリコン３６を堆積し、表面濃度５×１０１６ｃｍ−３、接合深さ（Ｘｊ）が３μｍのｎ形不純物層ができるように１１００℃以上の高温でドライブする。ここでポリシリコン３６の膜厚はＸｊ＝３μｍとなるような膜厚・ドライブ（熱処理）条件ならどれでもよい（図１５）。
【００３１】
ドライブした後、還元雰囲気（前記した水素雰囲気）で４０Ｔｏｒｒの減圧で１１００℃３分アニールし、トレンチ開口部の幅がトレンチ底部の幅よりも狭くなる形状に変化させる。例えば、トレンチ開口部ではトレンチ幅が０．５μｍ、トレンチ間の距離（トレンチ間シリコン柱３５）が１μｍとなる。このドライブでｎドリフト領域３９となるｎ領域３７が形成される（図１６）。
つぎに熱酸化によりシリコン柱３５を１０００℃で酸化する。この酸化によりシリコン柱３５の体積が増加し、トレンチ３４内部に空孔４０を残した状態でトレンチ開口部が柱同士が酸化膜３８となった状態で連結される（図１７）。図ではトレンチ３４が３つ上部で酸化膜として塞がれた状態となることで幅の広いトレンチ内部を空孔４０を有する酸化膜３８で充填した構造となっているが、トレンチ３４の数は任意に変えることができ、素子耐圧（ＢＶｄｓ）によって最終的に求められるドリフト長が要求を満たすように調整する。
【００３２】
つぎに、図４の工程のように、チャネル形成部に表面濃度が５×１０１６ｃｍ−３で、深さ３μｍのｐ形拡散層であるｐウェル領域５を形成し、ドレイン形成部に表面濃度が５×１０１６ｃｍ−３で、深さ３μｍのｎ形拡散層であるｎウェル領域６を形成する。その後、図示しない窒化膜を除去し、厚さ０．０２５μｍのゲート酸化膜７を形成し、このゲート酸化膜７上にゲート電極８を形成し、ソース形成部にｎ＋ 拡散を行ってｎソース領域９を形成し、ｎウェル領域６の表面層にｎドレイン領域１０を形成する。ゲート電極８上に層間絶縁膜１４を形成し、ｎソース領域９上とｐコンタクト領域１１上にソース電極１２を形成し、ｎドレイン領域１０上にドレイン電極１３を形成する。
【００３３】
尚、図１８のように、ストライプ状のシリコン柱を分断して、多数のシリコン柱４１としても構わない。この場合は、空孔４３はハッチングで示すように繋がり、空孔４３の占有率を大きくできる。
図１９は、この発明の第９実施例の半導体装置の要部断面図である。これは、ＳＯＩ基板５０に誘電体分離の分離領域５３を形成し、この分離領域５３に空孔５６を形成した場合である。この場合も分離領域幅が短縮できて、高集積化に有効である。この空孔を有する分離領域の形成方法は、前記のトレンチ内に空孔を形成する場合と同じである。
【００３４】
図２０から図２２は、この発明の第１０実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。これは図７や図１４の半導体装置についての製造方法であり、特に、空孔を形成した後、デバイスを形成するために必要となる表面に形成された絶縁膜の平坦化ついて説明している。ここでは、図１４のように複数個の空孔を有する場合について説明している。勿論、これは図１９の誘電体分離構造にも適用できる。
ｐ基板１を表面３０ｎｍ酸化し、その後、窒化膜を１００ｎｍ堆積し、さらにレジストを塗布後、横型高耐圧ＭＯＳＦＥＴのｎドリフト領域６０の形成予定領域を露光し、窒化膜、酸化膜を除去する。その後、レジスト灰化しレジストを除去した後、シリコンエッチングを行い、幅３μｍ、深さ２０μｍのトレンチを形成する。つぎに、トレンチ内壁にリンドープポリシリコンを成膜し、ドライブを行いｐ基板１の深さ方法に、拡散深さ（ｐｎ接合の深さＸｊ）が６μｍ程度になるようにドライブさせる。つぎに、トレンチ内のポリシリコンを酸化・除去し、熱酸化により、トレンチ内にあるトレンチ間のシリコン柱を熱酸化するとともにトレンチ内に熱酸化膜６１を形成する。熱酸化する前に還元雰囲気にてアニールしてもよい。熱酸化後のトレンチの幅は２μｍ程度であるため、熱ＣＶＤ法などで熱ＣＶＤ酸化膜６２を成膜する。この熱ＣＶＤ酸化膜６２の成膜では、トレンチ内が全て酸化膜で埋まることはなく、トレンチ内部には空孔６３が形成される。しかし、トレンチによる凹凸の影響を受け、熱ＣＶＤ酸化膜６２の上端は凹凸のある形状となる（図２０）。
【００３５】
つぎに、凹凸のある熱ＣＶＤ酸化膜６２の表面をＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）法により研磨除去し平坦化する。このＣＭＰ法を用いることで、ストッパなしでも任意の研磨深さで酸化膜内を平坦化することができる（図２１）。
つぎに、ＣＭＰ法で平坦化された熱ＣＶＤ酸化膜６２の平坦な研磨面６４を基準としてウエットエッチングまたはドライエッチングによりシリコン面が露出するまで残りの熱ＣＶＤ酸化膜６２を除去し、内部に空孔６３を有する熱ＣＶＤ酸化膜６２が形成される（図２２）。
【００３６】
つぎに、図示しないｐウエル領域、ｎウエル領域を形成し、ゲート、ソース、ドレインの各領域と各電極を形成し、図１４のような半導体装置とする。
このように、ＣＭＰ法で平坦化することで、上部が確実に熱ＣＶＤ酸化膜で閉じた空孔を形成することができる。閉じた空孔とすることで、空孔内にレジストが入り込むことや空孔内の金属汚染やパーテクル汚染を防止できる。その結果、高信頼性の半導体装置を製造することができる。
図２３から図２６は、この発明の第１１実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。これは、空孔の形成を、トレンチを形成せずに、直接半導体基板内に形成する方法である。
【００３７】
ゲート電極７７の形成領域とドレイン電極７８の形成領域に挟まれたｐ基板１にｎドリフト領域となるｎ領域７０を形成する。つぎに、ＳＩＭＯＸプロセスでｎ領域７０の一部に酸化膜７１を形成する（図２３）。
つぎに、軽元素イオン（Ｈｅイオンなど）を前記酸化膜７１を貫通し、ｎ領域７０内にイオン注入し、前記酸化膜７１近傍にダメージ層７３を形成する（図２４）。
つぎに、還元雰囲気（ＡｒガスにＯ２ を混入したガス）で１３００℃以上の高温で熱処理することで、前記ダメージ層７３に隣接する前記酸化膜７１を空孔７４に変換し、ｎ領域７０内に空孔を形成する（図２５）。
【００３８】
その後、空孔７４の上部のｎ領域７０を酸化して酸化膜７６を形成し、ｎドリフト領域７５、ｐウエル領域、ｎウエル領域、ゲート電極７７、ｎソース領域、ｎドレイン領域、ソース電極、ドレイン電極７８などを形成する（図２６）。
この製造方法では、トレンチを形成することなく、空孔７４を半導体基板内に形成できるため、空孔７４内の汚染がなく、高信頼性の半導体装置を製造できる。
また、空孔７４が形成されているため、前記の実施例と同様に、ゲート・ドレイン間の距離を短縮できて、高集積化を図ることができる。また、ウエハの反り量も小さくできる。
【００３９】
【発明の効果】
この発明によれば、ドリフト領域がトレンチに沿って形成される高耐圧横型ＭＯＳデバイスのトレンチを充填する絶縁膜に空孔を形成することで、トレンチ内の誘電率を低下させ、ゲート・ドレイン間の距離を短縮することができて、高集積化を図ることができる。
また、トレンチを充填する絶縁膜に空孔を形成することで、ウエハの反り量を大幅に減少させることができる。
また、幅の広い誘電体分離構造の分離領域の絶縁膜に空孔を複数個形成することで、分離領域の幅を短くできて、高集積化を図ることができる。
【００４０】
また、空孔を塞ぐ絶縁膜をＣＭＰで平坦化することで、上部が確実に塞がれた空孔を形成することで、空孔内の汚染（レジストの入り込み、金属汚染、パーテクル汚染など）を防止し、半導体装置の信頼性を高めることができる。
【図面の簡単な説明】
【図１】この発明の第１実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図
【図２】この発明の第２実施例の半導体装置の要部製造工程断面図
【図３】図２に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図４】図３に続く、この発明の第２実施例の半導体装置の要部製造工程断面図
【図５】この発明の第３実施例の半導体装置の要部製造工程断面図
【図６】図５に続く、この発明の第３実施例の半導体装置の要部製造工程断面図
【図７】この発明の第４実施例の半導体装置の要部断面図
【図８】この発明の第５実施例の半導体装置の要部製造工程断面図
【図９】図８に続く、この発明の第５実施例の半導体装置の要部製造工程断面図
【図１０】図９に続く、この発明の第５実施例の半導体装置の要部製造工程断面図
【図１１】ＣＶＤ酸化膜を表面に被覆した図
【図１２】この発明の第６実施例の半導体装置の要部製造工程断面図
【図１３】図１２に続く、この発明の第６実施例の半導体装置の要部製造工程断面図
【図１４】この発明の第７実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図
【図１５】この発明の第８実施例の半導体装置の要部製造工程断面図
【図１６】図１５に続く、この発明の第８実施例の半導体装置の要部製造工程断面図
【図１７】図１６に続く、この発明の第８実施例の半導体装置の要部製造工程断面図
【図１８】ストライプ状のシリコン柱を分断した場合の図
【図１９】この発明の第９実施例の半導体装置の要部断面図
【図２０】この発明の第１０実施例の半導体装置の要部製造工程断面図
【図２１】図２０に続く、この発明の第１０実施例の半導体装置の要部製造工程断面図
【図２２】図２１に続く、この発明の第１０実施例の半導体装置の要部製造工程断面図
【図２３】この発明の第１１実施例の半導体装置の要部製造工程断面図
【図２４】図２３に続く、この発明の第１１実施例の半導体装置の要部製造工程断面図
【図２５】図２４に続く、この発明の第１１実施例の半導体装置の要部製造工程断面図
【図２６】図２５に続く、この発明の第１１実施例の半導体装置の要部製造工程断面図
【図２７】従来の横型パワーＭＯＳＦＥＴの要部断面図
【図２８】本発明品の電位分布図
【図２９】従来品の電位分布図
【符号の説明】
１ ｐ基板
２、２０、３１、３９、６０、７５ ｎドリフト領域
３、２２、３３、４０、４３、５６、６３、７４ 空孔
４、２１、２３、２９、３２、３８、４２、５２、７１、７６ 酸化膜
５ ｐウエル領域
６ ｎウエル領域
７ ゲート酸化膜
８、７７ ゲート電極
９ ｎソース領域
１０ ｎドレイン領域
１１ ｐコンタクト領域
１２ ソース電極
１３、７８ ドレイン電極
１４ 層間絶縁膜
１５、３４ トレンチ
１６ ｎエピタキシャル層
１７、１９、２４、 ｎ拡散層
１８ イオン注入層
２５ 空隙
２６ 隙間
２７ ＣＶＤ酸化膜
２８ 窒化膜
３０ トレンチ幅
３５、４１ シリコン柱
３６ ポリシリコン
３７、７０ ｎ領域
５０ ＳＯＩ基板
５１ 半導体基板
５３ 分離領域
５４ 素子形成領域
５５ 酸化膜
６１ 熱酸化膜
６２ 熱ＣＶＤ酸化膜
７２ イオン注入
７３ ダメージ層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device such as a power IC (integrated circuit) which is applied to a power supply, a motor, an automobile and the like, and has a built-in and integrated lateral high-voltage power device. The present invention relates to a high breakdown voltage lateral MOS device.
[0002]
[Prior art]
As a structure of a conventional lateral power MOSFET integrated in a power IC, a structure has been reported in which a trench is formed and a long drift region is formed along the trench to ensure a withstand voltage (for example, see Patent Document 1). ).
FIG. 27 is a cross-sectional view of a main part of a conventional lateral power MOSFET. A trench 95 is formed in the p substrate 81, and phosphorus is obliquely ion-implanted into the inner wall of the trench 95. Thereafter, thermal oxidation is performed to fill the oxide film 83 in the trench 95 and form the n drift region 82. A LOCOS oxide film 84 is formed on oxide film 83, and a p-well region 85 and an n-well region 86 are formed in a surface layer of p-substrate 81. An n source region 89 and a p contact region 91 are formed in the surface layer of the p well region 85, and an n drain region 90 is formed in the surface layer of the n drift region 82 and the surface layer of the n well region 86. A gate electrode 88 is formed on a p well region 85 interposed between an n source region 89 and an n drift layer via a gate oxide film 87, and a source electrode 92 is formed on the n source region 89 and the p contact region 91. , A drain electrode 93 is formed on the n drain region 90. Reference numeral 94 in the figure denotes an interlayer insulating film.
[0003]
Since the integrated circuit is formed on the same semiconductor substrate as other low breakdown voltage control elements, the source electrode 92, the gate electrode 88, and the drain electrode 93 are provided on the surface of the p substrate 1. Further, in order to increase the breakdown voltage, the trench 95 is formed in the drift formation region between the gate and the drain for supporting the voltage as described above, and the n drift region 82 is formed around the trench by an oblique ion implantation method. By filling the oxide film 95 with the oxide film 95, sufficient electric field relaxation is achieved in the p substrate 1 even at a short distance.
The shape of the trench differs depending on the breakdown voltage class of 60 to 700 V. At 60 V, the trench width is about 3 μm and the depth is about 3 μm. At 700 V, a trench width of 20 μm and a depth of 20 μm are required. Since the trench is filled with an oxide film, the maximum critical electric field strength of the oxide film is about 30 times higher than that of silicon, which is a semiconductor substrate, so that the distance between the gate and the drain can be reduced (for a breakdown voltage class of 700 V, about 3 minutes). 1), high integration is enabled.
[0004]
In recent years, in order to achieve high integration of LSI, a dielectric isolation structure in which a trench is formed for element isolation and the trench is filled with an insulating film has been frequently used. In such a structure in which element isolation is performed by trench isolation (trench isolation), stress stress occurs in the trench due to a difference in thermal expansion coefficient between the insulating film to be filled and the semiconductor substrate, and the isolation characteristics are deteriorated. In addition, since the filling insulating film has a high dielectric constant, the parasitic capacitance becomes large, causing a problem such as a gate wiring delay. In order to solve these problems, holes are formed in the filling insulating film in the trench, the amount of the filling insulating film in the trench is reduced, and the stress stress due to the difference in thermal expansion coefficient between the insulating film and the semiconductor substrate is reduced. It is disclosed that crystal defects are prevented from entering the substrate, and that the dielectric constant of the filling insulating film in the trench is reduced to prevent gate wiring delay (for example, see Patent Document 2).
[0005]
Further, another document discloses that a hole is formed in an oxide film filling a trench of a trench isolation oxide film sandwiched between floating gate wirings of a MOS device constituting an integrated circuit of a flash memory, thereby forming a hole immediately below the trench isolation trench. It is disclosed that a crystal defect is prevented from being introduced into a source region to be formed (for example, see Patent Document 3).
In these Patent Documents 2 and 3, vacancies are formed in the filling insulating film having the trench isolation structure. The purpose thereof is to prevent generation of crystal defects and to reduce the average dielectric constant of the filling insulating film. This is to prevent a delay in gate wiring.
[0006]
As a method of forming the above-mentioned holes, He ions are implanted in the vicinity of an oxide film formed by a SIMOX (Silicon Implantation Oxide) process, and an oxide film adjacent to a damaged portion formed by the implantation is converted into holes. Is reported (for example, Non-Patent Document 125p-G-4).
[0007]
[Patent Document 1]
U.S. Pat. No. 5,844,275
[Patent Document 2]
JP 2000-183149 A
[Patent Document 3]
JP-A-2002-76299
[0008]
[Non-patent document 1]
Proceedings of the 63rd JSAP Lecture Meeting on Applied Physics, 2002.9
[0009]
[Problems to be solved by the invention]
When the trench is filled with an insulating film, the thermal expansion coefficient of the semiconductor substrate (here, silicon) is 7 times larger than that of the oxide film, and after the oxide film filling process at 800 to 1000 ° C., the filled oxide film and the silicon substrate Due to the difference in thermal expansion coefficient, the wafer warp is large, and in addition to the occurrence of the crystal defect due to the internal stress, there is a problem that the wafer warp becomes large and it becomes difficult to attach the wafer to the device stage in a later process. Occurs.
The amount of warpage of the wafer depends on the area ratio of the trench filled with the oxide film in the wafer surface. For example, when the ratio in the trench surface is 60%, in the case of a 6-inch diameter wafer, the amount of warpage is It is as large as 500 μm.
[0010]
In the structure in which the drift region is formed along the trench, the maximum critical electric field strength of the oxide film filling the trench is about 30 times that of silicon, which is a semiconductor substrate, and the relative dielectric constant is smaller than that of silicon. The breakdown voltage can be held by the oxide film in the trench, the gate-drain distance can be reduced (about one third in a breakdown voltage class of 700 V), and high integration can be achieved.
However, in order to achieve higher integration, it is necessary to further reduce the distance between the gate and the drain of the high breakdown voltage lateral MOS device.
Further, in the case of the above-described separation structure having holes, the separation width having one hole is relatively narrow. However, even in the case of a wide groove separation structure, the separation width is reduced to achieve high integration. It is required to do it.
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which are capable of reducing the amount of warpage of a wafer, reducing the distance between a gate and a drain, and achieving high integration by reducing the separation width of a wide separation region. To provide.
[0012]
[Means for Solving the Problems]
To achieve the above objectives,
(1) a source region formed in the surface layer of the semiconductor substrate, a drain region formed in the surface layer of the semiconductor substrate apart from the source region, and the semiconductor substrate sandwiched between the drain region and the source region. A hole formed and an upper portion separated by an insulating film, a drift region formed in the semiconductor substrate along the hole between the drain region and the source region, and formed in contact with the drain region; A gate electrode formed on the semiconductor substrate between the source region and the drift region via a gate insulating film; a source electrode formed on the source region; and a drain electrode formed on the drain region And a configuration having:
(2) a source region formed in the surface layer of the semiconductor substrate, a drain region formed in the surface layer of the semiconductor substrate apart from the source region, and the semiconductor substrate sandwiched between the drain region and the source region. The formed trench, an insulating film filling the trench, a void formed inside the insulating film, and the semiconductor substrate formed along the trench between the drain region and the source region; The semiconductor device includes a drift region formed in contact with the drain region, a source electrode formed on the source region, and a drain electrode formed on the drain region.
(3) The plurality of holes may be formed in a direction parallel to the surface of the semiconductor substrate. (4) It is preferable that the plane shape of the hole is a lattice shape.
(5) In a semiconductor device having a dielectric isolation region, the dielectric isolation region includes a trench formed in a semiconductor substrate, an insulating film formed in the trench, and a surface of the semiconductor substrate inside the insulating film. And a plurality of holes formed in parallel directions.
(6) In a semiconductor device having a dielectric isolation region, the dielectric isolation region includes a trench formed in a semiconductor substrate, an insulating film formed in the trench, and a planar shape inside the insulating film having a lattice shape. It has a configuration having holes.
(7) In the method of manufacturing a semiconductor device according to (1), a step of forming a trench in the first conductivity type semiconductor substrate and a step of forming an epitaxial layer doped with the second conductivity type impurity in the trench and the surface of the semiconductor substrate. Heat-treating in a reducing atmosphere, closing the trench opening, and simultaneously forming a second conductivity type drift region and a hole surrounded by the drift region in the semiconductor substrate; Insulating the drift region and isolating the upper portion of the drift region with the insulating film.
(8) In the method of manufacturing a semiconductor device according to (1), a step of forming a trench in the first conductivity type semiconductor substrate, a step of ion-implanting the second conductivity type impurity into the trench and the surface of the semiconductor substrate, and a reducing atmosphere Forming a second conductivity type drift region and a hole surrounded by the drift region in the semiconductor substrate at the same time, and forming the drift region above the hole in the semiconductor substrate. Insulating the insulating film and separating the upper portion of the drift region with the insulating film.
(9) In the method for manufacturing a semiconductor device according to any one of (2) to (4), a step of forming a trench in a semiconductor substrate, a step of forming a drift region along the trench, and a step of forming a heat in the trench. Forming an oxide film, closing the trench opening with the thermal oxide film, and forming a hole inside the thermal oxide film.
(10) In the method for manufacturing a semiconductor device according to any one of (2) to (4), a step of forming a trench in the semiconductor substrate, a step of forming a drift region along the trench, and a step of forming a chemical in the trench. Forming an insulating film by a vapor deposition method, closing a trench opening with the insulating film, and forming a hole inside the thermal insulating film.
(11) In the method of manufacturing a semiconductor device of (2), a step of forming a trench in the semiconductor substrate, a step of heat-treating in a reducing atmosphere to narrow the trench opening, and a step of oxidizing to form a thermal oxide film in the trench. And closing the trench opening with the thermal oxide film to form a hole.
(12) a step of forming a trench in the semiconductor substrate to form a plurality of semiconductor pillars; a step of oxidizing the semiconductor pillar by thermal oxidation and forming a thermal oxide film in the trench; Forming an insulating film by a phase growth method, closing an opening of the trench with the insulation, and forming a hole inside the insulating film.
(13) a step of forming a trench in the semiconductor substrate to form a plurality of semiconductor pillars, and oxidizing the semiconductor pillar by thermal oxidation and forming a thermal oxide film in the trench; And clogging with a thermal oxide film to form pores inside the oxide film.
(14) In the manufacturing methods of (12) and (13), after the step of forming the semiconductor pillar, the manufacturing method includes a step of performing heat treatment in a reducing atmosphere to narrow the trench opening.
(15) a step of forming a trench in the semiconductor substrate, a step of heat-treating in a reducing atmosphere to narrow the trench opening, a step of thermally oxidizing to form a thermal oxide film in the trench, and closing the trench opening with the thermal oxide film And forming a hole in the thermal oxide film.
(16) In the manufacturing method of (7), (8), (14) or (15), the reducing atmosphere is any one of argon gas, hydrogen gas, or a gas obtained by mixing hydrogen with argon gas. Good.
[Action]
In this structure, since the relative permittivity (= 1) of the vacancy (in the case of air) is smaller than the relative permittivity (= 4) of the oxide film, the potential applied according to Gauss' law is the vacancy of this ratio. Since it is supported, the trench width (hole width) can be reduced to 3 to 4 times while maintaining the withstand voltage as compared with the case where the trench is filled with the conventional oxide film, so that the element pitch can be reduced and the cost is reduced. This is advantageous.
[0013]
FIG. 28 shows a potential distribution diagram of the product of the present invention, and FIG. 29 shows a potential distribution diagram of the conventional product. This is a case where a voltage of 70 V is applied between the source and the drain, and it can be seen that in the present invention, equipotential lines can be densely formed in the holes, and the distance between the gate and the drain can be shorter than that of the conventional product.
Conventionally, since the entire trench was filled with an oxide film, the volume of the oxide film having a coefficient of thermal expansion greatly different from that of silicon was large. However, in the structure of the present invention, the trench width is reduced and the inside of the trench is reduced. Since holes (filled with air or an inert gas) are formed, the warpage of the wafer during the manufacturing process does not increase. Therefore, the present invention can be applied to a large current (low on-resistance) semiconductor device having a large trench formation area ratio. Further, since the device pitch is reduced as compared with the conventional structure, the chip size can be reduced with the same on-resistance, and the on-resistance can be reduced with the same chip size.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of a main part, and FIG. 1B is a cross-sectional view taken along line XX of FIG. It is principal part sectional drawing. FIG. 3A is a plan view of the cross-sectional view of FIG. In the following description, the case where a p substrate is used is shown, but the conductivity type of each region may be reversed using an n substrate, or only the substrate may be used as an n substrate. In addition, n represents an n-type conductivity, and p represents a p-type conductivity.
A not-shown stripe-shaped trench is formed in a p-substrate 1 (silicon substrate), and an n-drift region 2 (also referred to as an n-offset drain region) is formed along the hole 3 in this trench. An oxide film 4 is formed above the holes 1, and a p-well region 5 and an n-well region 6 are formed in the surface layer of the p substrate 1. An n source region 9 and a p contact region 11 are formed in a surface layer of the p well region 5, and an n drain region 10 is formed in a surface layer of the n well region 6. Gate electrode 8 is formed on p well region 5 interposed between n source region 9 and n drift region 2 with gate oxide film 7 interposed therebetween, and interlayer insulating film 14 is formed thereon. A source electrode 12 is formed on the n source region 9 and the p contact region 11, and a drain electrode 13 is formed on the n drain region 10. Note that the n-well region 6 is a region that complements the n-drain region 10, and need not be formed.
[0015]
In this structure, as described above, since the relative permittivity (= 1) of the holes 3 (in the case of air) is smaller than the relative permittivity (= 4) of the oxide film, the potential applied according to Gauss's law is Since it is supported on the hole side at this ratio, the trench width (hole width) can be reduced to 3 to 4 times as compared with the case where the trench is filled with a conventional oxide film. Therefore, the element pitch can be reduced, and the cost can be reduced.
When a high breakdown voltage lateral MOSFET of a breakdown voltage class of 70 V was manufactured, the on-resistance was conventionally 70 mΩmm. 2 Was 50 mΩmm 2 Was reduced to This is because the formation of the holes reduces the distance between the gate and the drain while maintaining the breakdown voltage, thereby increasing the integration density (higher integration) of the MOSFET cells.
[0016]
Conventionally, since the entire trench is filled with an oxide film, the volume of the oxide film having a large difference in thermal expansion coefficient from that of silicon is large. However, in this structure, the trench width becomes narrow and the inside of the trench becomes empty. Since holes are formed and the volume of the oxide film can be reduced, the amount of warpage of the wafer can be significantly reduced.
More specifically, the wafer warpage at the end of the process was as small as 20 μm in the present structure, although it was 500 μm conventionally. Therefore, it is possible to prevent troubles caused by the warpage of the wafer during the manufacturing process.
By forming holes and reducing the amount of warpage of the wafer, the trench formation area ratio can be increased as compared with the conventional case, and a semiconductor device having a high withstand voltage and a large current (low on-resistance) can be manufactured.
[0017]
2 to 4 show a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and are cross-sectional views of the main part manufacturing steps shown in the order of steps. This is a method for manufacturing the semiconductor device of FIG.
A trench 15 having an opening width of 1 μm and a depth of 3 μm is formed in a p substrate 1 (silicon substrate) having a specific resistance of 15 Ωcm and an impurity concentration of phosphorus atoms is 1 × 10 17 cm -3 To grow an n-type epitaxial layer 16 having a thickness of 1 μm (FIG. 2).
Next, Ar gas 96%, H 2 Annealing is performed at 1100 ° C. for 10 minutes at a reduced pressure of 40 Torr (40 × 133 Pa) in a reducing atmosphere (hydrogen atmosphere) of 4% gas to bring the silicon on the surface into contact with the inside of the hole 3 (width of 1 μm, top of the hole and substrate A silicon width between surfaces of 0.5 μm) is formed. At this time, phosphorus is re-diffused from the surface of the p substrate 1 and the n epitaxial layer 16 formed inside the trench 15, and the surface concentration is 5 × 10 5 16 cm -3 An n-type diffusion layer 17 having a depth of 3 μm is formed (FIG. 3).
[0018]
Next, a surface concentration of 5 × 10 16 cm -3 Then, a p-well region 5 which is a p-type diffusion layer having a depth of 3 μm is formed, and a surface concentration of 5 × 10 16 cm -3 Then, an n-well region 6 which is an n-type diffusion layer having a depth of 3 μm is formed. In this case, the hole 3 is formed in a deep portion, and the n-diffusion layer 17 formed in the surface layer of the p-substrate 1 is removed so as not to reach the hole 3, and then the p-well region 5 and the n-well region 6 are removed. It may be formed. Subsequently, a nitride film (not shown) is formed on each of the n source, gate, and drain region forming portions, and thermal oxidation is performed to form a 1.0 μm-thick oxide film 4 on the surface where the gate-drain nitride film does not exist. (LOCOS oxide film) is formed. At this time, silicon between the upper portion of the holes 3 and the substrate surface is completely oxidized to become an oxide film. Thereafter, the nitride film is removed, a gate oxide film 7 having a thickness of 0.025 μm is formed, a gate electrode 8 is formed on the gate oxide film 7, and n + Diffusion is performed to form an n-source region 9, and a p-well contact p is formed. + An n-drain region is formed in the diffusion layer (p-contact region) and a surface layer of the n-well region. An interlayer insulating film 14 is formed on the gate electrode 8, a source electrode 12 is formed on the n source region 9 and the p contact region 11, and a drain electrode 13 is formed on the n drain region 10 (FIG. 4). The reducing atmosphere was Ar gas only, H 2 It may be gas alone.
[0019]
5 and 6 show a method of manufacturing a semiconductor device according to a third embodiment of the present invention, and are cross-sectional views of the main part manufacturing steps shown in the order of steps. The manufacturing method of the semiconductor device of FIG. 1 is different from that of the second embodiment.
The difference from the second embodiment is that an n-type impurity is ion-implanted into the side wall and the bottom surface of the trench 15 to form the ion-implanted layer 18 instead of performing epitaxial growth after forming the trench.
An ion implantation layer 18 is formed in the trench 15 (FIG. 5). Next, heat treatment is performed in the same manner as in FIG. 3 to form the holes 3 and the n-diffusion layer 19 (FIG. 6). Subsequent steps are the same as in FIG.
[0020]
More specifically, a dose of 1 × 10 at 80 keV Thirteen cm -2 Is ion-implanted (doped) to form an ion-implanted layer 18, and then heat-treated (drive) at 1150 ° C. for 200 minutes to perform a surface concentration of 5 × 10 16 cm -3 Then, an n diffusion layer 19 having a depth of 3 μm is formed. The n diffusion layer 19 becomes the n drift region 2 formed around the hole 3.
An oxide film is used as a mask for forming the trench 15, but if ion implantation is performed before removing the oxide film, the n-diffusion layer 19 can be formed only on the side wall and the bottom surface of the trench 15. This eliminates the need for the step of removing the n-diffusion layer 17 formed on the surface layer of the p-type substrate 1 as shown in FIG.
[0021]
FIG. 7 is a sectional view showing a main part of a semiconductor device according to a fourth embodiment of the present invention. The difference from FIG. 1 is that holes 22 are covered with oxide film 21. Since oxide film 21 is interposed between n drift region 20 and holes 22, the relative dielectric constant gradually decreases from silicon toward the holes, so that the potential distribution is more narrowly clogged as compared with FIG. And electric field concentration hardly occurs. FIG. 27 is a diagram showing the state of equipotential lines when 70 V is applied to the product of the present invention (70 V withstand voltage product). Further, similarly to the first embodiment, the distance between the gate and the drain can be reduced, and high integration can be achieved. As a result, a high breakdown voltage lateral MOSFET with low on-resistance can be manufactured. Further, since the holes are formed, the amount of warpage of the wafer can be made equal to that of the first embodiment. In the figure, D2 is the hole length, W2 is the hole width, and Wox2 is the oxide film thickness.
[0022]
8 to 10 show a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. This is a method for manufacturing the semiconductor device shown in FIG. 7, which is different from the second embodiment in that a gap is formed above a hole.
Similarly to FIG. 2, a not-shown trench having a width of 1 μm and a depth of 3 μm is formed in a p-substrate 1 having a specific resistance of 15 Ωcm, and an impurity concentration of phosphorus atoms is 1 × 10 5. 17 cm -3 To grow a 1 μm thick n-type epitaxial layer.
Next, Ar gas 96%, H 2 Annealing is performed at 1100 ° C. for 10 minutes at a reduced pressure of 40 Torr in a reducing atmosphere (hydrogen atmosphere) of 4% gas to bring the silicon on the surface close to each other, to form a gap 25 having a gap 26 at the top (width of 1 μm, the top of the hole and the substrate surface). (A silicon width of 0.5 μm). At this time, phosphorus is re-diffused from the surface of the p substrate 1 and the n epitaxial layer formed inside the trench, and the surface concentration is 5 × 10 5 16 cm -3 , An n-type diffusion layer 24 having a depth of 3 μm is formed (FIG. 8).
[0023]
Next, the surface of the silicon substrate and the surface of the trench are oxidized by thermal oxidation. At first, an oxide film grows on the surface of the p substrate 1 and the surface of the trench. 21 and a hole 22 is formed in the center of the trench. The oxide film thickness inside this trench is 0.5 μm, and the hole width is 0.5 μm (FIG. 9).
Next, the oxide film 21 in the gate, source and drain portions is removed using a mask. Thereafter, the surface concentration is 5 × 10 16 cm -3 Then, a p-well region 5 which is a p-type diffusion layer having a depth of 3 μm is formed, and a surface concentration of 5 × 10 16 cm -3 Then, an n-well region 6 which is an n-type diffusion layer having a depth of 3 μm is formed. Subsequently, a nitride film (not shown) is formed on each of the source, gate, and drain region forming portions, and thermal oxidation is performed to form a 1.0 μm-thick oxide film 23 on the surface where the gate-drain nitride film does not exist. Form. At this time, the silicon between the hole upper part and the substrate surface is completely oxidized to become the oxide film 23. Thereafter, the nitride film is removed, a gate oxide film 7 having a thickness of 0.025 μm is formed, a gate electrode 8 is formed on the gate oxide film 7, and n + Diffusion is performed to form an n-source region 9, and a p-well contact p is formed. + A p-contact region 11 serving as a diffusion layer is formed, and an n-drain region 10 is formed in a surface layer of the n-well region 6. An interlayer insulating film 14 is formed on the gate electrode 8, a source electrode 12 is formed on the n source region 9 and the p contact region 11, and a drain electrode 13 is formed on the n drain region 10. Note that the n-well region 6 is a region that complements the n-drain region 10, and need not be formed (FIG. 10).
[0024]
In the trench oxidation of the fifth embodiment, the oxide film on the upper portion of the trench is connected by volume expansion due to thermal oxidation. However, the bonding surface is a physical connection, and the hole 22 is easily formed by wet etching in a later step. A route is created, and there is a concern that the chemical solution may enter and exit the holes.
In order to prevent this, a short-time annealing at 1300 ° C. at a high temperature is conceivable, but a more preferable method is to oxidize a CVD (Chemical Vapor Deposition) oxide film 27 as shown in FIG. By depositing on the film 21, a good-quality oxide film is formed on the path to the hole 22, so that the formation of the gap 26 leading to the hole 22 can be prevented.
[0025]
In this embodiment, the gap 25 is formed by annealing in a reducing atmosphere. However, when forming the trench, a trench whose bottom is wider than the opening of the trench may be formed. In this case, annealing in a reducing atmosphere may not be performed, and annealing in a nitrogen atmosphere may be used. Further, in the following embodiments, the same can be said for forming a trench.
12 and 13 show a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention. This is a further development of the fifth embodiment.
[0026]
After annealing in a reducing atmosphere, a surface concentration of 5 × 10 16 cm -3 Then, a p-well region 5 which is a p-type diffusion layer having a depth of 3 μm is formed, and a surface concentration of 5 × 10 16 cm -3 Then, an n-well region 6 which is an n-type diffusion layer having a depth of 3 μm is formed, and a nitride film 29 is formed in each of the source, gate, and drain region formation portions (FIG. 12).
Next, by performing thermal oxidation, an oxide film 29 having a thickness of 1.0 μm is formed on the surface where the nitride film 28 between the gate and the drain does not exist. The upper portion of the trench and the side wall of the trench are oxidized. In particular, the oxide film 28 is completely connected to the upper portion of the trench. Thereafter, the nitride film 28 is removed (FIG. 13).
[0027]
Next, the nitride film 28 is removed, and a gate oxide film 7 having a thickness of 0.025 μm is formed as shown in the process of FIG. 10, a gate electrode 8 is formed on the gate oxide film 7, and a source formation portion is formed. n + Diffusion is performed to form an n-source region 9, and a p-well contact p is formed. + A p-contact region 11 serving as a diffusion layer is formed, and an n-drain region 10 is formed in a surface layer of the n-well region 6. An interlayer insulating film 14 is formed on the gate electrode 8, a source electrode 12 is formed on the n source region 9 and the p contact region 11, and a drain electrode 13 is formed on the n drain region 10. In this structure, the oxide film 23 and the oxide film 22 shown in FIG. 10 can be simultaneously formed using the same nitride film 28 as a mask used as a mask when forming a LOCOS oxide film of a CMOS circuit element (not shown). There are advantages.
[0028]
In the semiconductor device of each of the embodiments described above, the example in which the element withstand voltage (BVds) is 70 V has been described. However, the same structure is established when the withstand voltage is 120 V or 700 V, and the parameters shown in Table 1 are obtained by scaling. ). D1 and W1 in the table are D1 and W1 shown in FIG. 1, and D2, W2 and Wox2 are D2, W2 and Wox2 shown in FIG.
[0029]
[Table 1]
Figure 2004153140
14A and 14B are configuration diagrams of a semiconductor device according to a seventh embodiment of the present invention. FIG. 14A is a plan view of a main part, and FIG. 14B is a cross-sectional view taken along line XX of FIG. It is principal part sectional drawing. FIG. 2A is a plan view as viewed from the YY plane in FIG. 1B.
The difference from FIG. 1 is that the number of holes 33 is plural when the trench width 30 is wide. In this figure, the case where three holes 33 are provided is shown. However, when the element withstand voltage is high, the trench width 30 is widened, and the number of the holes 33 is increased. That is, the number of the holes 33 may be selected according to the element withstand voltage.
[0030]
FIGS. 15 to 17 show a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention, which is a cross-sectional view of a main part manufacturing step shown in the order of steps. This is different from the second embodiment in the step of forming a plurality of trenches in order to form a plurality of holes.
Three trenches 34 each having a width of 1 μm and a depth of 20 μm are formed at an equal pitch in a p-type silicon substrate having a specific resistance of 15 Ωcm. That is, two silicon pillars 35 (semiconductor pillars) are formed between the trenches. The trench interval is 0.5 μm. Next, polysilicon 36 containing phosphorus is deposited by a low pressure CVD method, and the surface concentration is 5 × 10 5. 16 cm -3 Drive at a high temperature of 1100 ° C. or more so as to form an n-type impurity layer having a junction depth (Xj) of 3 μm. Here, the thickness of the polysilicon 36 may be any thickness and drive (heat treatment) condition such that Xj = 3 μm (FIG. 15).
[0031]
After the drive, annealing is performed at 1100 ° C. for 3 minutes in a reducing atmosphere (the above-described hydrogen atmosphere) at a reduced pressure of 40 Torr, so that the width of the trench opening becomes smaller than the width of the trench bottom. For example, at the trench opening, the trench width is 0.5 μm, and the distance between the trenches (inter-trench silicon pillar 35) is 1 μm. With this drive, an n region 37 to be an n drift region 39 is formed (FIG. 16).
Next, the silicon pillar 35 is oxidized at 1000 ° C. by thermal oxidation. Due to this oxidation, the volume of the silicon pillar 35 is increased, and the trench openings are connected to each other with the pillars forming an oxide film 38 while leaving the holes 40 inside the trench 34 (FIG. 17). In the figure, three trenches 34 are closed as oxide films at the upper part, so that the inside of the wide trench is filled with an oxide film 38 having holes 40, but the number of trenches 34 is It can be arbitrarily changed, and is adjusted so that the drift length finally obtained by the element withstand voltage (BVds) satisfies the requirement.
[0032]
Next, as shown in the step of FIG. 16 cm -3 Then, a p-well region 5 which is a p-type diffusion layer having a depth of 3 μm is formed, and a surface concentration of 5 × 10 16 cm -3 Then, an n-well region 6 which is an n-type diffusion layer having a depth of 3 μm is formed. Thereafter, a nitride film (not shown) is removed, a gate oxide film 7 having a thickness of 0.025 μm is formed, a gate electrode 8 is formed on the gate oxide film 7, and n is formed in a source formation portion. + Diffusion is performed to form an n source region 9, and an n drain region 10 is formed in the surface layer of the n well region 6. An interlayer insulating film 14 is formed on the gate electrode 8, a source electrode 12 is formed on the n source region 9 and the p contact region 11, and a drain electrode 13 is formed on the n drain region 10.
[0033]
In addition, as shown in FIG. 18, the silicon pillars in a stripe shape may be divided into a large number of silicon pillars 41. In this case, the holes 43 are connected as shown by hatching, and the occupancy of the holes 43 can be increased.
FIG. 19 is a sectional view showing a main part of a semiconductor device according to a ninth embodiment of the present invention. This is the case where an isolation region 53 for dielectric isolation is formed in the SOI substrate 50, and a hole 56 is formed in the isolation region 53. Also in this case, the width of the isolation region can be reduced, which is effective for high integration. The method of forming the isolation region having the holes is the same as the method of forming the holes in the trench.
[0034]
20 to 22 show a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention, which is a sectional view of a main part manufacturing step shown in the order of steps. This is a method of manufacturing the semiconductor device shown in FIGS. 7 and 14, and particularly describes the flattening of an insulating film formed on a surface necessary for forming a device after holes are formed. . Here, the case where a plurality of holes are provided as shown in FIG. 14 is described. Of course, this can also be applied to the dielectric isolation structure of FIG.
The surface of the p-substrate 1 is oxidized to a thickness of 30 nm, then a nitride film is deposited to a thickness of 100 nm, and after applying a resist, a region where the n drift region 60 of the lateral high voltage MOSFET is to be formed is exposed to remove the nitride film and the oxide film. Thereafter, after the resist is ashed and the resist is removed, silicon etching is performed to form a trench having a width of 3 μm and a depth of 20 μm. Next, a film of phosphorus-doped polysilicon is formed on the inner wall of the trench, and drive is performed so that the p-type substrate 1 is driven so that the diffusion depth (the depth Xj of the pn junction) is about 6 μm. Next, the polysilicon in the trench is oxidized and removed, and the silicon column between the trenches in the trench is thermally oxidized by thermal oxidation, and a thermal oxide film 61 is formed in the trench. Before the thermal oxidation, annealing may be performed in a reducing atmosphere. Since the width of the trench after thermal oxidation is about 2 μm, a thermal CVD oxide film 62 is formed by thermal CVD or the like. In the formation of the thermal CVD oxide film 62, the inside of the trench is not completely filled with the oxide film, and a hole 63 is formed inside the trench. However, under the influence of the irregularities due to the trench, the upper end of the thermal CVD oxide film 62 has an irregular shape (FIG. 20).
[0035]
Next, the uneven surface of the thermal CVD oxide film 62 is polished and removed by a CMP (Chemical Mechanical Polishing) method to be flattened. By using this CMP method, the inside of the oxide film can be planarized with an arbitrary polishing depth without using a stopper (FIG. 21).
Next, the remaining thermal CVD oxide film 62 is removed by wet etching or dry etching with reference to the flat polished surface 64 of the thermal CVD oxide film 62 planarized by the CMP method until the silicon surface is exposed. A thermal CVD oxide film 62 having holes 63 is formed (FIG. 22).
[0036]
Next, a p-well region and an n-well region (not shown) are formed, and gate, source, and drain regions and respective electrodes are formed to obtain a semiconductor device as shown in FIG.
In this manner, by flattening by the CMP method, it is possible to reliably form a hole whose upper portion is closed by the thermal CVD oxide film. By making the holes closed, it is possible to prevent the resist from entering the holes and to prevent metal contamination and particle contamination in the holes. As a result, a highly reliable semiconductor device can be manufactured.
FIGS. 23 to 26 show a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention, which is a sectional view showing main steps in the order of manufacturing steps. In this method, holes are formed directly in a semiconductor substrate without forming trenches.
[0037]
An n region serving as an n drift region is formed on the p substrate 1 sandwiched between the formation region of the gate electrode 77 and the formation region of the drain electrode 78. Next, an oxide film 71 is formed on a part of the n region 70 by a SIMOX process (FIG. 23).
Next, light element ions (such as He ions) penetrate through the oxide film 71 and are implanted into the n-region 70 to form a damaged layer 73 near the oxide film 71 (FIG. 24).
Next, a reducing atmosphere (Ar gas containing O 2 Is heat-treated at a high temperature of 1300 ° C. or more by using a gas mixed with the oxide film 71 to convert the oxide film 71 adjacent to the damaged layer 73 into holes 74 and form holes in the n region 70 (FIG. 25). .
[0038]
Thereafter, the n region 70 above the hole 74 is oxidized to form an oxide film 76, and the n drift region 75, the p well region, the n well region, the gate electrode 77, the n source region, the n drain region, the source electrode, A drain electrode 78 and the like are formed (FIG. 26).
According to this manufacturing method, since the holes 74 can be formed in the semiconductor substrate without forming a trench, the inside of the holes 74 is not contaminated and a highly reliable semiconductor device can be manufactured.
Further, since the holes 74 are formed, the distance between the gate and the drain can be reduced, and high integration can be achieved, as in the above embodiment. Also, the amount of warpage of the wafer can be reduced.
[0039]
【The invention's effect】
According to the present invention, by forming a hole in the insulating film filling the trench of the high breakdown voltage lateral MOS device in which the drift region is formed along the trench, the dielectric constant in the trench is reduced, and the gate-drain gap is reduced. Can be shortened, and high integration can be achieved.
Also, by forming holes in the insulating film filling the trench, the amount of warpage of the wafer can be significantly reduced.
Further, by forming a plurality of holes in the insulating film in the isolation region of the wide dielectric isolation structure, the width of the isolation region can be reduced, and high integration can be achieved.
[0040]
In addition, the insulating film that closes the holes is planarized by CMP to form holes that are reliably closed at the top, thereby contaminating the holes (resist penetration, metal contamination, particle contamination, etc.). Can be prevented, and the reliability of the semiconductor device can be improved.
[Brief description of the drawings]
FIGS. 1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view of a main part, and FIG. 1B is a cross-sectional view of the main part taken along line XX of FIG.
FIG. 2 is a sectional view of a main part manufacturing process of a semiconductor device according to a second embodiment of the present invention;
FIG. 3 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 2;
FIG. 4 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 3;
FIG. 5 is a sectional view of a main part manufacturing step of a semiconductor device according to a third embodiment of the present invention;
FIG. 6 is a sectional view of a main part manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 5;
FIG. 7 is a sectional view of a main part of a semiconductor device according to a fourth embodiment of the present invention;
FIG. 8 is a sectional view of a main part manufacturing step of a semiconductor device according to a fifth embodiment of the present invention;
FIG. 9 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the fifth embodiment of the present invention, following FIG. 8;
FIG. 10 is a sectional view of a main part manufacturing step of the semiconductor device according to the fifth embodiment of the present invention, following FIG. 9;
FIG. 11 is a diagram in which a surface is coated with a CVD oxide film.
FIG. 12 is a sectional view of a main part manufacturing step of a semiconductor device according to a sixth embodiment of the present invention;
FIG. 13 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the sixth embodiment of the present invention, following FIG. 12;
FIGS. 14A and 14B are configuration diagrams of a semiconductor device according to a seventh embodiment of the present invention, wherein FIG. 14A is a plan view of a main part, and FIG.
FIG. 15 is a sectional view showing a main part manufacturing process of a semiconductor device according to an eighth embodiment of the present invention;
FIG. 16 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the eighth embodiment of the present invention, following FIG. 15;
FIG. 17 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the eighth embodiment of the present invention, following FIG. 16;
FIG. 18 is a view when a silicon pillar in a stripe shape is divided.
FIG. 19 is a sectional view of a main part of a semiconductor device according to a ninth embodiment of the present invention;
FIG. 20 is a sectional view of a main part manufacturing step of a semiconductor device according to a tenth embodiment of the present invention;
FIG. 21 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the tenth embodiment of the present invention, following FIG. 20;
FIG. 22 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the tenth embodiment of the present invention, following FIG. 21;
FIG. 23 is a cross-sectional view of a main part manufacturing step of a semiconductor device according to an eleventh embodiment of the present invention;
FIG. 24 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the eleventh embodiment of the present invention, following FIG. 23;
FIG. 25 is a cross-sectional view of a main part manufacturing step of the semiconductor device of the eleventh embodiment of the present invention, following FIG. 24;
FIG. 26 is a cross-sectional view of a main part manufacturing step of the semiconductor device of the eleventh embodiment of the present invention, following FIG. 25;
FIG. 27 is a sectional view of a main part of a conventional lateral power MOSFET.
FIG. 28 is a potential distribution diagram of the product of the present invention.
FIG. 29 is a potential distribution diagram of a conventional product.
[Explanation of symbols]
1p substrate
2, 20, 31, 39, 60, 75 n drift regions
3, 22, 33, 40, 43, 56, 63, 74
4, 21, 23, 29, 32, 38, 42, 52, 71, 76 oxide film
5 p-well region
6 n-well region
7 Gate oxide film
8,77 Gate electrode
9 n source region
10 n drain region
11p contact area
12 Source electrode
13,78 Drain electrode
14 Interlayer insulation film
15, 34 trench
16 n epitaxial layer
17, 19, 24, n diffusion layer
18 Ion implantation layer
25 void
26 gap
27 CVD oxide film
28 nitride film
30 trench width
35, 41 Silicon pillar
36 polysilicon
37, 70 n regions
50 SOI substrate
51 Semiconductor substrate
53 separation area
54 Device formation area
55 oxide film
61 Thermal oxide film
62 Thermal CVD oxide film
72 Ion implantation
73 Damage Layer

Claims (16)

半導体基板の表面層に形成されるソース領域と、
該ソース領域と離して半導体基板の表面層に形成されるドレイン領域と、
該ドレイン領域と前記ソース領域に挟まれた前記半導体基板に形成され上部が絶縁膜で分離された空孔と、
前記ドレイン領域と前記ソース領域の間の前記空孔に沿う前記半導体基板に形成され、前記ドレイン領域と接して形成されるドリフト領域と、
前記ソース領域と前記ドリフト領域に挟まれた前記半導体基板上にゲート絶縁膜を介して形成されるゲート電極と、
前記ソース領域上に形成されるソース電極と、前記ドレイン領域上に形成されるドレイン電極と、
を有することを特徴とする半導体装置。A source region formed on a surface layer of the semiconductor substrate;
A drain region formed in a surface layer of the semiconductor substrate apart from the source region;
A hole formed in the semiconductor substrate sandwiched between the drain region and the source region and having an upper portion separated by an insulating film;
A drift region formed in the semiconductor substrate along the hole between the drain region and the source region, and formed in contact with the drain region;
A gate electrode formed on the semiconductor substrate sandwiched between the source region and the drift region via a gate insulating film;
A source electrode formed on the source region, a drain electrode formed on the drain region,
A semiconductor device comprising: 半導体基板の表面層に形成されるソース領域と、
該ソース領域と離して半導体基板の表面層に形成されるドレイン領域と、
該ドレイン領域と前記ソース領域に挟まれた前記半導体基板に形成されたトレンチと、
該トレンチに充填された絶縁膜と、
該絶縁膜内部に形成された空孔と、
前記ドレイン領域と前記ソース領域の間の前記トレンチに沿う前記半導体基板に形成され、前記ドレイン領域と接して形成されるドリフト領域と、
前記ソース領域上に形成されるソース電極と、前記ドレイン領域上に形成されるドレイン電極と、
を有することを特徴とする半導体装置。A source region formed on a surface layer of the semiconductor substrate;
A drain region formed in a surface layer of the semiconductor substrate apart from the source region;
A trench formed in the semiconductor substrate sandwiched between the drain region and the source region;
An insulating film filled in the trench;
Vacancies formed inside the insulating film;
A drift region formed on the semiconductor substrate along the trench between the drain region and the source region, and formed in contact with the drain region;
A source electrode formed on the source region, a drain electrode formed on the drain region,
A semiconductor device comprising: 前記空孔が、半導体基板の表面と平行な方向に複数個形成されることを特徴とする請求項１または２に記載の半導体装置。The semiconductor device according to claim 1, wherein a plurality of the holes are formed in a direction parallel to a surface of the semiconductor substrate. 前記空孔の平面形状が格子状であることを特徴とする請求項１または２に記載の半導体装置。The semiconductor device according to claim 1, wherein a planar shape of the hole is a lattice. 誘電体分離領域を有する半導体装置において、該誘電体分離領域が、半導体基板に形成されたトレンチと、該トレンチ内に形成された絶縁膜と、該絶縁膜内部に半導体基板の表面と平行な方向に複数個形成された空孔とを有することを特徴とする半導体装置。In a semiconductor device having a dielectric isolation region, the dielectric isolation region includes a trench formed in a semiconductor substrate, an insulating film formed in the trench, and a direction parallel to a surface of the semiconductor substrate inside the insulating film. And a plurality of holes formed in the semiconductor device. 誘電体分離領域を有する半導体装置において、該誘電体分離領域が、半導体基板に形成されたトレンチと、該トレンチ内に形成された絶縁膜と該絶縁膜内部に平面形状が格子状の空孔とを有することを特徴とする半導体装置。In a semiconductor device having a dielectric isolation region, the dielectric isolation region includes a trench formed in a semiconductor substrate, an insulating film formed in the trench, and voids having a lattice shape in a planar shape inside the insulating film. A semiconductor device comprising: 前記請求項１に記載の半導体装置の製造方法において、第１導電形半導体基板にトレンチを形成する工程と、該トレンチと前記半導体基板表面に第２導電形不純物をドープしたエピタキシャル層を形成する工程と、還元雰囲気で熱処理し、トレンチ開口部を閉塞し、前記半導体基板に第２導電形ドリフト領域と、該ドリフト領域で囲まれた空孔とを同時に形成する工程と、前記空孔の上部の前記ドリフト領域を絶縁化し、該絶縁膜で前記ドリフト領域の上部を分離する工程と、を有することを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein a step of forming a trench in the semiconductor substrate of the first conductivity type and a step of forming an epitaxial layer doped with impurities of the second conductivity type in the trench and the surface of the semiconductor substrate. Heat-treating in a reducing atmosphere, closing the trench opening, and simultaneously forming a second conductivity type drift region and a hole surrounded by the drift region in the semiconductor substrate; Insulating the drift region and isolating the upper portion of the drift region with the insulating film. 前記請求項１に記載の半導体装置の製造方法において、第１導電形半導体基板にトレンチを形成する工程と、該トレンチと前記半導体基板表面に第２導電形不純物をイオン注入する工程と、還元雰囲気で熱処理し、トレンチ開口部を閉塞し、前記半導体基板に第２導電形ドリフト領域と、該ドリフト領域で囲まれた空孔とを同時に形成する工程と、前記空孔の上部の前記ドリフト領域を絶縁化し、該絶縁膜で前記ドリフト領域の上部を分離する工程と、を有することを特徴とする半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein a step of forming a trench in the first conductivity type semiconductor substrate, a step of ion-implanting the second conductivity type impurity into the trench and the surface of the semiconductor substrate, and a reducing atmosphere. Forming a second conductivity type drift region and a hole surrounded by the drift region in the semiconductor substrate at the same time; and forming the drift region above the hole in the semiconductor substrate. Insulating the semiconductor device and isolating an upper portion of the drift region with the insulating film. 前記請求項２〜４のいずれか一項に記載の半導体装置の製造方法において、半導体基板にトレンチを形成する工程と、該トレンチに沿うようにドリフト領域を形成する工程と、前記トレンチ内に熱酸化膜を形成し、トレンチ開口部を該熱酸化膜で閉塞し、該熱酸化膜の内部に空孔を形成する工程と、を有することを特徴とする半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 2, wherein a step of forming a trench in the semiconductor substrate, a step of forming a drift region along the trench, and a step of forming heat in the trench. Forming an oxide film, closing a trench opening with the thermal oxide film, and forming a hole in the thermal oxide film. 前記請求項２〜４のいずれか一項に記載の半導体装置の製造方法において、半導体基板にトレンチを形成する工程と、該トレンチに沿うようにドリフト領域を形成する工程と、前記トレンチ内に化学気相成長法で絶縁膜を形成し、トレンチ開口部を該絶縁膜で閉塞し、該熱絶縁膜の内部に空孔を形成する工程と、を有することを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 2, wherein a step of forming a trench in the semiconductor substrate, a step of forming a drift region along the trench, and a step of forming a trench in the trench. Forming an insulating film by a vapor deposition method, closing a trench opening with the insulating film, and forming a hole inside the heat insulating film. 前記請求項２に記載の半導体装置の製造方法において、半導体基板にトレンチを形成する工程と、還元雰囲気で熱処理し、トレンチ開口部を狭める工程と、酸化してトレンチ内に熱酸化膜を形成し、トレンチ開口部を該熱酸化膜で閉塞し、空孔を形成する工程と、を有することを特徴とする半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein a step of forming a trench in the semiconductor substrate, a step of heat-treating in a reducing atmosphere to narrow the trench opening, and a step of oxidizing to form a thermal oxide film in the trench. Forming a hole by closing a trench opening with the thermal oxide film. 半導体基板にトレンチを形成し複数の半導体柱を形成する工程と、熱酸化により、前記半導体柱を酸化するとともに前記トレンチ内に熱酸化膜を形成する工程と、前記トレンチ内に化学気相成長法で絶縁膜を形成し前記トレンチの開口部を該絶縁で閉塞し、該絶縁膜の内部に空孔を形成する工程と、を有することを特徴とする半導体装置の製造方法。Forming a trench in the semiconductor substrate to form a plurality of semiconductor pillars; oxidizing the semiconductor pillar by thermal oxidation and forming a thermal oxide film in the trench; and chemical vapor deposition in the trench. Forming an insulating film, closing the opening of the trench with the insulation, and forming a hole inside the insulating film. 半導体基板にトレンチを形成し複数の半導体柱を形成する工程と、熱酸化により、前記半導体柱を酸化するとともに前記トレンチ内に熱酸化膜を形成し、前記複数個のトレンチの開口部を熱酸化膜で閉塞し、該酸化膜の内部に空孔を形成する工程と、を有することを特徴とする半導体装置の製造方法。Forming a trench in the semiconductor substrate to form a plurality of semiconductor pillars, and oxidizing the semiconductor pillar by thermal oxidation, forming a thermal oxide film in the trench, and thermally oxidizing the openings of the plurality of trenches. Clogging with a film and forming a hole inside the oxide film. 半導体柱を形成する工程の後に、還元雰囲気で熱処理しトレンチ開口部を狭める工程を有することを特徴とする請求項１２または１３に記載の半導体装置の製造方法。14. The method according to claim 12, further comprising, after the step of forming the semiconductor pillar, a step of performing heat treatment in a reducing atmosphere to narrow the trench opening. 半導体基板にトレンチを形成する工程と、還元雰囲気で熱処理しトレンチ開口部を狭める工程と、熱酸化してトレンチ内に熱酸化膜を形成し、トレンチ開口部を該熱酸化膜で閉塞し、該熱酸化膜の内部に空孔を形成する工程と、を有することを特徴とする半導体装置の製造方法。Forming a trench in the semiconductor substrate, heat-treating in a reducing atmosphere to narrow the trench opening, thermally oxidizing to form a thermal oxide film in the trench, closing the trench opening with the thermal oxide film, Forming a hole in the thermal oxide film. 前記還元雰囲気が、アルゴンガス、水素ガスもしくはアルゴンガスに水素を混合したガスのいずれか一つであることを特徴とする請求項７、８、１４および１５のいずれか一項に記載の半導体装置の製造方法。16. The semiconductor device according to claim 7, wherein the reducing atmosphere is any one of argon gas, hydrogen gas, and a gas obtained by mixing hydrogen with argon gas. Manufacturing method.
JP2002318352A 2002-10-31 2002-10-31 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4288925B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002318352A JP4288925B2 (en) 2002-10-31 2002-10-31 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002318352A JP4288925B2 (en) 2002-10-31 2002-10-31 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2004153140A true JP2004153140A (en) 2004-05-27
JP4288925B2 JP4288925B2 (en) 2009-07-01

Family

ID=32461504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002318352A Expired - Fee Related JP4288925B2 (en) 2002-10-31 2002-10-31 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4288925B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347565A (en) * 2004-06-03 2005-12-15 Fuji Electric Device Technology Co Ltd Semiconductor device and method for manufacturing the same
JP2006310513A (en) * 2005-04-28 2006-11-09 Fuji Electric Device Technology Co Ltd Semiconductor device and method of manufacturing the same
CN102244028A (en) * 2010-05-13 2011-11-16 三菱电机株式会社 Method for manufacturing dielectric isolation type semiconductor device
JP2012033648A (en) * 2010-07-29 2012-02-16 Renesas Electronics Corp Semiconductor device
JP2013135233A (en) * 2011-12-22 2013-07-08 Samsung Electronics Co Ltd Semiconductor element and forming method thereof
CN109196634A (en) * 2016-06-10 2019-01-11 应用材料公司 In the seam restorative procedure crossed in atmospheric pressure technique in promoting diffusional environment
CN113764503A (en) * 2020-06-03 2021-12-07 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN116190241A (en) * 2023-04-24 2023-05-30 江西萨瑞半导体技术有限公司 LDMOS field effect transistor and preparation method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347565A (en) * 2004-06-03 2005-12-15 Fuji Electric Device Technology Co Ltd Semiconductor device and method for manufacturing the same
JP2006310513A (en) * 2005-04-28 2006-11-09 Fuji Electric Device Technology Co Ltd Semiconductor device and method of manufacturing the same
CN102244028A (en) * 2010-05-13 2011-11-16 三菱电机株式会社 Method for manufacturing dielectric isolation type semiconductor device
JP2011238868A (en) * 2010-05-13 2011-11-24 Mitsubishi Electric Corp Method of manufacturing dielectric separation type semiconductor device
JP2012033648A (en) * 2010-07-29 2012-02-16 Renesas Electronics Corp Semiconductor device
JP2013135233A (en) * 2011-12-22 2013-07-08 Samsung Electronics Co Ltd Semiconductor element and forming method thereof
CN109196634A (en) * 2016-06-10 2019-01-11 应用材料公司 In the seam restorative procedure crossed in atmospheric pressure technique in promoting diffusional environment
CN109196634B (en) * 2016-06-10 2023-08-29 应用材料公司 Method for repairing seam in process of accelerating diffusion environment under super-atmospheric pressure
CN113764503A (en) * 2020-06-03 2021-12-07 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN116190241A (en) * 2023-04-24 2023-05-30 江西萨瑞半导体技术有限公司 LDMOS field effect transistor and preparation method thereof

Also Published As

Publication number Publication date
JP4288925B2 (en) 2009-07-01

Similar Documents

Publication Publication Date Title
TWI754161B (en) A semiconductor-on-insulator (soi) substrate and method for forming the same
CN108565261B (en) Semiconductor device and method for manufacturing the same
JP6106310B2 (en) Hybrid active field gap extended drain MOS transistor
US8125044B2 (en) Semiconductor structure having a unidirectional and a bidirectional device and method of manufacture
JP4644577B2 (en) Semiconductor device and manufacturing method of semiconductor device
US8877606B2 (en) Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation
US9660055B2 (en) Method of manufacturing a semiconductor device with lateral FET cells and field plates
US7906388B2 (en) Semiconductor device and method for manufacture
US7919801B2 (en) RF power transistor structure and a method of forming the same
TWI442569B (en) Semiconductor devices containing trench mosfets with superjunctions
CN105321824B (en) Method for manufacturing semiconductor device
JP2004064063A (en) High voltage vertical type dmos transistor, and method for producing the same
US20150087128A1 (en) Method of manufacturing a semiconductor device that includes a misfet
TWI690025B (en) Semiconductor-on-insulator (soi)substrate, method for forming thereof, and integrated circuit
JP4933776B2 (en) Semiconductor device and manufacturing method thereof
TW200908319A (en) Junction field effect transistors in germanium and silicon-germanium alloys and method for making and using
US8133783B2 (en) Semiconductor device having different structures formed simultaneously
JP4288925B2 (en) Semiconductor device and manufacturing method thereof
JP4791723B2 (en) Semiconductor device and manufacturing method thereof
US20090152670A1 (en) Semiconductor device and method of fabricating the same
JP4088031B2 (en) Semiconductor device and manufacturing method thereof
JP2006156989A (en) Semiconductor device and method of manufacturing the same
KR100756709B1 (en) Manufacturing process of semiconductor device and semiconductor device
US20090140332A1 (en) Semiconductor device and method of fabricating the same
JP2004039985A (en) Semiconductor device and manufacturing method therefor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050517

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060703

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060704

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070723

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081120

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20081216

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090119

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090310

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090323

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120410

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120410

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120410

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120410

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120410

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120410

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130410

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140410

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees