JP2004152783A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can obtain excellent characteristics while the size of a platform is compacted, and to provide a method of manufacturing the device. <P>SOLUTION: This semiconductor device is provided with electric circuits including semiconductor elements (3, 4, and 6) on silicon substrates (1 and 11). In the semiconductor device, cavities (V) are formed in the substrates (1 and 11), and embedded wiring layers (10) provided on the internal wall surfaces of the cavities (V) are connected to the electric circuits. The embedded wiring layers (10) can be formed by utilizing the surface migration of silicon. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a semiconductor element is actually formed on a silicon substrate and a method of manufacturing the same.
[Prior art]
2. Description of the Related Art A semiconductor device in which a semiconductor element such as a light emitting element, a transistor, and a diode is mounted on a silicon substrate is used for various purposes as a so-called “semiconductor module”.
[0002]
For example, with the full-fledged introduction of optical subscriber systems, cost reduction of transmission equipment is required. Above all, cost reduction and high-speed transmission of optical modules have become major issues. As a structure of a semiconductor device that solves this problem, there is a “hybrid mounting type optical module” in which optical fibers, optical devices, and electronic components are hybridly arranged on a flat silicon substrate, and a packaging technology similar to that of a semiconductor is applied. Such a hybrid mounting type optical module is disclosed, for example, in Non-Patent Document 1.
[0003]
[Non-patent document 1]
IEICE Technical Report EMD2000-41, CPM2000-56, OPE2000-53, LQE2000-47 (2000-08)
pp. 1-6
[0004]
FIG. 10 is a schematic diagram illustrating a main part of a hybrid mounting type optical module studied by the inventor in the course of reaching the present invention. That is, FIG. 2A shows a main part housed inside the package of the hybrid mounting type optical module, where FIG. 2A is a plan view, FIG. 2B is a front view, and FIG. 1C is a side view.
[0005]
This specific example is an optical transmission module, and a light emitting element 3 such as a semiconductor laser is connected to a driving IC 6 via a chip resistor 7 and driven. The light output from the light emitting element 3 is coupled to the optical fiber 8 and sent out. In addition, a monitoring light receiving element 4 is provided behind the light emitting element 3 to monitor the light output of the light emitting element 3 to enable feedback control.
[0006]
The substrate 1 on which these optical fibers 8, optical devices such as the light emitting element 3 and the light receiving element 4 and electronic components are mounted is called a "platform" and is formed of silicon (Si) or the like.
[0007]
A groove 2 for fixing and holding an optical fiber 8 is formed in the silicon platform 1. The light emitting element 3 is arranged on the platform 1 so as to be optically coupled to an optical fiber 8 fixed and held in the groove 2. A high-frequency circuit pattern 9 for driving the light emitting element 3 is provided on the platform 1. The chip resistor 7 is connected to the high-frequency circuit pattern 9 and is connected to the light emitting element driving IC 6 by a wire. The light emitting element driving IC 6 is also connected to the high frequency circuit pattern 5 for connection to an external circuit by a wire. The light receiving element 4 for monitoring the optical power of the light emitting element 3 is connected to the bias voltage applying circuit pattern 10 by wires.
[0008]
[Problems to be solved by the invention]
For the high-frequency circuit patterns 5 and 9, it is necessary to form a microstrip line corresponding to the transmission speed so that the transmitted signal waveform does not deteriorate. However, when forming a high-frequency circuit on a limited platform, it is necessary to bypass other components and circuits. As a result, the circuit length of the circuit pattern becomes longer, or "bending" such as a crank occurs.
[0009]
If the circuit length becomes long and the transmission frequency cannot be matched, there arises a problem that the transmission signal deteriorates due to the phase delay of the response frequency. Also, if the high-frequency circuit has a "bend", the transmission signal is reflected at that portion, and the transmission signal also deteriorates.
[0010]
Such a problem similarly occurs not only in the optical transmission module but also in various semiconductor devices in which a semiconductor element, a circuit pattern, and the like are mounted on a silicon substrate. That is, it is not easy to arrange predetermined components on a silicon substrate while reducing the size of the semiconductor device, and in many cases, a trade-off between electrical or optical performance and size occurs.
[0011]
The present invention has been made based on the recognition of such problems, and an object of the present invention is to provide a semiconductor device capable of obtaining excellent characteristics while reducing the size of a platform and a method of manufacturing the same.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a first semiconductor device of the present invention is a semiconductor device in which an electric circuit including a semiconductor element is provided on a silicon substrate, wherein a cavity is formed inside the silicon substrate, A buried wiring layer provided on an inner wall surface of the cavity is connected to the electric circuit.
[0013]
According to the above configuration, by providing the embedded wiring layer, excellent characteristics can be obtained while reducing the size of the silicon substrate. In the case where a microstrip line or the like is provided on the surface of a silicon substrate, providing a cavity therebelow can increase the dielectric constant of that portion, so that the microstrip line can be miniaturized and a semiconductor device can be manufactured. The size can be further reduced.
[0014]
Further, a second semiconductor device of the present invention is a semiconductor device in which an electric circuit including a semiconductor element is provided on a silicon substrate, wherein a groove is formed in the silicon substrate, and a wiring layer is formed at the bottom of the groove. And forming a buried wiring layer formed inside the silicon substrate by heating and flowing silicon around the groove.
[0015]
According to the above configuration, a structure in which a wiring layer is embedded inside a silicon substrate can be obtained by utilizing “surface migration” of silicon. By providing such a buried wiring layer, excellent characteristics can be obtained while reducing the size of the silicon substrate.
[0016]
Further, a third semiconductor device of the present invention includes a silicon substrate, a semiconductor element mounted on the silicon substrate, a surface wiring layer formed on the silicon substrate, and a semiconductor device formed inside the silicon substrate. And a buried wiring layer provided on the inner wall surface of the cavity.
[0017]
Even with the above configuration, by providing the embedded wiring layer, excellent characteristics can be obtained while reducing the size of the silicon substrate. In the case where a microstrip line or the like is provided on the surface of a silicon substrate, providing a cavity therebelow can increase the dielectric constant of that portion, so that the microstrip line can be miniaturized and a semiconductor device can be manufactured. The size can be further reduced.
[0018]
Further, a fourth semiconductor device of the present invention includes a silicon substrate, a semiconductor light emitting element mounted on the silicon substrate, a surface wiring layer formed on the silicon substrate, and An optical fiber provided, a cavity formed inside the silicon substrate, and a buried wiring layer provided on an inner wall surface of the cavity are provided.
[0019]
Even with the above configuration, by providing the embedded wiring layer, excellent characteristics can be obtained while reducing the size of the silicon substrate. In the case where a microstrip line or the like is provided on the surface of a silicon substrate, providing a cavity therebelow can increase the dielectric constant of that portion, so that the microstrip line can be miniaturized and a semiconductor device can be manufactured. The size can be further reduced.
[0020]
In the third and fourth semiconductor devices, when at least a part of the cavity is formed below at least a part of the surface wiring layer, when a microstrip line or the like is provided as the surface wiring layer, By providing a cavity thereunder, the dielectric constant of that portion can be increased, so that the microstrip line can be miniaturized, and the size of the semiconductor device can be further reduced.
[0021]
In any of the above semiconductor devices, if a part of the buried wiring layer is exposed at the bottom of the opening formed in the silicon substrate, the connection can be reliably and easily secured.
[0022]
On the other hand, a method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device in which an electric circuit including a semiconductor element is provided on a silicon substrate, wherein a step of forming a groove in the silicon substrate, Forming a wiring layer on the bottom; and heating the silicon substrate to flow silicon to cover the groove and bury the wiring layer inside the silicon substrate. .
[0023]
According to the above configuration, the embedded wiring layer can be formed in the silicon substrate.
[0024]
Also. In the embedding step, the flow of the silicon may close the opening of the groove, and the lower part of the groove may remain inside the silicon substrate as a cavity including the wiring layer.
[0025]
In the embedding step, the upper surface of the wiring layer may be in a state of contacting the flowing silicon.
[0026]
The method may further include, after the embedding step, a step of forming a wiring layer such that at least a part of the wiring layer overlaps the silicon substrate above the cavity.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0028]
FIG. 1 is a schematic diagram illustrating a main part of a semiconductor device according to an embodiment of the present invention. That is, FIG. 1A shows a portion housed inside the package of the semiconductor device, FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional view near the center thereof.
[0029]
This specific example is a semiconductor device obtained by applying the present invention to the optical transmission module shown in FIG. In the present invention, the cavity V is formed inside the platform 1, and the circuit pattern 10 is provided at the bottom. By forming the circuit pattern inside the platform 1 in this manner, the number of components on the platform 1 can be reduced. As a result, it is easy to optimize the arrangement of parts or their shapes while reducing the size of the platform 1.
[0030]
In the case of the specific example of FIG. 1, since the surface of the platform 1 can have a margin by embedding the circuit pattern 10 in the platform 1, the circuit length of the high-frequency circuit patterns 5 and 9 is set to an optimal range, and the pattern is “bent”. And the like can be prevented, and the high-frequency characteristics can be improved.
[0031]
Furthermore, by forming the cavity V inside the platform 1, the dielectric constant of the substrate when designing a microstrip line provided thereon increases, and the size of the microstrip line can be reduced. .
[0032]
The structure of the semiconductor device of this example is described as follows.
[0033]
First, the light emitting element 3 such as a semiconductor laser is connected to the driving IC 6 via the chip resistor 7 and driven. The light output from the light emitting element 3 is coupled to the optical fiber 8 and sent out. In addition, a monitoring light receiving element 4 is provided behind the light emitting element 3 to monitor the light output of the light emitting element 3 to enable feedback control.
[0034]
On a platform 1 formed by processing a silicon substrate, a groove 2 for fixing and holding an optical fiber 8 is formed. The light emitting element 3 is arranged on the platform 1 so as to be optically coupled to an optical fiber 8 fixed and held in the groove 2. A high-frequency circuit pattern 9 for driving the light emitting element 3 is provided on the platform 1. The chip resistor 7 is connected to the high-frequency circuit pattern 9 and is connected to the light emitting element driving IC 6 by a wire. The light emitting element driving IC 6 is also connected to the high frequency circuit pattern 5 for connection to an external circuit by a wire.
[0035]
On the other hand, the circuit pattern 10 for applying a bias voltage is embedded in the platform 1 and is exposed at openings H1 and H2 provided at both ends thereof. One end of the circuit pattern 10 is connected to the light receiving element 4 by wire at the opening H1. On the other hand, the other end of the circuit pattern 10 is exposed at the opening H2 and can be connected to an external circuit (not shown).
[0036]
By embedding the circuit pattern 10 inside the platform 1 in this manner, the arrangement of other components on the surface of the platform 1 can be made appropriate. In other words, when forming the circuit patterns 5 and 9 of the drive circuit of the light emitting element 3 that requires high-speed modulation, it is not necessary to bypass other components, and it is formed with an optimum circuit length and with reduced “bending”. can do. As a result, in the driving circuit of the light emitting element 3, the problem of high frequency deterioration can be avoided, and a compact semiconductor device having excellent high-speed modulation characteristics can be provided.
[0037]
Next, a manufacturing method for embedding a circuit pattern inside the platform will be described. Such a buried structure can be formed by utilizing “surface migration” of silicon.
[0038]
2 and 3 are process diagrams showing a main part manufacturing process of the semiconductor device of FIG. That is, in these figures, (b), (d), and (f) are plan views of the platform 1 during the process, respectively, and (a), (c), and (e) are (d), (e), respectively. It is sectional drawing of the center vicinity in d) and (f).
[0039]
First, as shown in FIGS. 2A and 2B, a silicon nitride (SiNx) film 12 is formed to a thickness of about 200 nm on an insulating silicon (Si) substrate 11 having a step on the surface. . Then, a circuit groove 13 for forming the circuit pattern 10 is formed by a method such as dry etching.
[0040]
Next, as shown in FIGS. 2C and 2D, a circuit metal layer 14 is formed on the bottom of the circuit groove 13 by a vacuum deposition method or the like.
[0041]
Next, as shown in FIGS. 2E and 2F, the circuit metal layer 14 is embedded in the silicon substrate 11. Here, “surface migration” is used. That is, the silicon substrate 11 is placed in a hydrogen atmosphere and subjected to a heat treatment at about 1100 ° C. Then, the heat treatment causes surface diffusion of silicon atoms on the surface of the silicon substrate 11, and the surface diffusion causes deformation in a direction to minimize the surface energy. Therefore, the surface diffusion of silicon becomes remarkable at the portion where the radius of curvature is shortest. When the groove 13 is formed, the radius of curvature at the corner of the bottom of the groove 13 and the corner of the upper opening of the groove 13 is the shortest. The surface diffusion of silicon occurs such that the radius of curvature of these portions increases. When the groove 13 has a certain depth, surface diffusion near the groove lower portion and the upper opening occurs independently. Furthermore, since the metal layer 14 is formed at the bottom of the groove 13, surface migration of silicon atoms is suppressed.
[0042]
As a result, the surface migration in the upper opening of the groove 13 becomes remarkable, and the opening of the groove 13 is closed to form an isolated cavity V. As a document disclosing such “surface migration” of silicon, for example, Non-Patent Document 2 can be cited.
[0043]
[Non-patent document 2]
Applied Physics Vol. 69, No. 10, (2000) pp. 1187-1191
[0044]
FIG. 4 is a schematic diagram showing a state in which an isolated cavity is formed by surface migration of silicon. That is, when the trench T is formed on the surface of the silicon S and heated, the middle of the trench T gradually narrows due to the surface migration of the silicon. Then, the bottom of the trench remains as an isolated cavity V, and the vicinity of the opening of the trench is finally flattened by the inflow of silicon from the periphery.
[0045]
Such deformation due to surface migration of silicon occurs even when the bottom of the trench T is not covered with a foreign material such as a metal layer. However, in order to form the isolated cavity V, it is desirable that the aspect ratio of the trench T is large to some extent. That is, when the depth of the trench T with respect to the opening width is large to some extent, an isolated cavity V is easily formed.
[0046]
On the other hand, according to the present invention, the surface migration of silicon at the bottom of the groove 13 can be suppressed by providing the metal layer 14 at the bottom of the groove 13. As a result, the deformation of embedding the groove 13 becomes remarkable by giving priority to the migration of silicon above the groove 13. That is, in the present invention, by providing the metal layer 14 at the bottom of the groove 13, even when the aspect ratio of the groove 13 is not so large, it becomes easy to bury the groove 13 by migration of silicon. That is, even when the depth is not so large with respect to the width of the groove 13, the groove 13 can be buried by migration of silicon.
[0047]
As a result of the study by the present inventor, the metal layer 14 was formed in the silicon substrate 11 by performing a heat treatment at 1100 ° C. for several minutes to several tens of minutes in a vacuum or a hydrogen atmosphere having a pressure of about 1000 Pascal. Could be embedded.
[0048]
Further, it is desirable that the material of the metal layer 14 be one that withstands such heat treatment. For example, molybdenum (Mo), tantalum (Ta), tungsten (W), platinum (Pt), or the like has high heat resistance. Metals can be used. Further, a material which reacts with silicon to form silicide may be used.
[0049]
Now, returning to FIG. 3 and continuing the description, the circuit patterns 5, 9 and other circuit patterns are formed on the surface of the silicon substrate 11 as shown in FIGS. . Further, openings H1 and H2 are provided in the connection region of the circuit pattern 10 embedded in the substrate, and both ends of the circuit pattern 10 are exposed.
[0050]
Next, as shown in FIGS. 3C and 3D, the silicon nitride film 12 in the upper portion of the silicon substrate 11 is removed by patterning, and an etching solution having an etching rate dependent on a plane orientation with respect to a silicon crystal. By etching the silicon substrate 11, the groove 2 for fixing the optical fiber is formed.
[0051]
Then, as shown in FIGS. 3 (e) and 3 (f), the optical fiber 8, the light emitting element 3, the monitor light receiving element 4, the light emitting element driving IC 6, and the chip resistor 7 are installed at predetermined positions, respectively. Is connected with a wire or the like. Through the above steps, the main part of the semiconductor device is completed.
[0052]
Thus, in the present invention, the circuit pattern can be embedded inside the platform by utilizing the surface migration of silicon. As a result, the arrangement of components on the surface of the platform can be simplified, and the size of the semiconductor device can be reduced. Further, the wiring length of the high-frequency circuit pattern can be set to an optimum range, and "bending" of a crank or the like can be prevented to improve high-frequency characteristics.
[0053]
FIG. 5 is a schematic view showing a semiconductor device as another embodiment of the present invention. That is, FIG. 1A shows a portion housed inside the package of the semiconductor device, FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional view near the center thereof. In this figure, the same elements as those described above with reference to FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0054]
In this embodiment, the circuit pattern 10 is formed to extend below the circuit pattern 9. By doing so, the cavity V is provided below the circuit pattern 9, so that the macrostrip line as the circuit pattern 9 can be made fine. That is, by providing the cavity V below the microstrip line, the dielectric constant of that portion can be increased, so that the microstrip line can be miniaturized.
[0055]
In the present invention, when the groove 13 is formed shallowly, the cavity V may hardly be formed.
[0056]
FIG. 6 is a schematic cross-sectional view illustrating a structure obtained when the groove 13 is formed shallowly. As described above, when the depth is smaller than the width of the groove 13, migration of silicon occurs so as to cover the metal layer 14 at the bottom, and the metal layer 14 is hardly formed in the silicon without forming a cavity. It may be embedded. Also in this case, it is possible to reduce the number of components provided on the surface of the platform, to achieve compactness and to optimize the circuit pattern.
[0057]
FIG. 7 is a schematic diagram of a semiconductor device as another embodiment of the present invention. That is, FIG. 1A shows a portion housed inside the package of the semiconductor device, FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional view near the center thereof. In this figure, the same elements as those described above with reference to FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0058]
Also in this embodiment, the circuit pattern 10 is formed at the bottom of the cavity V formed inside the platform 1. Then, the circuit patterns 5 and 9 are connected to the driving IC 6 provided thereon without passing through wires. In this way, it is possible to prevent high-frequency characteristics from deteriorating due to the parasitic inductance of the bonding wires and the like. FIGS. 8 and 9 are process diagrams showing a main part manufacturing process of the semiconductor device of this embodiment. That is, in these figures, (b), (d), (f), and (h) are plan views of the platform 1 during the process, respectively, and (a), (c), (e), and (g). FIGS. 3A and 3B are cross-sectional views near the center in (d), (d), (f) and (h), respectively.
[0059]
7 and 8, the description of the same steps as those described above with reference to FIGS. 2 and 3 will be omitted.
[0060]
In the case of this specific example, in the process shown in FIGS. 8G and 8H, after the metal layer 14 is embedded in the substrate 11 by surface migration of silicon, for example, by molecular beam epitaxy. Then, a driving IC 6 is formed by sequentially epitaxially growing a GaAs-based material 15 on the silicon substrate 11. As described above, the driving IC may be directly formed on the silicon substrate 11.
[0061]
The embodiment of the invention has been described with reference to the examples. However, the present invention is not limited to these specific examples.
[0062]
For example, the semiconductor device of the present invention is not limited to a device using an optical semiconductor element, but is a heterojunction bipolar transistor (HBT), a high electron mobility transistor (HEMT), or various types of transistors such as an IGBT (insulated gate transistor). A similar effect can be obtained by applying the same to a semiconductor device using a semiconductor element such as a diode.
[0063]
That is, a semiconductor device in which a semiconductor element is mounted on a silicon substrate, which has a wiring having the features of the present invention in the silicon substrate, and a semiconductor device whose design has been appropriately changed by those skilled in the art. Included in the scope of the invention.
【The invention's effect】
As described in detail above, according to the present invention, a circuit pattern can be embedded inside a platform by utilizing surface migration of silicon. As a result, the arrangement of components on the surface of the platform can be simplified, and the size of the semiconductor device can be reduced. Further, when forming a high-frequency circuit pattern or the like, it is possible to improve the high-frequency characteristics by setting the wiring length to an optimum range and preventing "bending" of a crank or the like.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating a main part of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a process chart showing a main part manufacturing process of the semiconductor device of FIG. 1;
FIG. 3 is a process chart showing a main part manufacturing process of the semiconductor device of FIG. 1;
FIG. 4 is a schematic view showing a state where an isolated cavity is formed by surface migration of silicon.
FIG. 5 is a schematic view showing a semiconductor device as another embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view illustrating a structure obtained when a groove 13 is formed shallowly.
FIG. 7 is a schematic diagram of a semiconductor device as another embodiment of the present invention.
8 is a process chart showing a main part manufacturing process of the semiconductor device of FIG. 7;
FIG. 9 is a process chart showing a main part manufacturing process of the semiconductor device of FIG. 7;
FIG. 10 is a schematic diagram showing a main part of a hybrid mounting type optical module studied by the inventor in the course of reaching the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon platform 3 Light emitting element 4 Light receiving element for monitoring 5 High frequency circuit pattern 7 Chip resistor 8 Optical fiber 9 High frequency circuit pattern 10 Bias voltage application circuit pattern 11 Silicon substrate 12 Silicon nitride film 13 Circuit groove 14 Metal layer H1, H2 opening S Silicon T Trench V Cavity

Claims (10)

A semiconductor device in which an electric circuit including a semiconductor element is provided on a silicon substrate,
A semiconductor device, wherein a cavity is formed inside the silicon substrate, and a buried wiring layer provided on an inner wall surface of the cavity is connected to the electric circuit. A semiconductor device in which an electric circuit including a semiconductor element is provided on a silicon substrate,
A buried wiring layer formed inside the silicon substrate by forming a groove in the silicon substrate and forming a wiring layer at the bottom of the groove and then heating and flowing silicon around the groove; A semiconductor device characterized by the above-mentioned. A silicon substrate,
A semiconductor element mounted on the silicon substrate,
A surface wiring layer formed on the silicon substrate,
A cavity formed inside the silicon substrate,
A buried wiring layer provided on the inner wall surface of the cavity,
A semiconductor device comprising: A silicon substrate,
A semiconductor light emitting device mounted on the silicon substrate,
A surface wiring layer formed on the silicon substrate,
An optical fiber provided on the silicon substrate,
A cavity formed inside the silicon substrate,
A buried wiring layer provided on the inner wall surface of the cavity,
A semiconductor device comprising: 5. The semiconductor device according to claim 3, wherein at least a part of the cavity is formed below at least a part of the surface wiring layer. The semiconductor device according to claim 1, wherein a part of the buried wiring layer is exposed at a bottom of an opening formed in the silicon substrate. A method for manufacturing a semiconductor device in which an electric circuit including a semiconductor element is provided on a silicon substrate,
Forming a groove in the silicon substrate;
Forming a wiring layer at the bottom of the groove;
Heating the silicon substrate and flowing the silicon to cover the groove and bury the wiring layer inside the silicon substrate;
A method for manufacturing a semiconductor device, comprising: 8. The method according to claim 7, wherein, in the embedding step, an opening of the groove is closed by the flow of the silicon, and a lower portion of the groove remains inside the silicon substrate as a cavity including the wiring layer. The method according to claim 7, wherein in the embedding step, an upper surface of the wiring layer is brought into contact with the flowing silicon. The method of manufacturing a semiconductor device according to claim 1, further comprising, after the embedding step, a step of forming a wiring layer so that at least a part of the wiring layer overlaps the silicon substrate above the cavity.

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