JP2004152277A - Start time shortening arithmetic unit and data loading method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a time required for a starting process, in an arithmetic unit provided with a CPU, a cache, a RAM and a ROM. <P>SOLUTION: This arithmetic unit is provided with a switching device 16 and a cache operation device 19. The switching device 16 determines whether or not desired data which the CPU 11 intends to read are present in the RAM 14, and makes the CPU 11 directly read the desired data from the ROM 13. A cache operation device 19 operates the cache 12 so as to initialize the RAM 14 based on cache data corresponding to desired data stored in the cache 12. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a startup time reduction arithmetic device, and more particularly, to a data load process of an arithmetic device having a central processing unit (CPU).

  Conventionally, in an arithmetic device having a CPU, a cache, a RAM, and a ROM, access to desired data by the CPU is performed by reading from the cache if the cache has the desired data, and storing the desired data in the RAM instead of the cache. In some cases, this is done by reading data from RAM. If there is no desired data in both the cache and the RAM, the desired data is copied from the ROM to the RAM, and then the data is read from the RAM by the CPU (for example, see Patent Document 1).

  FIG. 3 shows a flow of the startup processing of the operation system (OS).

  When the power is turned on and the system startup process is started (S101), the CPU presents an address corresponding to the desired data to read the data (S102), and determines whether the data is in the cache or the RAM. , And RAM sequentially (S103, S105). If there is desired data in the cache, it is read from the cache (S104). If the desired data is not in the cache but is in the RAM, it is read from the RAM (S108).

If there is no desired data in the cache or the RAM, the CPU starts copying necessary data (including at least the desired data) from the ROM to the RAM (S106), and waits for completion of the copy. (S107). Then, after the copy is completed, the desired data is read from the RAM (S108). Then, the CPU processes the read data (S109).
JP-A-05-242057 (page 2, FIG. 1)

  By the way, since data does not remain in the volatile memory such as the cache and the RAM at the time of the start-up process, in the conventional system, the RAM is initialized by always copying the data of the ROM to the RAM at the time of the start-up. This means that data necessary for the start-up process is written to the RAM.) Then, after the initialization of the RAM, the CPU needs to read data necessary for the start-up process from the RAM and perform the start-up process. Therefore, in the conventional system, the CPU cannot proceed with the start-up process until the copying of data from the ROM to the RAM is completed. As a result, the start-up process requires a lot of time.

  It is conceivable to temporarily save the data in the RAM to the non-volatile memory at the time of suspending, and then write the data back to the RAM at the time of returning from the suspend mode. appear. In other words, until the data saved in the nonvolatile memory is written back to the RAM, the processing of the CPU using this data cannot be executed.

  Accordingly, it is an object of the present invention to reduce the time required for a startup process and a return process from a suspend in an arithmetic device including a CPU, a cache, a RAM, and a nonvolatile memory.

  In order to solve this problem, the present invention provides a startup time reduction arithmetic device including a determination unit, a switching device, and a cache operation device. The determination means is a means for determining whether desired data to be read by the CPU exists in the RAM. The switching device is a device that causes the CPU to directly read desired data from the non-volatile memory in accordance with the result of the determination by the determination unit. The cache operation device is a device that initializes a RAM based on cache data corresponding to desired data stored in a cache.

  According to the present invention as described above, at the time of startup or at the time of return from suspend, the CPU does not need to wait for the completion of copying data from the nonvolatile memory to the RAM, and does not need to wait for the startup from the nonvolatile memory. Processing can be started immediately after data is acquired directly. Therefore, the time required for the startup processing and the return processing from the suspend is reduced.

  Further, since the RAM is initialized based on the cache data corresponding to the data read directly from the non-volatile memory by the CPU, the load time when the data directly read from the non-volatile memory is accessed again. Is shortened. Therefore, it is possible to reduce the time required for the start-up process and the process of returning from the suspend, and also to shorten the process following these processes.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 1 is a block diagram showing a configuration of an arithmetic unit according to one embodiment of the present invention. The arithmetic device includes a CPU 11, a cache 12, a ROM 13, a RAM 14, a switching device 16, and a cache operation device 19. Each component is mutually connected via a bus or the like.

  First, the role of each component at the time of startup will be described.

  The CPU 11 accesses the data for the activation process to execute the activation process. This access is performed by issuing an address of the RAM 14.

  The cache 12 is a volatile memory in which data held by turning off the power is lost. The cache 12 generally has a smaller storage capacity than the RAM 14, but has a higher access speed than the RAM 14. Data read by the CPU 11 from the RAM 14 or the like is temporarily stored in the cache 12, and the CPU first accesses the cache when trying to acquire data.

  The cache 12 holds a cache tag 17 corresponding to cache data that is temporarily held data. The cache tag 17 includes a dirty bit indicating whether or not the cache data has been updated. When data at a certain address on the RAM 14 is held as cache data in the cache 12, the address on the RAM 14 is stored in the cache tag 17 corresponding to the cache data. When the cache data is updated by the CPU 11, the dirty bit 18 of the cache tag 17 corresponding to the cache data is set to "dirty". When replacing the data in the cache 12, it is necessary to reflect the update made to the cache data to the original data in the RAM 14. Therefore, the CPU 11 rewrites the data of the address of the RAM 14 held in the cache tag 17 with the cache data in which the dirty bit 18 is set to “dirty”.

  Although the access speed of the ROM 13 is lower than that of the RAM 14, the ROM 13 is a nonvolatile memory capable of holding data even when the power is turned off. In the present embodiment, the data necessary for the start-up processing held in the ROM 13 is directly supplied to the CPU 11 without being once copied to the RAM 14 by the operation of the switching device 16 described later.

  The RAM 14 is a volatile memory that loses data stored when the power is turned off, and generally has a larger storage capacity than the cache 12. The access speed is lower than that of the cache 12 and higher than that of the ROM 13. When the CPU 11 operates data, a part of the data is copied from the ROM 13 having the slowest access speed to the RAM 14, and the CPU 11 accesses the data copied to the RAM 14. When the system is started, data is not held in the RAM 14, so that the RAM 14 needs to be initialized (data necessary for the start processing is written in the RAM), and data necessary for the start processing is copied from the ROM 13 to the RAM 14. Is done.

  The RAM data determination bit table 15 is a table stored in the RAM 14 to determine whether data is stored in the RAM 14. One bit of the RAM data determination bit table 15 (hereinafter referred to as RAM data determination bit) corresponds to every 32 bytes of the storage area of the RAM 14. When data is not stored in the corresponding storage area of the RAM 14, the RAM data determination bit is "0", but is changed to "1" when the data is written. When the system is started, no data is held in the RAM 14, so that all bits of the RAM data determination bit table 15 are "0". By referring to the RAM data determination bit table 15, it is possible to instantaneously determine whether data is held in the RAM 14.

  When the CPU 11 attempts to access a predetermined address of the RAM 14, the switching device 16 refers to the RAM data determination bit table 15 to determine whether data exists at the address of the RAM 14 specified by the CPU 11. If the data exists, the CPU 11 causes the CPU 11 to read the data from the RAM 14. If the data does not exist, the CPU 11 causes the CPU 11 to directly read the data corresponding to the address of the RAM 14 specified by the CPU 11 from the ROM 13. At this time, if the address of the RAM 14 specified by the CPU 11 is not the same as the address of the ROM 13 storing the data corresponding to this address, the switching device 16 sets the ROM 13 corresponding to the address of the RAM 14 specified by the CPU 11. And the CPU 11 may access the address of the ROM 13. Data read directly from the ROM 13 by the CPU 11 is temporarily stored in the cache 12.

  The cache operation device 19 operates the cache tag 17 of the cache 12 in response to the switching device 16 causing the CPU 11 to read data directly from the ROM 13. More specifically, the CPU 11 registers the address of the RAM 14 to which the CPU 11 should have originally accessed in the cache tag 17, and sets the dirty bit 18 to "dirty". The initialization of the RAM 14 is realized by the function of the cache operation device 19 and the mechanism of the cache 12.

  The principle of initialization of the RAM 14 in the present embodiment will be described in more detail. In the conventional system, the initialization of the RAM 14 is performed by copying data necessary for the startup process from the ROM 13 to the RAM 14. On the other hand, in the present embodiment, the data necessary for the start-up process is read directly from the ROM 13 by the CPU 11, so that the RAM 14 is not initialized during the start-up process. By the way, according to the existing cache mechanism, when the cache data is updated, the dirty bit corresponding to the cache data is set to “dirty”, and when the cache is replaced, the dirty bit is set to “dirty”. The cached data overwrites the original data stored in the RAM with the cached data. Thus, in the present embodiment, the initialization of the RAM 14 is realized by the cache operating device 19 operating the cache tag 17 as described above, thereby effectively utilizing the existing cache mechanism. That is, in the present embodiment, the data directly read from the ROM 13 by the CPU 11 is temporarily stored in the cache 12, and then all the data is stored at the original address of the RAM 14 regardless of whether or not the data has been updated. Thus, the initialization of the RAM 14 is performed.

  Next, the operation of the arithmetic device at the time of startup will be described with reference to the flowchart shown in FIG.

  When the power is turned on and the system startup process starts (S201), the CPU 11 presents an address corresponding to the desired data to read the data (S202), and determines whether or not the data exists in the cache 12 (S202). S203). If there is data in the cache 12, the CPU 11 reads it (S204), but there is no data in the cache 12 at startup. Then, in response to the CPU 11 trying to access a predetermined address in the RAM 14, the switching device 16 refers to the RAM data determination bit table 15 to determine whether or not data exists at that address in the RAM 14 ( S205). If there is data in the RAM 14, the CPU 11 reads it (S206), but there is no data in the RAM 14 at the time of startup. Therefore, the switching device 16 causes the CPU 11 to read data directly from the ROM 13 (S207). Since the data read at this time is held in the cache 12 as cache data, the cache operation device 19 operates the cache tag 17 corresponding to the cache data held in the cache 12 (S208). Then, the CPU 11 processes the read data (S209).

  As described above, according to the present embodiment, at the time of system startup processing, the processing of copying data in ROM 13 to RAM 14 can be omitted and CPU 11 can start the startup processing, so that the startup time is reduced. . Further, since the data read directly from the ROM 13 by the CPU 11 is temporarily stored in the cache 12 and then stored at the original address of the RAM 14, the RAM 14 is also initialized and the access speed of the data after the start-up processing is improved. I do.

  In the above description, the operation of the arithmetic device at the time of starting the system immediately after the power is turned on has been described. However, the present invention can be similarly applied to the start of the application program and the return processing from the suspend. . Also in this case, since the process of copying the data in the nonvolatile memory to the RAM 14 is omitted, the startup time of the application program and the time of returning from the suspend can be reduced. When the application is started, it is desirable that the RAM data determination bit table 15 corresponding to the area of the RAM 14 to which the data of the application should be loaded be cleared in advance.

  In the present embodiment, the CPU 11 performs the start-up process using the data stored in the ROM 13. However, the present invention is not limited to the ROM 13, and the present invention uses the data stored in an arbitrary nonvolatile memory. This is applicable when the CPU 11 performs the startup processing. For example, a similar effect can be obtained by applying the present invention even when the CPU 11 starts an application program stored in a memory card.

  In this embodiment, the switching device 16 determines whether or not the data to be read by the CPU 11 exists in the RAM 14. However, the present invention is not limited to this, and the data to be read by the CPU 11 exists in the RAM 14. A unit for determining whether or not the switching device 16 may be provided separately from the switching device 16. Further, the means for determining whether or not the data to be read by the CPU 11 exists in the RAM 14 may be the CPU 11.

  In the present embodiment, the switching device 16 refers to the RAM data determination bit table 15 to determine whether or not the data to be read by the CPU 11 exists in the RAM 14. However, the switching device 16 performs the determination by other methods. It does not matter. For example, a one-bit flag indicating whether any data has been written to any area of the RAM 14 may be prepared, and whether or not data exists in the RAM 14 may be determined by referring to this flag. Further, the CPU 11 may actually access the storage area of the RAM 14 to determine whether data exists.

  Further, in the present embodiment, the cache operating device 19 realizes the initialization of the RAM 14 by operating the dirty bit 18 of the cache tag 17, but the present invention is not limited to this, and for example, the cache data is replaced. Sometimes, the cache operation device 19 may write all the cache data deleted from the cache 12 to the RAM 14.

  In the present embodiment, the RAM data determination bit table 15 is stored in the RAM 14, but the RAM data determination bit table 15 may be stored in any storage device other than the RAM 14.

  Further, the switching device 16 may be realized by causing the CPU 11 to execute a program for causing the CPU 11 to function as the switching device 16, or a part or all of the functions may be realized by hardware. The same applies to the cache operation device 19.

  According to the present invention, it is possible to provide an arithmetic device in which startup processing and recovery processing from suspend are fast.

FIG. 1 is a block diagram showing a configuration of an arithmetic unit according to an embodiment of the present invention. 4 is a flowchart illustrating the operation of the arithmetic device according to the embodiment of the present invention. Flow chart showing the operation of a conventional system

Explanation of reference numerals

11 CPU
12 cache 13 ROM
14 RAM
15 RAM data determination bit table 16 Switching device 17 Cache tag 18 Dirty bit 19 Cache operating device

Claims (7)

An arithmetic device including a CPU, a cache, a RAM, and a nonvolatile memory,
Determining means for determining whether or not the data to be read by the CPU exists in the RAM;
A switching device that reads the data directly from the non-volatile memory to the CPU according to a determination result of the determination unit;
A cache operation device for operating the cache such that the RAM is initialized based on cache data corresponding to the data stored in the cache;   2. The startup time reduction arithmetic device according to claim 1, wherein the determination unit has a function of performing the determination with reference to a RAM data determination bit table that holds presence / absence of data in the RAM.   2. The startup time reduction arithmetic device according to claim 1, wherein the switching device has a function of determining an address in the nonvolatile memory corresponding to the data when the data does not exist in the RAM.   The activation according to claim 1, wherein the cache operation device has a function of setting dirty bits of all cache tags corresponding to the cache data to dirty when the data is stored in the cache as cache data. Time reduction arithmetic unit.   The cache operating device has a function of, when the data is stored in the cache as cache data, writing a RAM address corresponding to the cache data to a cache tag corresponding to the cache data. The start-up time reduction arithmetic device according to claim 1.   The startup time reduction arithmetic device according to claim 1, wherein the nonvolatile memory is a ROM. A method for loading data in an arithmetic device including a CPU, a cache, a RAM, and a nonvolatile memory,
A step of determining whether the data to be read by the CPU exists in the RAM;
Causing the CPU to read the data directly from the non-volatile memory according to the determination result;
Operating the cache such that the RAM is initialized based on cache data corresponding to the data stored in the cache when read directly from the non-volatile memory to the CPU. Data loading method.

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