JP2004147170A - Bit error rate calculation unit and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve estimated accuracy of bit error rate, regarding an error-correction coded receiving signal. <P>SOLUTION: A bit error rate calculation section 30 calculates the bit error rate of a coded signal received by a communication system, that transmits the coded signal containing information bit and redundant bit, where predetermined process has been applied to the information bit. The bit error rate calculating section 30 is capable of switching which bit comparison result between an information bit rXi, reXi and a redundant bit rYij, reYij is to be used. Since the comparison result of an appropriate bit can be used according to circumstances, the detection accuracy of the bit error rate can be improved. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an apparatus and a method for calculating a bit error rate of a received encoded signal in a communication system that transmits an encoded signal encoded in a predetermined format.
[0002]
[Prior art]
As a method of calculating the bit error rate of a received encoded signal, a method of comparing a received encoded signal with a re-encoded signal obtained by decoding the received encoded signal and re-encoding the decoded signal is known. Are known. When performing error correction encoding using a systematic code such as a turbo code, the encoded signal and the re-encoded signal each include an information bit and a redundant bit obtained by performing interleaving or convolutional encoding on the information bit. , Is included. Then, the bit error rate is calculated based on the result of comparison between information bits and redundant bits included in the coded signal and the re-coded signal, respectively.
[0003]
However, in the case of this method, there is a problem that the scale of the circuit for calculating the bit error rate becomes large as much as the re-encoding is performed. Therefore, there has been proposed a method of estimating a bit error rate by comparing information bits included in a received coded signal with information bits included in decoded data (see Patent Document 1). . In this method, since the comparison of the redundant bits is not performed, a circuit for re-encoding becomes unnecessary, and the circuit scale can be reduced as compared with the case of the above-described method.
[0004]
[Patent Document 1]
JP 2001-333050 A
[Problems to be solved by the invention]
However, in the method disclosed in Patent Document 1, since the bit error rate is estimated based only on the comparison result of the information bits, there is a problem that the estimation accuracy of the bit error rate is low because the comparison result of the redundant bits is not used. .
[0006]
Nevertheless, errors included in redundant bits may be propagated in re-encoding processing including recursive processing such as convolutional coding, so that it is desirable to always use the result of comparison of redundant bits. Absent.
[0007]
[Means for Solving the Problems]
A bit error rate calculation device according to the present invention calculates a bit error rate of a coded signal received in a communication system that transmits a coded signal including information bits and redundant bits obtained by subjecting the information bits to predetermined processing. A decoding unit for decoding a received encoded signal to obtain decoded information bits, and a re-encoding unit for encoding the decoded information bits to generate a re-encoded signal And a bit error rate calculation unit that calculates a bit error rate based on a comparison result between the received coded signal and the re-encoded signal, and calculates the bit error rate in the bit error rate calculation unit. It is possible to freely switch which bit of the information bit and the redundant bit is used for the comparison result.
[0008]
According to such a configuration, a bit comparison result suitable for a situation can be used, so that the detection accuracy of the bit error rate can be improved.
[0009]
Further, the bit error rate calculation device according to the present invention further includes an error detection unit that performs error detection of the decoded information bits, and the bit error rate calculation unit based on an error detection result in the error detection unit. It is preferable to switch which bit of the information bit and the redundant bit is used in the calculation of the bit error rate in.
[0010]
Further, in the bit error rate calculation device according to the present invention, the bit error rate calculation unit calculates the bit error rate using the comparison result of only the information bits, and the comparison result of the information bits and the redundant bits. It is preferable to switch between when the bit error rate is calculated using
[0011]
In the bit error rate calculation device according to the present invention, the coded signal transmitted in the communication system includes n types (n: an integer of 2 or more) of redundant bits, and the re-encoding processing unit performs It is preferable to generate a re-encoded signal including redundant bits of a type (m: an integer of 1 or more, m <n).
[0012]
Further, in the bit error rate calculation device according to the present invention, the coded signal transmitted in the communication system is a turbo-coded bit sequence, that is, information bits and redundant bits for performing convolutional coding without interleaving the information bits. Bits and redundant bits that interleave and convolutionally code the information bits. The main factor of the circuit size of the re-encoding circuit is the interleave circuit. When calculating the bit error rate by using information bits and one type (m = 1) of redundant bits, the re-encoding processing unit performs decoding information decoding. It is preferable to generate a re-encoded signal that includes the redundant bits for convolutionally encoding the bits without interleaving and does not include the redundant bits for interleaving and convolutionally encoding the decoded information bits.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG. (FIGS. 1 to 3) FIG. 1 is a block diagram illustrating an example of an encoding processing unit 10 that generates an encoded signal by performing error correction encoding processing on information bits using a systematic code, and FIG. FIG. 3 is a block diagram illustrating an example of a bit error rate calculation unit 30 included in the receiving device 20.
[0014]
An encoding processing unit 10 provided in a transmission device (not shown) of the communication system performs an error correction encoding process on information bits forming communication data to generate an encoded signal. In the example of FIG. 1, the information bits Xi (i = 1, 2,...) Are converted into information bits Xi and n redundant bits Yij (j = 0, 1, 2,. .., N−1; n ≧ 2). Each of the redundant bits Yij is obtained by convolutionally encoding the information bit Xi by the convolutional encoding unit 14-0 (Yi0), or an interleaver 12-j (j = 1, 2,..., N-1; n). .Gtoreq.2), and then convolutionally coded by the convolutional coding unit 14-j (j = 0, 1, 2,..., N-1; n.gtoreq.2). Thus, (Yi1 to Yin-1) are generated. The information bits Xi and the generated redundant bits Yij are input to a parallel / serial converter (P / S converter) 16 and are converted into serial signals. Specifically, the information bits Xi and the redundant bits Yij are, for example, “X1, Y10, Y11, Y12,..., Y1n-1, X2, Y20, Y21, Y22,. ,... Are generated. Then, the generated encoded signal is transmitted to the receiving device after being modulated in a predetermined format.
[0015]
As shown in FIG. 2, the receiving device 20 includes a demodulation processing unit 22 that demodulates a received encoded signal, and a decoding processing unit 24 that decodes the demodulated encoded signal to obtain decoded information bits. And a bit error rate calculation unit 30 that obtains a bit error rate of the received encoded signal.
[0016]
The bit error rate calculation unit 30 performs the same encoding process as that performed at the time of transmitting each bit of the encoded signal demodulated by the demodulation processing unit 22 and the decoded information bits acquired by the decoding processing unit 24 at the time of transmission. The bit error rate is obtained based on the result of comparing each bit of the re-encoded signal re-encoded by the corresponding bits with each other. Here, the bit error rate is defined as the bit error rate of the total number of bits (the number of sample bits) for which the bit error has occurred if the corresponding two bits do not match. It is calculated as a ratio of numbers.
[0017]
FIG. 3 is a diagram illustrating an example of the bit error rate calculation unit 30 provided in the reception device 20 of FIG. As described above, the re-encoded signal is generated by re-encoding the decoded information bits by the same encoding process as that performed at the time of transmission. Therefore, in the example of FIG. 3, the circuit that generates the re-encoded signal from the decoded information bits includes the same interleaver 12-j and convolutional encoder 14-j as in FIG. 1 with the same circuit configuration as in FIG. I have. With this circuit, information bits reXi and redundant bits reYij (i = 1, 2,..., J = 0, 1, 2,..., N−1; n ≧ 2) of the re-encoded signal are obtained. You.
[0018]
On the other hand, the demodulated coded signal is input to a serial / parallel converter (S / P converter) 36, where an information bit rXi and a redundant bit rYij (i = 1, 2,..., J = 0, 1) , 2,..., N−1; n ≧ 2).
[0019]
Then, the information bits reXi and redundant bits reYij of the re-coded signal and the information bits rXi and redundant bits rYij of the coded signal correspond to the corresponding bit comparison units 38-p (one) and 38-j (j = 0), respectively. , 1, 2,..., N−1; n ≧ 2, that is, n total). The bit comparing unit 38-p compares the information bits reXi and rXi, and the bit comparing unit 38-j compares the redundant bits reYij and rYij to detect a match / mismatch thereof.
[0020]
The number of times that the bits did not match in each bit comparing unit 38-p, 38-j, that is, the number of mismatched bits (the number of bits in which an error occurred) is determined by the counter 40-p for each bit comparing unit 38-p, 38-j. p, 40-j (j = 0, 1, 2,..., n−1; n ≧ 2), and the switches 42-p, 42-j (j = 0, 1, 2,. , N−1; n ≧ 2). The arithmetic unit 44 obtains the bit error rate by dividing the input number of mismatched bits by the total number of bits to be measured.
[0021]
In the present embodiment, switches 42-p and 42-j are provided between the counters 40-p and 40-j and the arithmetic unit 44, and the ON / OFF of the switches 42-p and 42-j is controlled to calculate the bit error rate. The source information bits or redundant bits can be switched. In the example of FIG. 3, the error detection unit 46 obtains an error detection result of a CRC (Cyclic Redundancy Check) code included in the decoded information bit group, and the switching control unit 48 switches the switch 42-based on the error detection result. ON / OFF of p, 42-j is switched. Specifically, for example, when no error is detected by the error detection unit 46, the switching control unit 48 turns on all the switches 42-p and 42-j. In this case, the bit error rate is calculated based on the comparison result of the information bits rXi and reXi and the comparison result of all the redundant bits rYij and reYij. On the other hand, when the error detection unit 46 detects an error, the switching control unit 48 turns ON only the switch 42-p and turns OFF the other switches. In this case, the bit error rate is calculated based on only the comparison result of the information bits rXi, reXi. That is, when an error is detected, the comparison result based on the redundant bit reYij generated by a circuit including recursive processing (for example, the convolutional encoder 14-j) in which the error propagates is not used. The error rate estimation accuracy can be improved. Further, even when no error is detected, it is possible to improve the accuracy of estimating the bit error rate by increasing the number from which the bit error rate is obtained. Note that which bit of the information bit or the redundant bit to use for the comparison result is not limited to the above example, and can be arbitrarily set according to the situation.
[0022]
Embodiment 2 FIG. (FIG. 4) FIG. 4 is a block diagram illustrating an example of the bit error rate calculation unit 30a according to the present embodiment. This bit error rate calculation section 30a can be used in place of bit error rate calculation section 30 in receiving apparatus 20 of FIG. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and redundant description will be omitted.
[0023]
As shown in FIG. 4, in the bit error rate calculation unit 30a, the re-encoded signal generated from the decoded information bits only includes the information bits reXi and the redundant bits reYi0, and the other redundant bits reYij (j = 1, 2,..., N−1; total n−1). As described above, by reducing the number of redundant bits (1 in the example of FIG. 4) generated as a re-encoded signal to be smaller than the number of redundant bits generated at the time of encoding in the transmitting apparatus (also n), The circuit scale for encoding can be reduced, and the bit error rate calculator 30a and, consequently, the receiver 20 including the same can be reduced in size and weight.
[0024]
In addition, the bit error rate calculation unit 30a in FIG. 4 determines whether or not to use the comparison result of the redundant bits reYi0 and rYi0 generated by performing only convolutional coding without performing interleave processing in calculating the bit error rate. Switch. Specifically, a switch 42-0 is provided only between the counter 40-0 and the operation unit 44, and when no error is detected in the error detection unit 46, the switching control unit 48 switches the switch 42-0. Is turned ON. In this case, the bit error rate is based on the comparison result between the information bit rXi of the coded signal and the information bit reXi of the recoded signal and the comparison result between the redundant bit rYi0 of the coded signal and the information bit reYi0 of the recoded signal. It is calculated based on: On the other hand, when the error detection unit 46 detects an error, the switching control unit 48 turns off the switch 42-0. In this case, the bit error rate is calculated based on a comparison result between the information bit rXi of the coded signal and the information bit reXi of the re-coded signal. This scheme is particularly effective in the case of a two-dimensional turbo code (that is, one redundant bit for performing only convolutional coding after interleaving one redundant bit for performing only convolutional coding). In a two-dimensional turbo code, if the bit error rate is calculated only from the result of comparing information bits as in the conventional device disclosed in Patent Document 1, the number of sample bits from which the bit error rate is calculated is the total number of bits. Therefore, there is a case where sufficient accuracy cannot be secured. On the other hand, according to the present embodiment, the number of sample bits is 2/3 of the total number of bits, and the increase in circuit size is suppressed by not using an interleaver, which is a main factor of the increase in circuit size in the re-encoding circuit. Thus, the accuracy of estimating the bit error rate can be improved as compared with the related art. When an error is detected, the redundant bit Yi0 obtained through the convolutional encoder 14-0 is not used for calculating the bit error rate. It is possible to suppress a decrease in the accuracy of rate estimation.
[0025]
The preferred embodiment of the present invention has been described above, but the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, the switches 42-p and 42-j are switched based on the CRC detection result. However, the switches may be switched according to other parameters, or may be switched automatically or manually according to the condition of the transmission path. It may be. Also, instead of providing a switch, the arithmetic unit inputs all the comparison results of the information bits and the redundant bits, and based on an instruction from the switching control unit, uses any of the input comparison results to The calculation unit may select whether to calculate the error rate. Further, the present invention is similarly applicable to systematic codes other than turbo codes.
[0026]
【The invention's effect】
As described above, according to the present invention, a bit comparison result suitable for a situation can be used, so that a more accurate bit error rate can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of an encoding processing circuit.
FIG. 2 is a diagram illustrating an example of a configuration of a receiving device including a bit error rate calculation unit according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of a bit error rate calculation unit according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of a bit error rate calculation unit according to a second embodiment of the present invention.
[Explanation of symbols]
10 coding processing unit, 12-j (j = 1, 2,..., N-1) interleaver, 14-j (j = 0, 1, 2,..., N-1) convolutional coding unit , 16 parallel / serial converter, 20 receiver, 22 demodulator, 24 decoder, 30, 30a bit error rate calculator, 38-p, 38-j (j = 0, 1, 2,...) .., N−1) bit comparison unit, 40-p, 40-j (j = 0, 1, 2,..., N−1) counter, 42-p, 42-j (j = 0, 1, 1) 2,..., N-1) switch, 44 operation unit, 46 error detection unit, 48 switching control unit.

Claims (6)

An apparatus for calculating a bit error rate of a coded signal received in a communication system that transmits a coded signal including information bits and redundant bits obtained by performing predetermined processing on the information bits,
A decoding processing unit that decodes the received encoded signal to obtain decoded information bits,
A re-encoding processing unit that encodes the decoded information bits to generate a re-encoded signal;
A bit error rate calculation unit that calculates a bit error rate based on a comparison result between the received encoded signal and the re-encoded signal,
With
A bit error rate calculation device, wherein the bit error rate calculation unit can switch which bit among the information bits and the redundant bits to use in the calculation of the bit error rate. Further, an error detection unit that performs error detection of the decoded information bits,
The method according to claim 1, wherein a bit error rate is calculated by the bit error rate calculator based on an error detection result of the error detector. 2. The bit error rate calculation device according to 1. The case where the bit error rate is calculated using the comparison result of only the information bits in the bit error rate calculation unit, and the case where the bit error rate is calculated using the comparison result of the information bits and the redundant bits, The bit error rate calculation device according to claim 1, wherein the switching is performed. The encoded signal transmitted in the communication system includes n (n: an integer of 2 or more) redundant bits,
The re-encoding processing unit according to claim 1, wherein the re-encoding processing unit generates a re-encoded signal including m kinds (m: an integer of 1 or more, m <n) of redundant bits. 2. A bit error rate calculation device according to claim 1. A coded signal transmitted in a communication system is a turbo-coded bit sequence, that is, information bits, redundant bits for performing convolutional coding without interleaving information bits, and redundant bits for performing interleaving and convolutional coding for information bits. And a bit,
The re-encoding processing unit generates a re-encoded signal that includes the redundant bits for performing convolutional encoding without interleaving information bits and that does not include the redundant bits for interleaving and convolutionally encoding information bits. The bit error rate calculation device according to claim 4, wherein A method of calculating a bit error rate of a received encoded signal in a communication system that transmits an encoded signal including information bits and redundant bits obtained by performing predetermined processing on the information bits,
Decoding the received encoded signal to obtain decoded information bits;
Encoding the decoded information bits to generate a re-encoded signal;
Calculating a bit error rate based on a comparison between the received encoded signal and the re-encoded signal,
Including
In the bit error rate calculating step, a bit error rate calculating method is characterized by switching which bit of the information bit and the redundant bit is used for calculating the bit error rate.

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