JP2004147072A5 - - Google Patents

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Publication number
JP2004147072A5
JP2004147072A5 JP2002309733A JP2002309733A JP2004147072A5 JP 2004147072 A5 JP2004147072 A5 JP 2004147072A5 JP 2002309733 A JP2002309733 A JP 2002309733A JP 2002309733 A JP2002309733 A JP 2002309733A JP 2004147072 A5 JP2004147072 A5 JP 2004147072A5
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JP
Japan
Prior art keywords
signal
amplitude
outputs
subtractor
amplifier
Prior art date
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Application number
JP2002309733A
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Japanese (ja)
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JP4232433B2 (en
JP2004147072A (en
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Publication date
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Priority claimed from JP2002309733A external-priority patent/JP4232433B2/en
Priority to JP2002309733A priority Critical patent/JP4232433B2/en
Priority to CNB2003801062630A priority patent/CN100488040C/en
Priority to AU2003301465A priority patent/AU2003301465A1/en
Priority to DE60304887T priority patent/DE60304887T2/en
Priority to AT03756655T priority patent/ATE324703T1/en
Priority to PCT/JP2003/013257 priority patent/WO2004036742A1/en
Priority to ES03756655T priority patent/ES2261966T3/en
Priority to EP03756655A priority patent/EP1552606B1/en
Priority to US10/831,642 priority patent/US7215937B2/en
Publication of JP2004147072A publication Critical patent/JP2004147072A/en
Publication of JP2004147072A5 publication Critical patent/JP2004147072A5/ja
Priority to US11/581,205 priority patent/US7613441B2/en
Priority to US11/581,208 priority patent/US7587188B2/en
Priority to US11/581,206 priority patent/US7650128B2/en
Publication of JP4232433B2 publication Critical patent/JP4232433B2/en
Application granted granted Critical
Priority to US12/424,474 priority patent/US7809341B2/en
Priority to US12/538,581 priority patent/US7835714B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【0032】
また、信号生成回路10は、レベル検出回路101、増幅器102、減算器103、リミッタ回路104、PD105及びLPF106等を備える。レベル検出回路101は、例えば、信号aの最大振幅を検出し、検出結果に基づいた信号を増幅器102に出力する。増幅器102は、後述する減算器103から出力される信号cの振幅が一定になるように、レベル検出回路101から入力した信号に基づいて発振器93から入力した信号bを増幅し、信号b1として出力する。
[0032]
In addition, the signal generation circuit 10 includes a level detection circuit 101, an amplifier 102, a subtractor 103, a limiter circuit 104, a PD 105, an LPF 106, and the like. The level detection circuit 101 detects, for example, the maximum amplitude of the signal a, and outputs a signal based on the detection result to the amplifier 102. The amplifier 102 amplifies the signal b input from the oscillator 93 based on the signal input from the level detection circuit 101 so that the amplitude of the signal c output from the subtracter 103 described later becomes constant, and outputs the amplified signal as a signal b1. Do.

【0033】
減算器103は、フィルタ回路8から信号a、増幅器102から信号b1を入力し、信号aから信号b1を減算して信号cとして出力する。リミッタ回路104は、減算器103から入力した信号cの振幅を所定の上限値及び下限値の範囲に制限し、信号dとして出力する。リミッタ回路104によって、信号cに含まれるノイズをある程度除去することができる。
[0033]
The subtractor 103 receives the signal a from the filter circuit 8 and the signal b1 from the amplifier 102, subtracts the signal b1 from the signal a, and outputs the result as a signal c. The limiter circuit 104 limits the amplitude of the signal c input from the subtractor 103 to a range of predetermined upper limit value and lower limit value, and outputs it as a signal d. The limiter circuit 104 can remove noise contained in the signal c to some extent.

【0035】
ここで、減算器103から出力される信号cの振幅を一定にする為の、信号b1の振幅について説明する。長波標準波形は10%と100%の変調度を持つ。従って信号aも同様の振幅を持ち、信号aの最大振幅をXとすると、最小振幅は0.1Xとなる。また、信号b1の振幅はYとする。そして減算器103によって信号aから信号b1を減算した信号cの振幅の絶対値が一定になるためには、
|X−Y|=|0.1X−Y|
Y=0.55X
即ち、信号b1の振幅を信号aの最大振幅の55%とすることで、減算器103から出力する信号cの信号の振幅は一定となる。
[0035]
Here, the amplitude of the signal b1 for making the amplitude of the signal c output from the subtracter 103 constant will be described. The long wave standard waveform has 10% and 100% modulation. Therefore, the signal a also has the same amplitude, and assuming that the maximum amplitude of the signal a is X, the minimum amplitude is 0.1 ×. The amplitude of the signal b1 is Y. Then, in order for the absolute value of the amplitude of the signal c obtained by subtracting the signal b1 from the signal a by the subtractor 103 to be constant,
| X-Y | = | 0.1X-Y |
Y = 0.55X
In other words, by 55% of the maximum amplitude of the signal amplitude of the signal b1 a, the amplitude of the signal of the signal c output from the subtracter 103 is constant.

【0037】
まず、減算器103は信号aから信号b1を減算し、信号cを出力する(ステップS1)。ここで、レベル検出回路101によって信号aの振幅が検出され、増幅器102は検出結果に基づいて信号bを増幅して信号b1とする。このとき、信号b1はその振幅が信号aの最大振幅の55%になるように増幅される。また、信号aから信号b1を減算することによって、信号aの振幅が10%の変調度である時間帯A、Cにおいては、信号cは信号b1逆相となり、信号aの振幅が100%の変調度である時間帯Bにおいては、信号cは信号b1同相となる
[0037]
First, the subtractor 103 subtracts the signal b1 from the signal a and outputs the signal c (step S1). Here, the amplitude of the signal a is detected by the level detection circuit 101, and the amplifier 102 amplifies the signal b based on the detection result to obtain a signal b1 . At this time, the signal b1 is amplified so that its amplitude is 55% of the maximum amplitude of the signal a. Further, by subtracting the signal b1 from the signal a, in the time zones A and C in which the amplitude of the signal a is 10% modulation, the signal c is in reverse phase to the signal b1, and the amplitude of the signal a is 100%. In the time zone B which is the modulation degree of the signal c, the signal c is in phase with the signal b1 .

【0038】
次に、リミッタ回路104は信号cの振幅についてVH以上及びVL以下を遮断し、信号dを出力する(ステップS2)。そしてPD105は、信号bと信号dの位相を比較し、信号eを出力する(ステップS3)。ここで信号bの位相は信号b1と同相であるため、信号bの波形の図示は省略する。PD105は、信号bと信号dが同相である場合(時間A及びC)、信号dを正の方向に整流する。逆に信号bと信号dが逆相である場合(時間B)、信号dを負の方向に整流する。
[0038]
Next, the limiter circuit 104 blocks the amplitude of the signal c from V H or more and V L or less, and outputs a signal d (step S2). Then, the PD 105 compares the phases of the signal b and the signal d, and outputs a signal e (step S3). Here, since the phase of the signal b is in phase with the signal b1 , the illustration of the waveform of the signal b is omitted. The PD 105 rectifies the signal d in the positive direction when the signals b and d are in phase (time A and C). Conversely, if the signals b and d are in reverse phase (time B), the signal d is rectified in the negative direction.

【0042】
尚、本実施の形態では、信号b1は信号aの最大振幅の55%の振幅であることとして説明したが、信号aの最大振幅の10%の振幅であってもよい。つまり、信号aから信号aの最大振幅の10%の振幅を持つ信号を減算すると、100%の変調時には信号があるが、10%の変調時には信号が打ち消される。従って、減算結果の信号の有無を判別することによって、信号aを検波することが可能である。
[0042]
In the present embodiment, the signal b1 has been described as having an amplitude of 55% of the maximum amplitude of the signal a, but may have an amplitude of 10% of the maximum amplitude of the signal a. That is, when a signal having an amplitude of 10% of the maximum amplitude of the signal a is subtracted from the signal a, the signal is present at 100% modulation, but the signal is canceled at 10% modulation. Therefore, the signal a can be detected by determining the presence or absence of the signal resulting from the subtraction.

JP2002309733A 2002-10-16 2002-10-24 Radio receiver, radio clock, and repeater Expired - Fee Related JP4232433B2 (en)

Priority Applications (14)

Application Number Priority Date Filing Date Title
JP2002309733A JP4232433B2 (en) 2002-10-24 2002-10-24 Radio receiver, radio clock, and repeater
CNB2003801062630A CN100488040C (en) 2002-10-16 2003-10-16 Radio wave reception device, radio wave clock, and repeater
AU2003301465A AU2003301465A1 (en) 2002-10-16 2003-10-16 Radio wave reception device, radio wave clock, and repeater
DE60304887T DE60304887T2 (en) 2002-10-16 2003-10-16 Radio wave receiving device, radio wave clock, and repeater
AT03756655T ATE324703T1 (en) 2002-10-16 2003-10-16 RADIO WAVE RECEIVING DEVICE, RADIO WAVE CLOCK, AND REPEATER
PCT/JP2003/013257 WO2004036742A1 (en) 2002-10-16 2003-10-16 Radio wave reception device, radio wave clock, and repeater
ES03756655T ES2261966T3 (en) 2002-10-16 2003-10-16 RADIO WAVE RECEPTION DEVICE, RADIO WAVE CLOCK AND REPEATER.
EP03756655A EP1552606B1 (en) 2002-10-16 2003-10-16 Radio wave reception device, radio wave clock, and repeater
US10/831,642 US7215937B2 (en) 2002-10-16 2004-04-23 Radio wave reception device, radio wave clock, and repeater
US11/581,205 US7613441B2 (en) 2002-10-16 2006-10-13 Radio wave reception device and radio wave clock
US11/581,208 US7587188B2 (en) 2002-10-16 2006-10-13 Radio wave reception device, radio wave clock, and repeater
US11/581,206 US7650128B2 (en) 2002-10-16 2006-10-13 Radio wave reception device, radio wave clock, and repeater
US12/424,474 US7809341B2 (en) 2002-10-16 2009-04-15 Radio wave reception device, radio wave clock, and repeater
US12/538,581 US7835714B2 (en) 2002-10-16 2009-08-10 Radio wave reception device, radio wave clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002309733A JP4232433B2 (en) 2002-10-24 2002-10-24 Radio receiver, radio clock, and repeater

Publications (3)

Publication Number Publication Date
JP2004147072A JP2004147072A (en) 2004-05-20
JP2004147072A5 true JP2004147072A5 (en) 2005-03-17
JP4232433B2 JP4232433B2 (en) 2009-03-04

Family

ID=32455459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002309733A Expired - Fee Related JP4232433B2 (en) 2002-10-16 2002-10-24 Radio receiver, radio clock, and repeater

Country Status (1)

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JP (1) JP4232433B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100835084B1 (en) 2006-09-29 2008-06-04 삼성전기주식회사 Receiver having auto-controll function for frequency bend

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