JP2004146716A - Sem type visual-inspection method and apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection method and apparatus having higher performances than conventional ones whereby the unintended kinds of defects including false informations can be removed from their inspection results and automatic-defect-classification (ADC) results. <P>SOLUTION: In the inspection apparatus using an electron microscope which senses the defects present on the pattern of a sample based on the sensed signal of secondary charged particles generated by a scanning electron beam, there is provided such a function that the informations obtained by its ADC function are so fed back to its inspection function in the form of an inspection/non-inspection region as to improve its inspection and ADC performances. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inspection method and an inspection apparatus using a scanning electron microscope for inspecting a semiconductor device having a fine pattern, a wafer, a photomask (exposure mask), and a substrate such as a liquid crystal.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor device such as a memory or a microcomputer used for a computer or the like is manufactured by repeating a process of transferring a pattern of a circuit or the like formed on a photomask by exposure processing, lithography processing, etching processing, or the like. In the manufacturing process of a semiconductor device, the quality of the result of the lithography process, the etching process, and other processes, and the presence of a defect such as generation of a foreign substance greatly affect the manufacturing yield of the semiconductor device. Therefore, in order to detect the occurrence of an abnormality or a defect early or in advance, a pattern on a semiconductor wafer is inspected at the end of each manufacturing process.
[0003]
As an example of a method for inspecting a defect existing in a pattern on a semiconductor wafer, an optical appearance inspection apparatus that compares patterns using an optical image obtained by irradiating a semiconductor wafer with light has been put to practical use. However, with the miniaturization of circuit patterns, the complexity of circuit pattern shapes, and the diversification of materials, it is difficult to detect such defects in optical images, so electron beam images with higher resolution than optical images must be used. A method and an apparatus for inspecting a pattern have been put to practical use.
For example, techniques described in the following Patent Literature 1, Patent Literature 2, Non-Patent Literature 1, Non-Patent Literature 2, Non-Patent Literature 3, and Non-Patent Literature 4 are known.
[0004]
In order to perform high-throughput and high-precision inspection following the increase in the diameter of a wafer and the miniaturization of a circuit pattern, it is necessary to acquire an image with a high SN at a very high speed. Therefore, the number of electrons irradiated by using a large current beam that is 1000 times or more (100 nA or more) that of a normal scanning electron microscope (SEM) is secured, and a high SN ratio is maintained. Further, high-speed and high-efficiency detection of secondary electrons and reflected electrons generated from the substrate is essential.
[0005]
Further, a low-acceleration electron beam of 2 keV or less is irradiated so that a semiconductor substrate having an insulating film such as a resist is not affected by charging. This technique is described in Non-Patent Document 5. However, a large current and low-acceleration electron beam causes aberration due to the space charge effect, making it difficult to perform high-resolution observation.
As a method for solving this problem, a method is known in which a high-acceleration electron beam is decelerated immediately before a sample and irradiated on the sample as a substantially low-acceleration electron beam. For example, there are techniques described in Patent Literature 3 and Patent Literature 4.
[0006]
Patent Document 5 discloses a means for irradiating an electron beam on a substrate surface on which a circuit pattern is formed and scanning the same, a detecting means for detecting a signal generated secondarily from the substrate surface, and a method for detecting the detected signal. There is described a pattern inspection apparatus including a means for forming an image on an operation screen, and a means for recognizing and discriminating information on foreign matters and defects based on the shape, unevenness, and potential contrast of the substrate surface from the image. .
[0007]
Patent Document 6 discloses that a defect on a substrate to be inspected is determined based on the converted defect image signal and layout information of various conductor components on the substrate to be inspected. An SEM defect review apparatus including a category classification unit for automatically classifying the defect into a category indicated by the type of the continuity failure defect is described.
[0008]
Patent Document 7 discloses a defect display screen forming means for displaying the number of defects and a defect position, a defect position specifying means for specifying a defect position from the defect display screen, and a two-dimensional one-time scanning SEM image of the designated defect position. Inspection apparatus for semiconductor circuit patterns, which includes a defect location / inspection image for displaying a mark and a monitor means.
[0009]
Patent Literature 8 describes an inspection method using an electron beam including a step of creating an image signal in which predetermined both end portions of an electron beam scanning area are deleted and a step of inspecting the surface of a sample based on the image signal. Have been.
[0010]
Patent Document 9 discloses that at least one kind of inspection information of an inspection apparatus and an inspection result of an inspection apparatus for inspecting a defect of a sample is stored, and the stored information can be transmitted and received between a plurality of inspection apparatuses. Along with storing the determination result of whether or not the defect of the sample detected by the apparatus is a false report, the defect candidate detected in the sample area where the false report occurs frequently is subjected to statistical processing to set a low probability of review. A defect observation method for observing the defect is described.
In the inspection apparatus using the SEM as described above, the following problems still remain.
[0011]
[Patent Document 1]
JP-A-59-192943
[Patent Document 2]
JP-A-5-258703
[Patent Document 3]
JP-A-2-142045
[Patent Document 4]
JP-A-6-139885
[Patent Document 5]
JP 2001-159616 A
[0012]
[Patent Document 6]
JP 2002-124555 A
[Patent Document 7]
JP 2000-161948 A
[Patent Document 8]
JP-A-2002-251975
[Patent Document 9]
JP 2002-100660 A
[0013]
[Non-patent document 1]
Electron-beam inspection system for x-ray mask production, Sandland, et al. J. et al. Vac. Sci. Tech. B, Vol. 9, No. 6, pp. 3005-3009 (1991)
[Non-patent document 2]
Requirements and performance of an electron-beam
column-designed for x-ray mask inspection, Meisburger, et al. , J. et al. Vac. Sci. Tech. B, Vol. 9, No. 6, pp. 3010-3014 (1991)
[Non-Patent Document 3]
Low-voltage electron-optical system for the high-speed
inspection of integrated circuits, Meisburger, et al. , J. et al. Vac. Sci. Tech. B, Vol. 10, No. 6, pp. 2804-2808 (1992)
[Non-patent document 4]
Characterization of a New Automated Electron-Beam
See Wafer Inspection System, Hendricks, et al. , SPIE Vol. 2439, p. 174-183 (20-22 February, 1995)
[Non-Patent Document 5]
"Electron / Ion Beam Handbook (2nd edition)", edited by the 132nd Committee of the Japan Society for the Promotion of Science, (Nikkan Kogyo Shimbun, 1986), p. 622-623
[0014]
[Problems to be solved by the invention]
The SEM type visual inspection apparatus may include a defect that is not originally intended due to various causes. In such a case, a function of automatically identifying and classifying the defect (Automatic Defect Review; ADR, Automatic Defect Classification; ADC). To select the desired defect. However, if a large number or a large number of defects not intended are included, it is expected that not only will the ADC classification accuracy be reduced, but also that the inspection performance of the inspection apparatus itself will be reduced.
[0015]
The present invention has been made in view of the above points, and improves the defect detection performance and ADC classification accuracy by providing a function of designating an area in which a large number of unintended defects are once detected by the ADC function. An object of the present invention is to provide an SEM-type visual inspection method and an inspection apparatus.
[0016]
[Means for Solving the Problems]
According to the present invention, an area in which many defects that are not intended by the ADC function are detected once is a non-inspection area in the next inspection, and an area in which many defects are detected is inspected in more detail. In addition, the present invention provides an SEM-type visual inspection method and an inspection apparatus that have a function of designating only that region as an inspection region, thereby improving defect detection performance and ADC classification accuracy.
[0017]
The object is to irradiate a semiconductor substrate in the middle of a pre-process, for example, a wafer surface (hereinafter, described by taking a wafer surface as an example) with an electron beam, and to generate an electronic signal secondary generated from the wafer surface by the electron beam. Detecting, and storing an image signal of a first area on the wafer surface based on the electronic signal, and converting the image of the area stored in the storage step to another image on the wafer surface. Calculating a feature amount of the defect in the SEM type visual inspection method including a step of comparing the image with the image of the second area where the same wafer pattern is formed, and a step of determining a defect on the wafer pattern from the comparison result Performing the step of classifying the defect based on the feature amount, linking the classified defect with a defect position, and setting an area on the wafer surface including the defect classification having a malformed defect position. It can be realized by having a step of setting the inspection or non-examination region later times.
Further, the defect classification step may be a graph display using the feature amount on a coordinate axis.
[0018]
Further, the defect position linking step may be a map display in which the correspondence between the defect or defect group classified in the defect classification step and the defect position on the wafer surface of the defect or defect group can be visually confirmed.
The inspection or non-inspection area setting step may set, on the map display, an area on the wafer surface including the defect classification having an unevenly located defect position.
[0019]
On the other hand, means for irradiating the semiconductor wafer surface in the middle of the pre-process with an electron beam, means for detecting an electronic signal secondary generated from the wafer surface by the electron beam, Means for storing the image signal of the first area, and comparing the image of the area stored in the storing step with the image of the second area where another identical wafer pattern is formed on the wafer surface Means for calculating a feature amount of the defect, and means for classifying the defect based on the feature amount. Means for linking the classified defect with a defect position, and means for setting a region on the wafer surface including the defect classification having a maldistributed defect position as a next or subsequent inspection or non-inspection region More can be achieved.
[0020]
Here, the target defect is a defect of a type that the user desires to detect, and is a defect that is not the target if the same defect is of a type that the user does not want.
Further, even if a defect does not actually exist, a “false alarm” that is output in the same manner as an actual defect due to an inspection device is a defect that is not intended regardless of the user's wishes.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 5 show a first embodiment of the present invention.
FIG. 1 shows an embodiment of the inspection apparatus according to the present invention. The SEM main body 60 roughly includes an electron beam generating unit including the electron source 50, an electron beam scanning control unit including the deflection electrode 52, and a sample operation unit including the sample 61, the sample holder 62, the sample moving stage 56, and the like.
[0022]
The primary electron beam 71 generated from the electron source 50 is accelerated by an acceleration electrode (not shown) and irradiates the sample 61 held by the sample holder 62. In the process, the electron optical system constituted by the coil and the electrode is controlled by the electron optical system control circuit 51 so that the electron beam 71 is focused at the sample position. The electron beam 71 is scanned by the deflection electrode 52 and the deflection control circuit 53 and combined with the sample moving stage 56 controlled by the stage control circuit 57 to obtain a stripe image.
[0023]
Secondary electrons 72 are generated from the sample surface by the primary electron beam 71 irradiating the sample 61. The secondary electrons 72 are accelerated again by an electrode (not shown) and guided to the detector 54 by an electrode (not shown). The secondary electrons captured by the detector 54 are signalized by the detection circuit 55 and sent to the image processing device 58.
[0024]
The image sent to the image processing device 58 is corrected by the input correction unit 501. Here, for example, gradation conversion, dark level correction, beam addition processing, and the like for adjusting the contrast of the image are performed. The corrected image is sent to the chip memory 502. The chip memory 502 temporarily stores an image in chip units and generates a delayed image for image comparison. The inspection image and the reference image generated from the chip memory 502 are sent to the CH dividing unit 503 and divided into a plurality of CHs. By dividing into a plurality of channels, it is possible to reduce the image processing rate as compared with processing the image as it is.
[0025]
The image divided into CHs is corrected by the position correction unit 504 so as to match each other on a pixel-by-pixel basis after measuring the positional deviation of the image between the inspection image and the reference image. The corrected image is sent to the chip comparison unit 505 and the feature amount generation unit 506. The chip comparing unit 505 extracts a part having a difference between the inspection image and the reference image and outputs the extracted part as a defect image. The feature amount generation unit 506 obtains, for example, a gradation difference between the inspection image and the reference image, and a brightness gradient (differential value) of each pixel of the inspection image. The defect image is sent to the feature extraction unit 507 to obtain the position, projection length, area, and the like of the defect. The feature amount calculation unit 508 compiles the tone difference and the differential value from the feature amount generation 506 in synchronization with the defect portion, and calculates the feature amount of the defective portion, for example, the sum of the tone differences and the sum of the absolute values of the differential values. I do. The value obtained by the feature extraction 507 and the value obtained by the feature calculation 508 are collected in the defect information unit 509 and digitized. The digitized defect information is sent to the host computer 59 by the operation of the control CPU 510 and the like. 520 is a system bus.
[0026]
In the present embodiment, the process of the chip comparison is described as an example. However, the same process is performed in the case of effective cell comparison when cells having the same structure are regularly arranged like a cell mat portion of a memory. However, the position correction is a process of shifting the inspection image by the cell pitch, and the process of detecting a large positional shift between the images is unnecessary. Further, depending on how the circuit is assembled, the inspection image and the reference image do not need to be separately divided from the chip memory 502 and divided into channels 503, and the signals can be separated from the image signal before the position correction 504.
[0027]
The host computer 59 has a GUI (Graphical User Interface) and has a function of receiving instructions from an operator and controlling the entire apparatus. For example, an inspection control unit 601 that controls an inspection sequence, a defect confirmation control unit 602 that classifies defect information after inspection based on a feature amount and confirms a specific defect, and a recipe control unit 603 that creates an inspection recipe. And a utility control unit 604 necessary for operating the apparatus, a defect determination unit 605 for extracting a real defect from the defect information by real ghost processing, and a sequence control for controlling a collective operation such as inspection and defect confirmation. Each function includes a unit 606, a GUI control unit 607, a data management unit 608 for inspection results, defect images, recipe information, and the like.
[0028]
Next, the operation of each unit of the inspection apparatus shown in FIG. 1 will be described according to the inspection flow of FIG.
First, a wafer cassette in which wafers are placed on an arbitrary shelf is placed on a cassette mounting portion of a wafer transfer system (Step 310 in FIG. 5).
[0029]
Next, in order to specify a wafer to be inspected from the operation screen, a shelf number in the cassette in which the wafer is set is specified. Then, various inspection conditions are input from the operation screen (Step 320 in FIG. 5). Inspection condition input contents include electron beam current, electron beam irradiation energy, scanning speed and signal detection sampling clock, inspection area, various information on the wafer to be inspected, whether or not to automatically inspect a plurality of wafers, and the same. Whether the wafer is continuously inspected under different inspection conditions, the contents such as ADC conditions are input. Although it is possible to input individual parameters, usually, a combination of the above various inspection parameters is stored in a database as an inspection condition file, and it is only necessary to select and input an inspection condition file. When the input of these conditions is completed (Step 320 in FIG. 5), the inspection is started as Step 330 (Step 330 in FIG. 5).
[0030]
When the automatic inspection is started, first, the set wafer is transferred into the inspection apparatus. In the wafer transfer system, the holder for mounting the wafer is set to the size and shape of the wafer regardless of whether the diameter of the wafer to be inspected is different or the shape of the wafer is different such as an orientation flat type or a notch type. It can be dealt with by replacing them together. The wafer to be inspected is placed on a holder by a wafer loader including a cassette, an arm, a preliminary vacuum chamber, etc., held and fixed, and evacuated in the wafer loader together with the holder, and the inspection chamber is already evacuated by the vacuum exhaust system. (Step 340 in FIG. 5).
[0031]
When the wafer is loaded, electron beam irradiation conditions are set for each unit by the electron optical system control unit based on the input inspection conditions. Then, the stage is moved so that the beam calibration pattern placed on the wafer holder is under the electron optical system (Step 350 in FIG. 5), an electron beam image of the beam calibration pattern is obtained, and the focus is set based on the image. And adjustment of astigmatism. Then, it moves to a predetermined position on the wafer to be inspected, acquires an electron beam image of the wafer, and adjusts contrast and the like. Here, when it becomes necessary to change the electron beam irradiation conditions and the like, the parameters can be changed and the beam calibration can be performed again. At the same time, the height of the wafer is obtained from the height detector, and the correlation between the height information and the focusing condition of the electron beam is obtained by the wafer height detection system. Automatically adjusts the focus condition based on the result of the wafer height detection. As a result, high-speed continuous electron beam image acquisition has become possible (step 360 in FIG. 5).
After the adjustment of the electron beam irradiation condition and the adjustment of the focus and astigmatism, alignment is performed at two points on the wafer (step 370 in FIG. 5).
[0032]
When the alignment is completed, the rotation and the coordinate values are corrected based on the alignment result, and then the pattern is moved to the second calibration pattern placed on the sample holder (Step 380 in FIG. 5). The second calibration pattern is a transistor in which a junction is normally formed in advance or a pattern corresponding to the transistor, and the brightness of the normal portion is calibrated using the pattern. Based on this result, the wafer is moved onto the wafer, an image of the pattern location on the wafer is obtained, and the brightness adjustment, that is, the calibration is performed (Step 390 in FIG. 5).
[0033]
When the calibration is completed, an inspection is performed (Step 400 in FIG. 5). As for the inspection method, the image processing is performed in real time while the stage is continuously moved and the specified area is inspected, and the image is automatically saved at the position where the defect occurs (step 410 in FIG. 5). Then, the inspection result and the ADC result are displayed on the monitor, and the data is output to the outside via the data conversion unit (step 420 in FIG. 5).
[0034]
When the inspection conditions are set (step 320 in FIG. 5) to inspect the same portion a plurality of times under different conditions, the area that has been inspected once is subjected to a charge removal process. Although the charge removing section is not shown in FIG. 1, for example, the charge removing processing is performed by irradiating ultraviolet light.
[0035]
Then, the inspection is performed again under different electron beam irradiation conditions (step 400 in FIG. 5). In the present embodiment, a step of resetting the inspection / non-inspection area from the inspection result and the ADC result and determining whether or not to perform the inspection again (step 430 in FIG. 5) is added. That is, a step (Step 440 in FIG. 5) of resetting the inspection / non-inspection area when re-inspection is performed is provided. In this way, when the inspection is completed, the wafer is unloaded and the inspection ends (Step 450 in FIG. 5).
[0036]
The inspection method of the SEM appearance inspection apparatus will be specifically described with reference to FIGS. 2, 3, and 4. FIG. 2 is a diagram showing a process of setting an inspection / non-inspection region, FIG. 3 is a defect map diagram displayed on the screen, and FIG. 4 is a defect classification diagram displayed on the screen.
[0037]
2, a defect inspection unit 200 corresponds to the image processing device 58 and the host computer 59 in FIG. 1, and defect information and feature amounts 210 output therefrom are input to the defect classification unit 220. The defect classifying unit 220 can classify the defect as a defect class 230 shown in FIG. In FIG. 4, it is classified into open, short, and other defects. Further, when these pieces of information are input to the defect position link unit 240, the information is displayed as a defect position information 250 on the wafer, for example, in a map corresponding to the defect of each classification (FIG. 3). The defects classified into the defect positions are displayed, the status of the uneven distribution of the defects is displayed on the screen, and the area on the wafer surface where the defects having the unevenly distributed defect positions are displayed is specified. Here, in the inspection / non-inspection area setting unit 260, it is possible to easily set the inspection / non-inspection area for the next and subsequent times by specifying the desired defect group (270). As a result, a target defect can be selectively inspected, and the classification performance of the ADC can be significantly improved. Here, all of 220, 240, and 260 can be configured on the host computer 59.
The determination as to whether or not there is a defect is made based on whether or not an index such as a difference in brightness or a position shift exceeds a certain threshold value.
[0038]
At this time, by appropriately selecting the feature amount of the defect, the target defect can be narrowed down, and the threshold value can be set more accurately and in detail than when the threshold value is commonly set for various types of defects. Detect defects that could not be detected until now.
[0039]
Next, a detailed flow (corresponding to step 430 in FIG. 5) of the first embodiment of the present invention will be described with reference to FIG.
First, the results of the inspection and the ADC are input (step 700 in FIG. 6), and thereafter, the feature amount of the defect is calculated using the results (step 710 in FIG. 6). In this case, the feature amount may be sequentially calculated simultaneously with the inspection. A feature amount suitable for classifying a defect from the obtained feature amount is designated (step 720 in FIG. 6), and a defect classification display as indicated by 230 in FIG. 4 is performed (step 730 in FIG. 6). Also in this case, the feature amount may be specified in advance before the inspection, and the defect amount processing may be sequentially performed while calculating the feature amount simultaneously with the inspection. Next, corresponding to this defect classification, defect position information 250 on the wafer as shown in FIG. 3 is displayed (step 740 in FIG. 6). Then, using the defect position information 250, the next inspection / non-inspection area can be easily set in the form of specifying a desired defect group as shown in 270 in FIG. 3 (step in FIG. 6). 750). The above-described repetition is performed by selecting another feature amount, and a necessary inspection / non-inspection area is set. Then, it is determined whether or not the area setting has been completed (step 760 in FIG. 6). If the area setting has been completed, the process proceeds to a determination as to whether or not to perform a reexamination (step 770 in FIG. 6), and reexamination or termination is selected.
[0040]
As described above, the step of irradiating the semiconductor substrate surface with an electron beam, the step of detecting an electronic signal generated secondarily from the substrate surface by the electron beam, and the step of detecting an electronic signal on the substrate surface based on the electronic signal A step of storing an image signal of an area, and a step of determining a defect on a substrate pattern by using the image of the area stored in the storing step. Calculating the feature amount of the defect, classifying the defect based on the feature amount, linking the classified defect with a defect position, and displaying the defect classified into the defect position. Displaying the uneven distribution of defects on a screen; identifying an area on the substrate surface where a defect having an unevenly located defect is displayed; and applying the identified area to the next or subsequent inspection or inspection area. Configuration That SEM Shikigaikan inspection method according to SEM Shikigaikan inspection system is constructed and a step.
[0041]
A step of irradiating the semiconductor substrate surface with an electron beam; a step of detecting an electronic signal generated secondarily from the substrate surface by the electron beam; and a first step on the substrate surface based on the electronic signal. A step of storing an image signal of the area, and a step of comparing the image of the area stored in the storing step with an image of a second area where another substrate pattern on the same substrate surface is formed; Determining the defect on the substrate pattern from the comparison result; calculating the characteristic amount of the defect in the SEM type visual inspection method using the SEM type visual inspection device; and classifying the defect based on the characteristic amount Performing the step of linking the classified defects and the defect positions; displaying the defects classified into the defect positions to display the uneven distribution of the defects on a screen; and displaying the defects having the unevenly distributed defect positions. The base Identifying a region on the surface, SEM Shikigaikan inspection method according to SEM Shikigaikan inspection apparatus and a step of setting the specified region in the examination or inspection area of the next time is formed.
[0042]
Further, an SEM appearance inspection method is characterized in that each step is repeated to narrow down defects in an inspection or non-inspection area.
A means for irradiating the semiconductor substrate surface with an electron beam; a means for detecting an electronic signal secondary generated from the substrate surface by the electron beam; and an image of an area on the substrate surface based on the electronic signal. Calculating a feature amount of the defect in the SEM type visual inspection apparatus, comprising: means for storing a signal; and means for determining a defect on the substrate pattern using the image of the area stored in the storing step. Means for classifying the defect based on the feature amount, means for linking the classified defect with a defect position, displaying the defect classified into the defect position, and displaying the uneven distribution state of the defect on a screen. Means for specifying an area on the substrate surface on which a defect having an unevenly located defect position is displayed, and means for setting the specified area and a next or subsequent inspection or non-inspection area With device SEM appearance inspection apparatus is configured that.
[0043]
A means for irradiating the semiconductor substrate surface with an electron beam; a means for detecting an electronic signal generated secondarily from the substrate surface by the electron beam; and a first device on the substrate surface based on the electronic signal. Means for storing an image signal of an area, means for comparing the image of the area stored in the storage step with an image of a second area on which another substrate pattern on the same substrate surface is formed, A means for calculating a feature amount of the defect; a means for classifying the defect based on the feature amount; Means for linking a defect with a defect position, means for displaying defects classified into defect positions and displaying the uneven distribution of defects on a screen, and an area on the substrate surface on which a defect having an unevenly distributed defect position is displayed The process of identifying , SEM appearance inspection apparatus is configured with an image processing apparatus having a means for setting the inspection or non-examination region next and subsequent and said specified region.
[0044]
As described above, if false information is concentrated around the wafer due to, for example, disturbance of the electric field distribution around the wafer, if only this false information can be separated by selecting the feature amount, the next inspection / Since a non-inspection area can be easily set, an excellent inspection method and an excellent inspection apparatus capable of detecting a target defect with higher accuracy can be provided.
[0045]
FIG. 7 shows a second embodiment of the present invention. The configuration of the first embodiment is substantially adopted. In the first embodiment of FIG. 2, the defect position information 250 is targeted for the defect distribution on the wafer, but here, the defect distribution in the die 800 on the wafer 810 is targeted.
[0046]
The die 800 of the wafer 810 in FIG. 7A includes a memory mat 820, a direct peripheral circuit 830, an indirect peripheral circuit 840, and the like as illustrated in the die enlarged view of FIG. 7B. Here, since the peripheral circuits 830 and 840 have a lower pattern density than the memory mat unit 820, it is difficult to perform positioning in image processing, and false information tends to occur. Here, for example, a case where a false report common to each die occurs in a part of the direct peripheral circuit 830 is shown. If the false information can be separated by proper selection of the feature quantity, the same inspection / non-inspection area can be easily set for all the dies by the area setting 270 including the defect distribution.
As described above, according to this embodiment, it is possible to efficiently remove false alarms depending on the circuit pattern in the die.
[0047]
For false alarms that depend on circuit patterns in a die, the inspection / non-inspection area on one die can be automatically set in the same manner on all dies on the wafer instead of manually setting. Also, in the case where the distribution of the false report is clear on the external shape, such as a low pattern density, etc., and as described above, the false report is unrelated to the user's desire (the user does not have to ask the user → automation is possible). In some cases, fully automatic setting of the inspection / non-inspection area on the die is also possible.
[0048]
FIG. 8 shows a third embodiment of the present invention. FIG. 8 shows a GUI for setting an inspection / non-inspection area for the next and subsequent times in the defect position information (defect map) 250. Click 910 to set an inspection area or 920 to set a non-inspection area, and then set an area on the defect map. Although FIG. 8 shows a setting example 270 of a rectangle in the setting of the area, for example, an arbitrary polygon using a polygonal line may be used. In addition, the set inspection / non-inspection areas are distinguished by colors and line types, and are configured to be easily apparent. Although FIG. 8 shows the defect position information on the wafer, it can be switched to the die display, and can be used as the GUI of the embodiment shown in FIG.
[0049]
Here, on the screen 930 on the right side, an actual SEM image can be reacquired and displayed by clicking a defect on the defect map. At this time, if the image at the time of inspection remains in the memory, the image may be displayed. Further, the defect classification information 230 corresponding to the left defect position information (defect map) 250 may be displayed as shown in FIG. In that case, the GUI may be configured so that an arbitrary feature amount can be set on the X and Y axes of the graph.
[0050]
As described above, a series of flows from the automatic defect classification (ADC) result display 230, the defect position information display 250 (wafer / die), and the inspection / non-inspection area setting information display 270 can be uniformly handled in the GUI of FIG. This makes it possible to provide an inspection method and an inspection apparatus that are easier to use.
[0051]
【The invention's effect】
As described above, according to the present invention, the information obtained by the ADC function is fed back to the inspection function in the form of an inspection / non-inspection area, thereby improving both the inspection performance and the ADC performance. An inspection method and an inspection device can be provided.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view showing a device configuration of an SEM type visual inspection device.
FIG. 2 is a block diagram illustrating a first embodiment of setting an inspection / non-inspection area for the next and subsequent times based on the ADC result of the present invention.
FIG. 3 is a defect map diagram.
FIG. 4 is a defect classification diagram.
FIG. 5 is a diagram showing an inspection flow for obtaining defect position information according to the present invention.
FIG. 6 is a diagram showing a flow of ADC result feedback according to the present invention.
FIG. 7 is a view for explaining setting of an inspection / non-inspection area in a die according to a second embodiment of the present invention.
FIG. 8 is a diagram showing a monitor display example of an inspection / non-inspection area setting screen according to a third embodiment of the present invention.
[Explanation of symbols]
Reference numeral 50: electron source, 51: electron beam source control device, 52: deflection electrode, 53: deflection control circuit, 54: detector, 55: detection circuit, 56: sample moving stage, 57: stage control circuit, 58: image processing Apparatus, 59: Host computer, 60: SEM main body, 61: Sample, 62: Sample holder, 71: Electron beam, 72: Secondary electron, 220: Defect classification unit, 230: Defect classification information, 240: Defect position link unit , 250: defect position information, 260: inspection / non-inspection area setting unit, 270: inspection area information, 501: input correction unit, 502: chip memory, 503: CH division unit, 504: position correction unit, 505: chip comparison Unit, 506: feature amount generation unit, 507: feature extraction unit, 508: feature amount calculation unit, 509: defect information unit, 510: control CPU, 601: inspection control unit, 602: defect confirmation control unit, 05 ... defect determination unit, 607 ... GUI control unit.

Claims (10)

A step of irradiating the semiconductor substrate surface with an electron beam, a step of detecting an electronic signal generated secondarily from the substrate surface by the electron beam, and an image signal of an area on the substrate surface based on the electronic signal. A step of storing, and a step of determining a defect on the substrate pattern using the image of the area stored in the storage step, the SEM appearance inspection method by the SEM appearance inspection apparatus,
Calculating the feature amount of the defect;
Classifying the defect based on the feature amount;
Linking the classification defects and defect locations;
Displaying the defects classified into the defect positions and displaying the uneven distribution of the defects on a screen;
A step of specifying an area on the substrate surface where a defect having an unevenly located defect position is displayed,
Setting the specified area as a next or subsequent inspection or inspection target area. Irradiating the semiconductor substrate surface with an electron beam, detecting an electronic signal secondary generated from the substrate surface by the electron beam, and a first region on the substrate surface based on the electronic signal. A step of storing an image signal; a step of comparing the image of the area stored in the storage step with an image of a second area where another substrate pattern on the same substrate surface is formed; Discriminating a defect on the substrate pattern from the SEM-type visual inspection method using a SEM-type visual inspection device comprising:
Calculating the feature amount of the defect;
Classifying the defect based on the feature amount;
Linking the classification defects and defect locations;
Displaying the defects classified into the defect positions and displaying the uneven distribution of the defects on a screen;
A step of specifying an area on the substrate surface where a defect having an unevenly located defect position is displayed,
Setting the specified area as a next or subsequent inspection or inspection target area. 3. The SEM appearance inspection method according to claim 1, wherein each step is repeated to narrow down defects in an inspection or non-inspection area. 3. The SEM appearance inspection method according to claim 1, wherein in the defect position linking step, the correspondence between the defect or defect group classified by the defect classification and the defect position on the substrate surface of the defect or defect group is visually confirmed. An SEM-type visual inspection method characterized in that the map display is possible. 5. The SEM appearance inspection method according to claim 1, wherein the inspection or non-inspection area setting step displays, on the map surface, an area on the substrate surface including the defect classification having an unevenly located defect position. An SEM type visual inspection method characterized by being set as above. Means for irradiating the semiconductor substrate surface with an electron beam, means for detecting an electronic signal secondary generated from the substrate surface by the electron beam, and an image signal of an area on the substrate surface based on the electronic signal. A SEM-type visual inspection apparatus comprising: a storage unit; and a unit configured to determine a defect on the substrate pattern using the image of the area stored in the storage step.
Means for calculating the feature amount of the defect,
Means for classifying the defect based on the feature amount;
Means for linking the classification defect with a defect position;
Means for displaying defects classified into defect positions and displaying the uneven distribution of defects on a screen;
A step of specifying an area on the substrate surface where a defect having an unevenly located defect position is displayed,
An SEM visual inspection apparatus comprising: an image processing apparatus including the specified area and a unit for setting a next or subsequent inspection or non-inspection area. Means for irradiating the semiconductor substrate surface with an electron beam, means for detecting an electronic signal secondary generated from the substrate surface by the electron beam, and a first region on the substrate surface based on the electronic signal. Means for storing an image signal; means for comparing the image of the area stored in the storing step with an image of a second area on the same substrate surface on which another substrate pattern is formed; Means for determining a defect on the substrate pattern from the SEM type visual inspection device comprising:
Means for calculating the feature amount of the defect,
Means for classifying the defect based on the feature amount;
Means for linking the classification defect with a defect position;
Means for displaying defects classified into defect positions and displaying the uneven distribution of defects on a screen;
A step of specifying an area on the substrate surface where a defect having an unevenly located defect position is displayed,
An SEM visual inspection apparatus comprising: an image processing apparatus including the specified area and a unit for setting a next or subsequent inspection or non-inspection area. 8. The SEM type visual inspection apparatus according to claim 6, wherein each means is repeated to narrow down defects in an inspection or non-inspection area. 8. The SEM type visual inspection device according to claim 6, wherein the defect position linking means performs a map display in which a defect or a defect group classified by the defect classification can be visually checked for a correspondence of a defect position on a substrate surface. SEM type visual inspection device characterized by the above-mentioned. 10. The SEM type visual inspection apparatus according to claim 6, wherein the inspection or non-inspection area setting means displays the area on the substrate surface including the defect classification having the unevenly located defect positions on the map. A SEM type visual inspection device characterized by setting above.

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