JP2004140219A - Semiconductor fabricating method - Google Patents

Semiconductor fabricating method Download PDF

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Publication number
JP2004140219A
JP2004140219A JP2002304283A JP2002304283A JP2004140219A JP 2004140219 A JP2004140219 A JP 2004140219A JP 2002304283 A JP2002304283 A JP 2002304283A JP 2002304283 A JP2002304283 A JP 2002304283A JP 2004140219 A JP2004140219 A JP 2004140219A
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Japan
Prior art keywords
insulating film
semiconductor substrate
reaction chamber
semiconductor device
frequency power
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JP2002304283A
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Japanese (ja)
Inventor
Yuji Honda
本田 勇二
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NEC Kyushu Ltd
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NEC Kyushu Ltd
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Priority to JP2002304283A priority Critical patent/JP2004140219A/en
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  • Chemical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To enable an interlayer insulation film 25 to be embedded in a gaps between the interconnections 23 on a semiconductor substrate without damaging the insulation film 22 of its underlayer on the semiconductor substrate 21 by plasma ions, and without charging up the underlayer in a semiconductor fabricating method for forming the interlayer insulation film for filling the gaps between the interconnections 23. <P>SOLUTION: On the insulation film 22 containing the interconnections 23 in the semiconductor substrate 21 including the interconnections 23 on the insulation film 22, a thin protection film 24 is formed without applying a substrate bias voltage, and thereafter the interlayer insulating film 25 is formed. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関し、特に、半導体基板に高周波電力を印加する高密度プラズマCVD法を用いて半導体装置の層間絶縁膜を形成する半導体装置の製造方法に関する。
【0002】
【従来の技術】
近年、半導体装置の回路素子の微細化に伴いによる半導体装置における配線構成には、多層配線が必要となる。また、微細化による配線の間隔や線幅が狭くなる。しかしながら、この配線の微細化による配線抵抗の増加を避けるために、ある程度の配線断面積が必要である。
【0003】
このため、配線の高さを高くし実際の抵抗を低くしている。しかしながら、配線の間隔が狭く配線の高さが高くなる高アスペクト比の配線パタ−ンに層間絶縁膜を埋めるには、埋め込み性の良い、例えば、シリコン基板に高周波電力を印加するバイアス系プラズマCVD法が主に用いられている。
【0004】
図3(a)〜(c)は従来の半導体装置の製造方法の一例を説明するための図である。この製造方法は、間隔の狭いあるいは広い金属配線に層間絶縁膜を形成する方法である。まず、図3(a)に示すように、シリコン基板101の表面に絶縁膜102が形成され、さらに、絶縁膜102の上にパタ−ニングされた下層配線107a〜107eが形成されている。
【0005】
次に、図3(b)に示すように、シリコン基板101に高周波電力を印加し、高密度プラズマ法により13.5MHzという高い基板バイアスで薄いシリコン酸化膜108を形成する。すなわち、プラズマイオンが追従できない周波数でシリコン酸化膜を形成することで、下地のトランジスタ等のゲ−ト酸化膜の界面準位の生成を抑えている。
【0006】
次に、図3(c)に示すように、イオンが追従できる400kHzの低周波数の基板バイアスを用いてシリコン酸化膜109を形成する。このように、基板にプラズマダメ−ジを避けるために、最初にプラズマダメ−ジを与えない高い周波数をバイアスして酸化膜を形成し、しかる後、プラズマイオンを引き込み厚い酸化膜で配線間を埋め込んでいる(特許文献1参照)。
【0007】
【特許文献1】
特開平11−154673号公報(第12頁−13頁、図1)
【0008】
【発明が解決しようとする課題】
上述した従来の半導体装置の製造方法では、イオンが追従できない高い周波数である基板バイアスを印加して薄い酸化膜を形成しているものの、プラズマ中の軽いイオンや電子を引き込む恐れがある。このため、引き込まれた電子や軽いイオンが半導体基板に衝突し、半導体基板の下地である酸化膜に削るだけではなくチャ−ジアップし、MOSトランジスタのゲ−ト酸化膜を破損させるという問題がある。
【0009】
また、配線間の隙間を層間絶縁膜で埋め込む際に、基板バイアスの周波数を変更しなければならず、作業上煩わしさがある。さらに、二つの高周波電源を必要とし設備コストが高くなるという欠点がある。
【0010】
従って、本発明の目的は、半導体基板上に形成される配線層の下地をプラズマイオンでキズ付けたり、下地にチャ−ジアップさせたりすることなく半導体基板上の配線間の隙間に層間絶縁膜を埋め込むことができる半導体装置の製造方法を提供することにある。
【0011】
【課題を解決するための手段】
本発明の特徴は、半導体基板に高周波電力を印加する高密度プラズマCVD法を用いて半導体装置の配線間の隙間に層間絶縁膜を埋め込む半導体装置の製造方法において、前記半導体基板上に絶縁膜を形成する工程と、前記絶縁膜上に導電層を形成する工程と、前記導電層をパタ−ニングにより配線を形成する工程と、しかる後前記絶縁層を含む前記配線上に保護絶縁膜を形成する工程とを含む半導体装置の製造方法である。
【0012】
また、前記保護絶縁膜を形成した後、前記配線の隙間を埋める層間絶縁膜を形成することが望ましい。さらに、前記保護絶縁膜の膜厚は、少なくとも20nmであることが望ましい。さらに、前記高密度プラズマCVD法は、誘導結合プラズマ発生装置を用いる高密度プラズマCVD法であることが望ましい。
【0013】
本発明の他の特徴は、絶縁膜が形成され該絶縁膜上に配線を有する半導体基板を載置するペデスタルを収納する反応室と、この反応室の頭頂部に配置される第1の誘導コイルと、前記反応室の側壁に配置される第2の誘導コイルと、前記反応室の頭頂部から反応ガスを導出するトップノズルと、前記反応室の側壁から反応ガスを導出するサイドノズルと、前記半導体基板に基板バイアスを印加する高周波電源とを備える誘導結合型プラズマCVD装置において、前記トップノズルから前記反応ガスを減圧された前記反応室に導出し、前記第1および第2の誘導コイルに高周波電力を印加させプラズマを発生させ、前記半導体基板に基板バイアスを印加させることなく前記配線を含む前記半導体基板の絶縁膜上に保護膜を形成する半導体装置の製造方法である。
【0014】
また、前記保護膜を形成した後に、前記トップノズルおよび前記サイドノズルから前記反応ガスを導出させ、前記第1および第2の誘導コイルに高周波電力を印加させプラズマを発生させ、前記半導体基板に基板バイアスを印加させ、前記半導体基板の配線の間を埋める層間絶縁膜を形成することが望ましい。
【0015】
【発明の実施の形態】
次に、本発明について図面を参照して説明する。
【0016】
図1は本発明の一実施の形態における半導体装置の製造方法を説明するための誘導結合型プラズマCVD装置の構成を示す模式断面図である。高密度プラズマCVD装置である誘導結合プラズマCVD装置は、図1に示すように、反応室1の頭頂部に配置される誘導コイル9と外側壁に巻かれる誘導コイル8を有している。また、反応ガスを反応室1に導入するトップノズル3およびサイドノズル2が配置されている。そして、誘導コイル8および誘導コイル9への高周波電源11および高周波電源10の高周波電力の印加と導入される反応ガスとによって、反応室1内にプラズマを発生させる。
【0017】
また、被処理基板であるウェハ20は、表面がセラミックなどでコ−ティングされたペデスタル4に静電吸着保持されている。そして、冷却ガス供給装置7からウェハ20の裏面に供給されるヘリウムによりウェハの上昇温度を抑えている。プラズマに加熱されても、例えば、ウェハ20の温度は摂氏350度に維持される。
【0018】
一方、反応室1に供給される反応ガスは、頭頂部にあるトップノズル3と側壁部にあるサイドノズル2から導入される。トップノズル3からはArおよびOならびにシランガス(SiH)が供給され、同様にサイドノズル2からもArおよびOならびにシランガス(SiH)が供給される。導入された反応ガスはタ−ボポンプ6で減圧されるが、圧力が放電し易い圧力になるようにスロットルバルブ13で調節される。
【0019】
プラズマを励起する誘導コイル9および誘導コイル8には、2MHzの高周波電力を印加する高周波電源10および高周波電源11が接続されている。一方、ペデスタル4を含む下部電極5には、基板バイアスとなる13.56MHzの高周波電源12が接続され、基板バイアスを印加することでプラズマ中のイオンを引き込む作用が生じる。この基板バイアスを印加することで、アルゴンイオンによるスパッタエッチングレ−トの傾斜角依存性を利用して、傾斜した部分のスパッタ率が高くなる。
【0020】
図2(a)〜(d)は本発明の一実施の形態における半導体装置の製造方法を説明するために工程順に示す断面図である。次に、図1と図2を参照して半導体装置の製造方法を説明する。
【0021】
まず、図2(a)に示すように、半導体基板21に酸化膜である絶縁膜22を形成し、その上に配線層を形成し、レジストを塗布しそれをマスクにし、配線層をパタ−ンニングし、図2(b)に示す配線23を形成する。この工程は、通常の平行平板型プラズマCVD装置やECRプラズマCVD装置でも実施できる。
【0022】
次に、図1の誘電結合型プラズマCVD装置のペデスタル4に半導体基板21を載置し、タ−ボポンプ6により反応室1を減圧する。反応室1が所定の圧力に到達したら、トップノズル3からArを16sccm、Oを45sccm、SiHを18sccmを反応室1に導出し、高周波電源11,10により高周波電力を誘導コイル8,9に印加させプラズマを発生させる。このことによりプラズマ中の電荷をもたないラジカルが、プラズマにより加熱された半導体基板に吸着反応し、図2(c)に示すように、絶縁膜22および配線23に薄いシリコン酸化膜である一様の厚さの保護膜24が形成される。
【0023】
なお、半導体基板に基板バイアスが印加されないので、プラズマ中のイオンを引き込むことがないので、絶縁膜22の損傷やゲ−ト酸化膜の破壊を起こすことはない。また、種々の実験からこの保護膜24の厚さは、薄くとも20nmは必要である。そして、この保護膜24の厚さに達する時間は、数秒で得られる。
【0024】
この保護膜24を形成した後、引き続き、トップノズル3からArを16sccm、Oを20sccm、SiHを9.5sccmを反応室1に導出し、サイドノズル2からArを110sccm、Oを120sccm、SiHを56sccmを反応室1に導出させ、高周波電力を誘導コイルに印加し、プラズマを発生させる。そして、半導体基板に基板バイアスとして高周波電源12により高周波電力、例えば、2000乃至3500Wを印加させる。
【0025】
このことにより、プラズマ中のイオンが引き込まれ、アルゴンイオンによるスパッタエッチングレ−トの傾斜角度依存性に伴って、デポジションとスパッタリングが同時に起き、図2(d)に示すように、配線23の間を層間絶縁膜25が埋め込むように形成される。また、プラズマによって加熱される半導体基板が温度上昇しないように、冷却ガス供給装置7からヘリウムガスを供給し、半導体基板を冷却し摂氏400度に維持している。
【0026】
こように層間絶縁膜25が形成した後、配線23の真上にあたる層間絶縁膜の突起は、CMPなどにより平坦に研磨する。
【0027】
【発明の効果】
以上説明したように本発明は、絶縁膜上に配線を有する半導体基板に前記配線を含む絶縁膜上に、基板バイアスを印加させることなく薄い保護膜を形成してから、層間絶縁膜を形成するので、下地である絶縁膜をプラズマダメ−ジや下地削れを起こすことなく層間絶縁膜を形成でき、品質の歩留まりが向上するといういう効果がある。
【図面の簡単な説明】
【図1】本発明の一実施の形態における半導体装置の製造方法を説明するための誘導結合型プラズマCVD装置の構成を示す断面図である。
【図2】本発明の一実施の形態における半導体装置の製造方法を説明するために工程順に示す断面図である。
【図3】従来の半導体装置の製造方法の一例を説明するための図である。
【符号の説明】
1  反応室
2  サイドノズル
3  トップノズル
4  ペデスタル
5  下部電極
6  タ−ボポンプ
7  冷却ガス供給装置
8,9  誘導コイル
10,11,12  高周波電源
13  スロットルバルブ
21  半導体基板
22  絶縁膜
23  配線
24  保護膜
25  層間絶縁膜
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which an interlayer insulating film of a semiconductor device is formed by using a high-density plasma CVD method for applying high-frequency power to a semiconductor substrate.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a wiring configuration in a semiconductor device due to miniaturization of circuit elements of the semiconductor device requires multilayer wiring. In addition, the distance between lines and the line width due to miniaturization are reduced. However, in order to avoid an increase in wiring resistance due to the miniaturization of the wiring, a certain wiring cross-sectional area is required.
[0003]
For this reason, the height of the wiring is increased and the actual resistance is reduced. However, in order to bury the interlayer insulating film in a wiring pattern having a high aspect ratio in which the distance between the wirings is narrow and the height of the wiring is high, for example, bias plasma CVD for applying a high frequency power to a silicon substrate has a good embedding property. The law is mainly used.
[0004]
3A to 3C are views for explaining an example of a conventional method for manufacturing a semiconductor device. This manufacturing method is a method of forming an interlayer insulating film on a metal wiring having a narrow or wide interval. First, as shown in FIG. 3A, an insulating film 102 is formed on the surface of a silicon substrate 101, and patterned lower wirings 107a to 107e are formed on the insulating film 102.
[0005]
Next, as shown in FIG. 3B, high-frequency power is applied to the silicon substrate 101, and a thin silicon oxide film 108 is formed by a high-density plasma method with a high substrate bias of 13.5 MHz. That is, by forming a silicon oxide film at a frequency that plasma ions cannot follow, generation of interface states of a gate oxide film of a base transistor or the like is suppressed.
[0006]
Next, as shown in FIG. 3C, a silicon oxide film 109 is formed by using a low-frequency substrate bias of 400 kHz that can follow ions. As described above, in order to avoid plasma damage on the substrate, an oxide film is first formed by biasing at a high frequency that does not cause plasma damage, and thereafter, plasma ions are drawn in and a thick oxide film is formed between the wirings. It is embedded (see Patent Document 1).
[0007]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 11-154673 (Pages 12-13, FIG. 1)
[0008]
[Problems to be solved by the invention]
In the above-described conventional method for manufacturing a semiconductor device, although a thin oxide film is formed by applying a substrate bias having a high frequency that cannot follow ions, there is a risk that light ions or electrons in the plasma may be attracted. For this reason, the drawn electrons and light ions collide with the semiconductor substrate, causing a problem that the gate oxide film of the MOS transistor is damaged, not only shaving the oxide film underlying the semiconductor substrate, but also charging up the oxide film. .
[0009]
Further, when the gap between the wirings is filled with the interlayer insulating film, the frequency of the substrate bias must be changed, which is troublesome in operation. Further, there is a disadvantage that two high-frequency power sources are required and the equipment cost is increased.
[0010]
Accordingly, an object of the present invention is to provide an interlayer insulating film in a gap between wirings on a semiconductor substrate without scratching the underlying layer of a wiring layer formed on the semiconductor substrate with plasma ions or charging up the underlying layer. An object of the present invention is to provide a method for manufacturing a semiconductor device which can be embedded.
[0011]
[Means for Solving the Problems]
A feature of the present invention is a method of manufacturing a semiconductor device in which an interlayer insulating film is buried in a gap between wirings of a semiconductor device by using a high-density plasma CVD method in which high-frequency power is applied to the semiconductor substrate, wherein the insulating film is formed on the semiconductor substrate. Forming, forming a conductive layer on the insulating film, forming a wiring on the conductive layer by patterning, and then forming a protective insulating film on the wiring including the insulating layer. And a method for manufacturing a semiconductor device.
[0012]
Further, it is preferable that after forming the protective insulating film, an interlayer insulating film that fills a gap between the wirings is formed. Further, the thickness of the protective insulating film is desirably at least 20 nm. Further, it is desirable that the high-density plasma CVD method is a high-density plasma CVD method using an inductively coupled plasma generator.
[0013]
Another feature of the present invention is that a reaction chamber for accommodating a pedestal on which an insulating film is formed and a semiconductor substrate having wiring on the insulating film is placed, and a first induction coil disposed at the top of the reaction chamber A second induction coil disposed on a side wall of the reaction chamber, a top nozzle for leading a reaction gas from a top of the reaction chamber, a side nozzle for leading a reaction gas from a side wall of the reaction chamber, In an inductively coupled plasma CVD apparatus including a high frequency power supply for applying a substrate bias to a semiconductor substrate, the reaction gas is led out from the top nozzle to the depressurized reaction chamber, and a high frequency is supplied to the first and second induction coils. A semiconductor device in which plasma is generated by applying power and a protective film is formed on an insulating film of the semiconductor substrate including the wiring without applying a substrate bias to the semiconductor substrate. It is a production method.
[0014]
Further, after forming the protective film, the reaction gas is led out from the top nozzle and the side nozzle, high-frequency power is applied to the first and second induction coils to generate plasma, and the substrate is formed on the semiconductor substrate. It is desirable to apply a bias to form an interlayer insulating film that fills the space between the wirings of the semiconductor substrate.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0016]
FIG. 1 is a schematic cross-sectional view showing a configuration of an inductively coupled plasma CVD apparatus for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the inductively coupled plasma CVD apparatus, which is a high-density plasma CVD apparatus, has an induction coil 9 arranged at the top of the reaction chamber 1 and an induction coil 8 wound around the outer wall. Further, a top nozzle 3 and a side nozzle 2 for introducing a reaction gas into the reaction chamber 1 are provided. Then, plasma is generated in the reaction chamber 1 by applying the high-frequency power of the high-frequency power supply 11 and the high-frequency power of the high-frequency power supply 10 to the induction coil 8 and the induction coil 9 and the introduced reaction gas.
[0017]
The wafer 20 as a substrate to be processed is electrostatically attracted and held on a pedestal 4 whose surface is coated with ceramic or the like. Then, the rising temperature of the wafer is suppressed by helium supplied from the cooling gas supply device 7 to the back surface of the wafer 20. Even when heated by the plasma, for example, the temperature of wafer 20 is maintained at 350 degrees Celsius.
[0018]
On the other hand, the reaction gas supplied to the reaction chamber 1 is introduced from the top nozzle 3 at the top and the side nozzle 2 at the side wall. From top nozzle 3 is supplied with Ar and O 2 and a silane gas (SiH 4), likewise Ar and O 2 and a silane gas from the side nozzle 2 (SiH 4) is supplied. The introduced reaction gas is depressurized by the turbo pump 6 and is adjusted by the throttle valve 13 so that the pressure becomes easily dischargeable.
[0019]
A high frequency power supply 10 and a high frequency power supply 11 for applying a high frequency power of 2 MHz are connected to the induction coil 9 and the induction coil 8 for exciting the plasma. On the other hand, a 13.56 MHz high frequency power supply 12 serving as a substrate bias is connected to the lower electrode 5 including the pedestal 4, and the action of attracting ions in the plasma is generated by applying the substrate bias. By applying this substrate bias, the sputter rate in the inclined portion is increased by utilizing the inclination angle dependence of the sputter etching rate due to argon ions.
[0020]
2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps for explaining the method. Next, a method for manufacturing a semiconductor device will be described with reference to FIGS.
[0021]
First, as shown in FIG. 2A, an insulating film 22 which is an oxide film is formed on a semiconductor substrate 21, a wiring layer is formed thereon, a resist is applied, and the resist is used as a mask, and the wiring layer is patterned. And the wiring 23 shown in FIG. 2B is formed. This step can also be performed by a general parallel plate type plasma CVD apparatus or ECR plasma CVD apparatus.
[0022]
Next, the semiconductor substrate 21 is placed on the pedestal 4 of the inductively coupled plasma CVD apparatus shown in FIG. 1, and the pressure in the reaction chamber 1 is reduced by the turbo pump 6. When the reaction chamber 1 reaches a predetermined pressure, 16 sccm of Ar, 45 sccm of O 2, and 18 sccm of SiH 4 are led out of the top nozzle 3 into the reaction chamber 1, and high-frequency power is supplied from the high-frequency power supplies 11 and 10 to the induction coils 8 and 9. To generate plasma. As a result, radicals having no charge in the plasma adsorb to the semiconductor substrate heated by the plasma, and as shown in FIG. 2C, a thin silicon oxide film is formed on the insulating film 22 and the wiring 23. A protective film 24 having a similar thickness is formed.
[0023]
Since no substrate bias is applied to the semiconductor substrate, ions in the plasma are not drawn in, so that the insulating film 22 is not damaged and the gate oxide film is not broken. From various experiments, it is necessary that the thickness of the protective film 24 be at least 20 nm. The time required to reach the thickness of the protective film 24 is obtained in a few seconds.
[0024]
After forming the protective film 24, 16 sccm of Ar, 20 sccm of O 2 , 9.5 sccm of SiH 4 were led out to the reaction chamber 1 from the top nozzle 3, and 110 sccm of Ar and 120 sccm of O 2 were introduced from the side nozzle 2. , SiH 4 is led out to the reaction chamber 1 at 56 sccm, and high-frequency power is applied to the induction coil to generate plasma. Then, high frequency power, for example, 2000 to 3500 W is applied to the semiconductor substrate by the high frequency power supply 12 as a substrate bias.
[0025]
As a result, ions in the plasma are attracted, and deposition and sputtering occur simultaneously with the inclination angle dependence of the sputter etching rate due to the argon ions. As shown in FIG. The interlayer insulating film 25 is formed so as to fill the space. Further, a helium gas is supplied from the cooling gas supply device 7 so that the semiconductor substrate heated by the plasma does not rise in temperature, and the semiconductor substrate is cooled and maintained at 400 degrees Celsius.
[0026]
After the formation of the interlayer insulating film 25, the protrusion of the interlayer insulating film immediately above the wiring 23 is polished flat by CMP or the like.
[0027]
【The invention's effect】
As described above, the present invention forms a thin protective film on a semiconductor substrate having wiring on an insulating film on an insulating film including the wiring without applying a substrate bias, and then forms an interlayer insulating film. Therefore, an interlayer insulating film can be formed on the underlying insulating film without causing plasma damage or undercutting of the underlying film, and the yield of quality is improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of an inductively coupled plasma CVD apparatus for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps for describing the method.
FIG. 3 is a diagram illustrating an example of a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
Reference Signs List 1 reaction chamber 2 side nozzle 3 top nozzle 4 pedestal 5 lower electrode 6 turbo pump 7 cooling gas supply device 8, 9 induction coil 10, 11, 12 high frequency power supply 13 throttle valve 21 semiconductor substrate 22 insulating film 23 wiring 24 protective film 25 Interlayer insulating film

Claims (6)

半導体基板に高周波電力を印加する高密度プラズマCVD法を用いて半導体装置の配線間の隙間に層間絶縁膜を埋め込む半導体装置の製造方法において、前記半導体基板上に絶縁膜を形成する工程と、前記絶縁膜上に導電層を形成する工程と、前記導電層をパタ−ニングにより配線を形成する工程と、しかる後前記絶縁層を含む前記配線上に保護絶縁膜を形成する工程とを含むことを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device in which an interlayer insulating film is buried in a gap between wirings of a semiconductor device by using a high-density plasma CVD method of applying high-frequency power to a semiconductor substrate; Forming a conductive layer on an insulating film, forming a wiring on the conductive layer by patterning, and then forming a protective insulating film on the wiring including the insulating layer. A method for manufacturing a semiconductor device. 前記保護絶縁膜を形成した後、前記配線の隙間を埋める層間絶縁膜を形成することを特徴とする請求項1記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein after forming the protective insulating film, an interlayer insulating film filling a gap between the wirings is formed. 前記保護絶縁膜の膜厚は、少なくとも20nmであることを特徴とする請求項1または請求項2記載の半導体装置の製造方法。3. The method according to claim 1, wherein the thickness of the protective insulating film is at least 20 nm. 前記高密度プラズマCVD法は、誘導結合プラズマ発生装置を用いる高密度プラズマCVD法であることを特徴とする請求項1、請求項2または請求項3記載の半導体装置の製造方法。4. The method according to claim 1, wherein the high-density plasma CVD is a high-density plasma CVD using an inductively coupled plasma generator. 絶縁膜が形成され該絶縁膜上に配線を有する半導体基板を載置するペデスタルを収納する反応室と、この反応室の頭頂部に配置される第1の誘導コイルと、前記反応室の側壁に配置される第2の誘導コイルと、前記反応室の頭頂部から反応ガスを導出するトップノズルと、前記反応室の側壁から反応ガスを導出するサイドノズルと、前記半導体基板に基板バイアスを印加する高周波電源とを備える誘導結合型プラズマCVD装置において、前記トップノズルから前記反応ガスを減圧された前記反応室に導出し、前記第1および第2の誘導コイルに高周波電力を印加させプラズマを発生させ、前記半導体基板に基板バイアスを印加させることなく前記配線を含む前記半導体基板の絶縁膜上に保護膜を形成することを特徴とする半導体装置の製造方法。A reaction chamber for housing a pedestal on which an insulating film is formed and on which a semiconductor substrate having wirings is mounted, a first induction coil disposed at the top of the reaction chamber, and a side wall of the reaction chamber. A second induction coil disposed, a top nozzle for leading a reaction gas from the top of the reaction chamber, a side nozzle for leading a reaction gas from a side wall of the reaction chamber, and applying a substrate bias to the semiconductor substrate In an inductively coupled plasma CVD apparatus having a high frequency power supply, the reaction gas is led out from the top nozzle to the depressurized reaction chamber, and high frequency power is applied to the first and second induction coils to generate plasma Forming a protective film on an insulating film of the semiconductor substrate including the wiring without applying a substrate bias to the semiconductor substrate. Law. 前記保護膜を形成した後に、前記トップノズルおよび前記サイドノズルから前記反応ガスを導出させ、前記第1および第2の誘導コイルに高周波電力を印加させプラズマを発生させ、前記半導体基板に基板バイアスを印加させ、前記半導体基板の配線の間を埋める層間絶縁膜を形成することを特徴とする請求項5記載の半導体装置の製造方法。After forming the protective film, the reaction gas is led out from the top nozzle and the side nozzle, high-frequency power is applied to the first and second induction coils to generate plasma, and a substrate bias is applied to the semiconductor substrate. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the interlayer insulating film is formed so as to fill between the wirings of the semiconductor substrate by applying the voltage.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041505A (en) * 2004-07-22 2006-02-09 Hynix Semiconductor Inc Method of forming passivation layer of semiconductor device
JP2006128615A (en) * 2004-10-28 2006-05-18 Hynix Semiconductor Inc High density plasma chemical vapor deposition apparatus and manufacturing method of semiconductor element using it
JP2006237479A (en) * 2005-02-28 2006-09-07 Mitsubishi Heavy Ind Ltd Plasma processing apparatus
US9171734B1 (en) 2014-08-25 2015-10-27 Hitachi Kokusai Electric Inc. Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium
US9287346B2 (en) 2012-01-26 2016-03-15 Samsung Electronics Co., Ltd. Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041505A (en) * 2004-07-22 2006-02-09 Hynix Semiconductor Inc Method of forming passivation layer of semiconductor device
JP2006128615A (en) * 2004-10-28 2006-05-18 Hynix Semiconductor Inc High density plasma chemical vapor deposition apparatus and manufacturing method of semiconductor element using it
JP2006237479A (en) * 2005-02-28 2006-09-07 Mitsubishi Heavy Ind Ltd Plasma processing apparatus
US9287346B2 (en) 2012-01-26 2016-03-15 Samsung Electronics Co., Ltd. Semiconductor device
US9171734B1 (en) 2014-08-25 2015-10-27 Hitachi Kokusai Electric Inc. Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium
JP5840268B1 (en) * 2014-08-25 2016-01-06 株式会社日立国際電気 Substrate processing apparatus, semiconductor device manufacturing method, and recording medium
KR20160024713A (en) * 2014-08-25 2016-03-07 가부시키가이샤 히다치 고쿠사이 덴키 Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer readable recording medium
KR101665373B1 (en) * 2014-08-25 2016-10-24 가부시키가이샤 히다치 고쿠사이 덴키 Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer readable recording medium

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