JP2004139361A - Direct memory access device and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To elongate a bus occupying time on the side of a host CPU by holding read access on the side of the host CPU during read access on the side of an external device and transferring downloaded data directly to the side of the host CPU. <P>SOLUTION: When a DMA request signal DREQ is active and an empty flag FLG is active, DMA read access is performed and data read from an external device 13 is stored in a data buffer 21. Thereby, the data is firstly read from the external device 13 without waiting for a DMA enabling signal DACK from the host CPU 11, and then read request is performed on the host CPU 11 when the empty flag FLG is inactive, the data in the data buffer 21 is transferred to the side of the host CPU 11 in response to read from the host CPU 11, and the empty flag FLG is asserted. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a direct memory access (DMA) device and a control method thereof, and more particularly to a direct memory access device having a DMA interface (I / F) interposed between a host CPU and an external device and a control method thereof. .
[0002]
[Prior art]
Conventionally, as shown in FIG. 6, an external device 103 is provided outside a chip on which a host CPU 101 and a DMA controller 192 are mounted, and data transfer is performed via a DMA interface 104 interposed between the host CPU 101 and the external device 103. In the direct memory access apparatus performing the read operation, when the external device 103 performs a read access, the read access of the host CPU 101 is held and the data fetched from the external device 103 is directly transferred to the host CPU 101 (for example, see Patent Reference 1). FIG. 7 shows the operation timing.
[0003]
[Patent Document 1]
JP-A-7-21118
[Problems to be solved by the invention]
However, in the direct memory access apparatus according to the above-described conventional example, the data bus 105 of the host CPU 101 is occupied during the read access of the external device 103, so that the read access of the external device 103 is completed. However, there is a problem that the data bus 105 of the host CPU 101 cannot be used.
[0005]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a direct memory access device capable of greatly reducing the occupation time of a data bus on a host CPU side during a read access on an external device side. And a control method therefor.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a host CPU, an external device provided outside a chip on which the host CPU is mounted, and a DMA interface interposed between the host CPU and the external device are provided. In a direct memory access apparatus provided with a DMA interface, a buffer for temporarily storing data and a flag generation means for generating an empty flag indicating whether or not the buffer is empty are provided in a DMA interface, and a DMA request signal from an external device is provided. Is active and the empty flag is active, fetches data from an external device and stores it in the buffer, then makes a read request to the host CPU when the empty flag is inactive, Data in the buffer when And transferred to the CPU side and asserts the empty flag.
[0007]
By performing the above processing at the time of read access of the external device, the data is read from the external device and stored in the buffer without waiting for the DMA permission signal from the host CPU at the time of the read access of the external device. In other words, data can be read ahead from an external device. Therefore, the occupation time of the data bus on the host CPU side during read access on the external device side can be greatly reduced. Further, by pre-reading the data in advance, the data transfer time can be reduced in the case of continuous read access or the like.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0009]
[First Embodiment]
FIG. 1 is a block diagram showing a configuration example of the direct memory access device according to the first embodiment of the present invention. As is clear from FIG. 1, the direct memory access device according to the present embodiment has a configuration including a host CPU 11, a DMA controller 12, an external device 13, and a DMA interface (I / F) 14. Here, the external device 13 is a memory circuit provided outside the chip on which the host CPU 11 is mounted.
[0010]
The DMA interface 14 has a configuration including a data buffer 21, an empty (Empty) flag generator 22, and a DMA timing generator 23. The data buffer 21 is provided for temporarily storing data read from the external device 13 at the time of read access on the external device 13 side.
[0011]
The empty flag generation unit 22 monitors whether the data buffer 21 is empty (Empty). When the data buffer 21 is empty, the empty flag generation unit 22 becomes active (for example, high level when positive logic), and becomes full (Full). An empty flag FLG that is inactive at some time (for example, low level when the logic is positive) is generated. The DMA interface 14 generates a timing signal required for data transfer under the control of the DMA controller 12 when performing DMA data transfer between the host CPU 11 and the external device 13.
[0012]
Here, the operation clock used by the host CPU 11 and the operation clock used by the DMA interface 14 are synchronized. As an example, both the host CPU 11 and the DMA interface 14 use the same operation clock CLK. The DMA request signal DREQ input from the external device 13 to the DMA interface 14 is a level type signal for issuing a DMA request over the input period, that is, a level input signal.
[0013]
Next, the operation of the DMA interface 14 in the direct memory access device according to the first embodiment having the above configuration will be described with reference to the timing chart of FIG.
[0014]
When the DMA request signal DREQ input from the external device 13 is active and the empty flag FLG generated by the empty flag generator 22 is active, that is, when the data buffer 21 becomes empty, the DMA interface 14 Without waiting for the DMA permission signal DACK, the DMA controller returns the DMA permission signal DACK to the external device 13 to generate a read access to the external device 13, fetches data from the external device 13 and stores it in the data buffer 21.
[0015]
When the empty flag FLG is inactive, that is, when the data buffer 21 is full (Full), a DMA read request is issued to the host CPU 11. Then, when data is read from the host CPU 11, the data in the data buffer 21 is transferred to the host CPU 11 and the empty flag FLG is asserted (activated).
[0016]
As described above, in the direct memory access device in which the operation clock of the host CPU 11 and the operation clock of the DMA interface 14 are synchronized and the DMA request signal DREQ is level-input, the DMA request signal DREQ is active and the empty flag FLG is set. When active, DMA read access is performed and data read from the external device 13 is stored in the data buffer 21. When the empty flag FLG is inactive, a read request is issued to the host CPU 11. By transferring the data in the data buffer 21 to the host CPU 11 and asserting the empty flag FLG, data from the external device 13 can be read first without waiting for the DMA permission signal DACK from the host CPU 11. It is possible to Misr, can greatly reduce the time occupied by host CPU11 side of the data bus 15 at the time of the external device 13 side of the read access.
[0017]
In addition, at the time of read access of the external device 13, the data fetched from the external device 13 is not directly transferred to the host CPU 11, but instead of waiting for the DMA permission signal DACK from the host CPU 11, the DMA By returning DACK and prefetching data in advance, that is, by reading data from the external device 13 and storing it in the data buffer 21, there is also an advantage that the data transfer time can be reduced in the case of continuous read access or the like. .
[0018]
In the present embodiment, an example has been described in which the DMA request signal DREQ is a level input signal in a direct memory access device in which the operation clock of the host CPU 11 and the operation clock of the DMA interface 14 are synchronized. The present invention is also applicable to a pulse type signal that issues a DMA request at the timing when the DMA request signal DREQ is input, that is, a pulse input signal.
[0019]
In a direct memory access device in which the operation clock of the host CPU 11 and the operation clock of the DMA interface 14 are synchronized, when the DMA request signal DREQ is pulse input, as shown in the timing chart of FIG. The read access is started at the rising timing of the data request signal DREQ when the empty flag FLG is active. However, there is no activation only by the empty flag FLG.
[0020]
[Second embodiment]
FIG. 4 is a block diagram showing a configuration example of a direct memory access device according to the second embodiment of the present invention. In the drawing, the same parts as those in FIG. 1 are denoted by the same reference numerals.
[0021]
In the direct memory access device according to the present embodiment, the operation clock of the host CPU 11 and the operation clock of the DMA interface 14 are asynchronous, and the level of the DMA request signal DREQ is input. Here, the operation clock of the DMA interface 14 is CLK1, and the operation clock of the host CPU 11 is CLK2. As the operation clock on the host CPU 11 side and the operation clock on the DMA interface 14 side are asynchronous, the DMA interface 14 sets the data buffer 21 and the empty flag generation unit 22 for both CLK1 and CLK2, respectively. The prepared structure is adopted.
[0022]
That is, the DMA interface 14 includes, as the data buffer 21 and the empty flag generation unit 22, the first data buffer 21-1 and the first empty flag generation unit 22-1 operated by the operation clock CLK 1 on the DMA interface 14 side, and the host CPU 11. It has a second data buffer 21-2 and a second empty flag generation unit 22-2 that operate with the operation clock CLK2 on the side. The configuration other than the DMA interface 14 is the same as that of the direct memory access device according to the first embodiment.
[0023]
Next, the operation of the DMA interface 14 in the direct memory access device according to the second embodiment having the above configuration will be described with reference to the timing chart of FIG.
[0024]
When the DMA request signal DREQ from the external device 15 is active and the first empty flag FLG1 generated by the first empty flag generator 22-1 is active, that is, when the data buffer 21-1 becomes empty, the host CPU 11 Without waiting for the DMA permission signal DACK of the external device 13, a DMA read access to the external device 13 is generated by returning the DMA permission signal DACK to the external device 13, and the data is fetched from the external device 13 to acquire the data buffer. 21-1 and negates the first empty flag FLG (inactivates it).
[0025]
Next, when the first empty flag FLG1 is inactive and the second empty flag FLG2 generated by the second empty flag generator 22-2 is active, that is, when the second empty flag generator 22-2 is empty, the first Data is transferred from the data buffer 21-1 to the second data buffer 21-2, the first empty flag FLG1 is asserted (activated), and the second empty flag FLG2 is negated.
[0026]
When the first data buffer 21-1 becomes empty and the first empty flag FLG1 is asserted, read access to the external device 13 is performed. By this read access, data is fetched from the external device 13 and stored in the data buffer 21-1, and when the second empty flag generator 22-2 is empty, the first data buffer 21-1 to the second data buffer 21- 2 is repeated.
[0027]
On the other hand, when the second empty flag FLG2 is inactive, that is, when it is Full, a read request is issued to the host CPU 11, and when data is read from the host CPU 11, the data in the second data buffer 21-2 is transferred to the host CPU 11 side. To assert the second empty flag FLG2. After the data in the second data buffer 21-2 is transferred to the host CPU 11, when the first empty flag FLG1 is inactive and the second empty flag FLG2 is active, the second data from the first data buffer 21-1 is transmitted. The data is transferred to the buffer 21-2.
[0028]
As described above, the DMA interface 14 prepares the data buffers 21 (21-1 and 21-2) and the empty flag generators 22 (22-1 and 22-2) for the operation clocks CLK1 and CLK2, respectively. Then, at the time of read access of the external device 13, data is read ahead from the external device 13 and relayed by the data buffers 21-1 and 21-2 without waiting for the DMA permission signal DACK from the host CPU 11, Even when the operation clock of the host CPU 11 and the operation clock of the DMA interface 14 are asynchronous, the occupation of the data bus 15 of the host CPU 11 at the time of read access of the external device 13 is the same as in the case of synchronization. Time can be greatly reduced and continuous read access etc. If, it is possible to shorten the transfer time of the data.
[0029]
【The invention's effect】
As described above, according to the present invention, at the time of read access on the external device side, data can be pre-read from the external device without waiting for the DMA permission signal from the host CPU. The occupation time of the data bus can be significantly reduced, and the data transfer time can be reduced in the case of continuous read access or the like.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a direct memory access device according to a first embodiment of the present invention.
FIG. 2 is a timing chart in the case of a level input in the direct memory access device according to the first embodiment.
FIG. 3 is a timing chart in the case of pulse input in the direct memory access device according to the first embodiment.
FIG. 4 is a block diagram illustrating a configuration example of a direct memory access device according to a second embodiment of the present invention.
FIG. 5 is a timing chart for a level input in a direct memory access device according to a second embodiment.
FIG. 6 is a block diagram showing a conventional example of a direct memory access device.
FIG. 7 is a timing chart of a direct memory access device according to a conventional example.
[Explanation of symbols]
11 Host CPU, 12 DMA Controller, 13 External Device, 14 DMA Interface (I / F), 21, 21-1, 21-2 Data Buffer, 22, 22-1, 22-2 Empty Flag Generation unit, 23: DMA timing generation unit

Claims (11)

A host CPU;
An external device provided outside the chip on which the host CPU is mounted;
A DMA (Direct Memory Access) interface interposed between the host CPU and the external device;
The DMA interface comprises:
A buffer for temporarily storing data,
Flag generating means for generating an empty flag indicating whether the buffer is empty,
When the DMA request signal from the external device is active and the empty flag is active, data is fetched from the external device and stored in the buffer. When the empty flag is inactive, a read request is issued to the host CPU. And transferring the data in the buffer to the host CPU in response to a read from the host CPU and asserting the empty flag. 2. The direct memory access device according to claim 1, wherein the DMA request signal is a level type signal for issuing a DMA request over an input period. 2. The direct memory access device according to claim 1, wherein the DMA request signal is a pulse type signal that issues a DMA request at an input timing. 2. The direct memory access device according to claim 1, wherein an operation clock of the host CPU and an operation clock of the DMA interface are asynchronous. The buffer and the flag generator include a first buffer and a first flag generator that operate with an operation clock of the DMA interface, and a second buffer and a second flag generator that operate with an operation clock of the host CPU. Consisting of
The DMA interface comprises:
When a DMA request signal from the external device is active and a first empty flag generated by the first flag generation means is active, data is fetched from the external device and stored in the first buffer, and Negate the empty flag,
When the first empty flag is inactive and the second empty flag generated by the second flag generating means is active, data is transferred from the first buffer to the second buffer, Asserting an empty flag and negating said second empty flag;
5. The direct memory access device according to claim 4, wherein when a read is made from the host CPU, the data in the second buffer is transferred to the host CPU and the second empty flag is negated. The DMA interface, after transferring data from the first buffer to the second buffer, when asserting the first empty flag, fetches data from the external device and stores the data in the first buffer, 6. The direct memory access device according to claim 5, wherein when the second empty flag is active, data is transferred from the first buffer to the second buffer. After transferring the data of the second buffer to the host CPU side, the DMA interface transfers the data from the first buffer to the second buffer when the first empty flag is inactive and the second empty flag is active. 6. The direct memory access device according to claim 5, wherein data is transferred to the direct memory access device. A host CPU, an external device provided outside the chip on which the host CPU is mounted, and a buffer interposed between the host CPU and the external device for temporarily storing data and the buffer being empty. A direct memory access (DMA) interface having flag generation means for generating an empty flag indicating whether or not an
When the DMA request signal from the external device is active and the empty flag is active, fetch data from the external device and store it in the buffer;
When the empty flag is inactive, a read request is made to the host CPU, and when there is a read from the host CPU, the data in the buffer is transferred to the host CPU and the empty flag is asserted. A method for controlling a direct memory access device. A first buffer in which the operation clock of the host CPU and the operation clock of the DMA interface are asynchronous with each other, and the buffer and the flag generation unit operate with the operation clock of the DMA interface; In the case of comprising a first flag generating means, a second buffer and a second flag generating means operating on the operation clock of the host CPU,
When a DMA request signal from the external device is active and a first empty flag generated by the first flag generation means is active, data is fetched from the external device and stored in the first buffer, and Negate the empty flag,
Next, when the first empty flag is inactive and the second empty flag generated by the second flag generating means is active, data is transferred from the first buffer to the second buffer, Asserting one empty flag and negating said second empty flag;
Next, when the second empty flag is inactive, a read request is made to the host CPU, and when a read is made from the host CPU, the data in the second buffer is transferred to the host CPU and 9. The control method for a direct memory access device according to claim 8, wherein an empty flag is asserted. After the data is transferred from the first buffer to the second buffer, when the first empty flag is asserted, data is fetched from the external device and stored in the first buffer, and the second empty flag is stored. 10. The method according to claim 9, wherein data is transferred from the first buffer to the second buffer when is active. After transferring the data in the second buffer to the host CPU, when the first empty flag is inactive and the second empty flag is active, the data is transferred from the first buffer to the second buffer. 10. The method for controlling a direct memory access device according to claim 9, wherein:

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