JP2004139260A - Command processing system by multiprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the bottle neck of a microprocessor in the interface part of a disk controller, and to prevent the performance deterioration of a storage system due to the disk controller. <P>SOLUTION: This interface part is provided with an external I/F transmitting/receiving part 101 connected to a high order host server, a microprocessor part having microprocessors 113 and 116 for processing commands from the high order host server and a command control circuit 121 interposed between the external I/F transmitting/receiving part and the microprocessor part. The plurality of microprocessor parts 111 and 114 are connected to the command control circuit 121, and the command control circuit is provided with a multiplex write function for transferring commands to a plurality of microprocessor parts simultaneously at one time, and the commands from the high order host server are distributed to the respective microprocessors so as to be processed by the multiplex write function. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a command processing distribution method for transferring a command issued from a higher-level information processing device to a storage device to a plurality of microprocessors by a multiplex write function and performing command processing smoothly.
[0002]
[Prior art]
FIG. 5 is a diagram showing an overall configuration of data transfer including a host computer, DKC, and DKU according to the related art. In FIG. 5, a DKC (disk controller) for controlling data transfer processing interposed between an upper host server and a DKU (disk unit) as a disk unit of the storage device forms an interface unit with the upper host server. (Channel adapter), CACHE (cache), and DKA (disk adapter) forming an interface with the DKU.
[0003]
As shown in FIG. 5, the CHA includes an external I / F transmission / reception unit 501, a command control circuit 521, a data transfer control unit 531 and a microprocessor unit 511. Although one microprocessor control circuit 512 and one microprocessor 513 are shown in the microprocessor part 511 in FIG. 5, a plurality of the microprocessor parts 511 may be connected.
[0004]
In the prior art shown in FIG. 5, a series of data transfer is performed between the host server and the DKU via the CHA which is the interface unit of the DKC. At this time, even if the CHA as the interface unit has one or two microprocessors for command processing as shown in FIG. , That is, a series of command processing until the data transfer end status is returned to the host server, is executed by the one microprocessor.
[0005]
Further, the system processing time can be shortened by the multiprocessor processing method in the prior art. The common program includes two processors in a master-slave relationship and a shared memory, and a common program executable by each processor is included in the memory. It is disclosed that the amount of parallel processing of each processor is made substantially equal by changing the execution distribution of the program.
[0006]
[Patent Document 1]
JP-A-5-28120
[Problems to be solved by the invention]
According to the above-described conventional technology, the microprocessor is unable to operate the interface unit (CHA) because many I / O requests are issued from the higher-level host server or a certain command processing takes time to fall into some busy state. As a bottleneck, commands may be queued (the command may be received and stored in a large amount that cannot be processed) or retried. In such a situation, the performance of the storage system may be degraded due to the DKC.
[0008]
Further, according to Patent Document 1, the system processing time is reduced based on a structural constraint that the two processors are in a master-slave relationship and have a shared memory loaded with a common program. However, there is an inconvenience that it cannot be applied to a RAID (Redundant Arrays Inexpensive Disks: DKC + DKU) interface unit using a general-purpose processor or memory.
[0009]
An object of the present invention is to reduce a bottleneck of a microprocessor in an interface section of a disk controller (DKC), and to prevent a decrease in performance of a storage system due to a disk controller.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, the present invention mainly employs the following configuration. An external I / F transmission / reception unit connected to an upper host server, a microprocessor unit having a microprocessor for processing a command issued from the upper host server, and an external I / F transmission unit and the microprocessor unit. A command control circuit interposed between the command control circuit and an interface unit of the storage device,
A plurality of microprocessor units are connected to the command control circuit,
The command control circuit has a multiplex write function of simultaneously transferring a command from the upper host server to the plurality of microprocessor units at a time, and the multiplex write function of the command control circuit allows A command processing method that distributes commands to each microprocessor and processes them.
[0011]
By adopting this configuration, the command processing issued from the host server can be load-balanced among the microprocessors, and the bottleneck by the microprocessors can be reduced.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
A command processing distribution method by a multiprocessor according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a specific configuration of a CHA (channel adapter) which is an interface unit with an upper-level host server according to an embodiment of the present invention, and FIG. 2 is a diagram showing two processors in the CHA according to the embodiment of the present invention. FIG. 3 is a diagram showing a temporal progress of a command phase in two processors according to the present embodiment in comparison with a conventional technique. FIG. 4 is a diagram showing a specific configuration of a CHA (channel adapter) which is an interface unit with a higher-level host server according to another embodiment of the present invention.
[0013]
The configuration shown in FIG. 1 shows a part that performs command control of an interface unit (channel adapter (CHA)) of a disk device that is an interface with an upper-level host server. The external I / F transmission / reception unit 101 includes an external I / F transmission / reception circuit 102 and an external I / F protocol control circuit 103. The microprocessor parts 111 and 114 are composed of microprocessors 113 and 116 and microprocessor control circuits 112 and 115. The external I / F transmission / reception circuit 102 is a higher-level interface circuit connected to a higher-level host server. The external I / F protocol control circuit 103 is a circuit for converting information received by the external I / F transmission / reception circuit 102 into a CHA internal interface signal.
[0014]
The microprocessors 113 and 116 process commands issued from the host server. The microprocessor control circuits 112 and 115 are circuits for converting transmission / reception information of the microprocessors 113 and 116 into CHA internal interface signals. The command control circuit 121 is a circuit having an interface between the external I / F protocol control circuit 103 and the microprocessor control circuits 112 and 115. The command control circuit 121 has a function of multiplexing writing to each of the microprocessors 113 and 116. The external I / F transmission / reception circuit 102 transfers the command received from the host server to the microprocessors 113 and 116. Here, the multiplex write function is a function of simultaneously transmitting information transmitted by a single command from the host server to a plurality of microprocessors at once.
[0015]
One feature of the embodiment of the present invention is that the command control circuit has a multiplex write function for simultaneously transferring commands to a plurality of microprocessors at once. Generally speaking, when performing a series of data transfer, a phase occurs in which various types of information are exchanged between an initiator (for example, a higher-order command device) and a target (disk device). In an embodiment of the present invention, the information exchange processing of the various phases in the target is distributed to and executed by a plurality of microprocessors. Details of the multiplex write function described above will be described below. Actually, in FIG. 1, the command control circuit 121 transfers the command received from the host server to the microprocessors 113 and 116 by the external I / F transmission / reception circuit 102 using the multiplex write function, and the command is processed. An example of the procedure will be described.
[0016]
When a certain command (for example, WRITE, READ, etc.) is instructed from the upper host server, processing contents of the command execution are transmitted as a plurality of command phases in order to execute the command. For example, it is assumed that the following four command phases are transmitted from the host server.
[0017]
(1) Initiator selects target,
(2) The initiator transfers a command indicating the transfer mode,
(3) the initiator transfers data transfer parameters such as a data transfer start address for data transfer and the number of data block transfers;
(4) The initiator issues a transfer instruction indicating an instruction to start data transfer.
[0018]
These four command phases are received by the external I / F transmission / reception circuit 102, converted into an internal interface signal of CHA (channel adapter) by the external I / F protocol control circuit 103, passed through the command control circuit 121, and controlled by the microprocessor. The signals are processed by the microprocessors 113 and 116 via the circuits 112 and 115.
[0019]
These four command phases are transferred to all the microprocessors (113 and 116 in the present embodiment) by the multiplex write function of the command control circuit 121. When passing through the command control circuit 121, for example, the command phases 1 and 2 are transferred. 3 is processed by the microprocessor 113, and the command phases 2 and 4 are processed by the microprocessor 116, so that the microprogram on the command control circuit 121 adds a certain flag to each command phase. , 116.
[0020]
Next, the processing of the command phase transferred to each of the microprocessors 113 and 116 will be described. In the present embodiment, first, the microprocessor 113 executes the processing of the command phase 1 based on the flag added when the command phase is transferred to each of the microprocessors 113 and 116 by the command control circuit 121. The initiator selects a target. For this command phase 1, the target returns to the initiator that it has been selected. At the same time, the fact that the command phase 1 has been processed is similarly reported to the microprocessor 116.
[0021]
The microprocessor 116 receiving the report that the command phase 1 has been processed executes the processing of the command phase 2. In response to this command phase 2, the target returns to the initiator that it has grasped the transfer mode. At the same time, the fact that the command phase 2 has been processed is similarly reported to the microprocessor 113. The microprocessor 113 that has received the report that the command phase 2 has been processed executes the processing of the command phase 3.
[0022]
In response to the command phase 3, the target returns to the initiator that the data transfer parameter has been received. At the same time, the fact that the command phase 3 has been processed is similarly reported to the microprocessor 116. The microprocessor 116 receiving the report that the command phase 3 has been processed executes the processing of the command phase 4.
[0023]
For this command phase 4, the target requests the initiator to transfer data, and the data transfer is started. At the same time, the fact that command phase 4 has been processed is similarly reported to the microprocessor 113, and the microprocessor 113 is notified that all command phases have been processed. As described above, in the present embodiment, the command processing has been described using four command phases as an example. However, even when there are five or more command phases, the command processing is performed in the same procedure.
[0024]
As described above, by performing the command processing in the above-described procedure using two microprocessors, one microprocessor is ready to execute the command phase, and one microprocessor is ready to execute the command phase. As soon as the completion of the processing of the command phase is received, the command processing can be performed immediately, and the overhead for shifting to the next command phase processing when a series of command processing is executed by one microprocessor can be eliminated.
[0025]
The command processing distribution method according to the embodiment of the present invention described above will be described again with reference to FIGS. In the embodiment of the present invention, the load of the microprocessor can be distributed by performing the multiplex write, and the write to another address can be performed through a plurality of microprocessors in one transfer command. There are features of the invention. Here, there are various specific methods of command processing based on multiplex writing, and the method is entrusted to the microprogram on the command control circuit (in the above example, the microprocessor 113 processes the command phases 1 and 3). , The microprocessor 116 processes the command phases 2 and 4). In short, in the present embodiment, the command control circuit is provided with hardware called a multiplex write function as a mechanism for efficiently operating a plurality of microprocessors (multiprocessors).
[0026]
FIG. 2 is a flowchart showing an example of a state of data exchange between the upper host server and the disk device interface unit (CHA) up to the data transfer in one data transfer by a command from the upper host server. I have. First, when, for example, a write (WRITE) instruction is issued by the upper host server (step 1), the command is received in the CHA, and the command is transferred to the microprocessors 113 and 116 by the multiplex write function of the command control circuit 121. (Step 2). At this time, which microprocessor is to execute the command phase is determined by adding a flag by a microprogram on the command control circuit 121.
[0027]
Next, the microprocessor 113 processes the command phase 1 and notifies the end report (see the arrow in the upper part of FIG. 3). At the same time, the microprocessor 116 processes the command phase 2 (step 3). Thereafter, the microprocessor 113 processes the command phase 3, the microprocessor 116 receives the end report of the command phase 1, and executes the processing of the command phase 2 (remaining processing) that can be processed only after the end of the command phase 1 ( In the period T in the middle part of FIG. 3), the end report of the command phase 2 is notified (step 4) (see the arrow in the middle part of FIG. 3).
[0028]
Next, the microprocessor 113 receives the end report of the command phase 2, executes the remaining processing of the command phase 3, and notifies the end report. At the same time, the microprocessor 116 processes the command phase 4 (step 5). Subsequently, the microprocessor 116 receives the end report of the command phase 3, executes the remaining processing of the command phase 4, and notifies the end report of the command phase 4 (step 6).
[0029]
FIG. 3 shows a comparison between the multiplex write according to the present embodiment and the prior art. As can be seen from this drawing, in the present embodiment, the control by the microprogram on the command control circuit is combined. The command can be transferred to a plurality of (for example, two) microprocessors at one time, and can be processed in parallel, thereby shortening the command processing time, and also leading to a load distribution of the microprocessors. In the prior art, the processing of the next command phase must be performed after the completion of each command phase, and there is a problem in the command processing time and the microprocessor load.
[0030]
On the other hand, in the above-described processing of the command phase by the microprocessors 113 and 116 shown in FIG. 2, there are cases where it is better to transmit an end report to the other microprocessor and cases where it is not necessary to transmit the end report. It depends on how the command is processed. As described above, when each command phase for one data transfer is processed in a distributed manner (shared) in each microprocessor, the previous command phase is completed, and the next command phase requiring a chronological order is executed. In order to execute it, it is necessary to give a completion report. However, when a series of commands for separate data transfer are processed in each microprocessor, it is not necessary to notify the other microprocessor of the end of the command processing.
[0031]
In the embodiment of the present invention, a command to be processed is transferred to each microprocessor by hardware in a command control circuit, and this command processing is performed in the above-described two patterns (that is, one command corresponds to two commands). The pattern shared by one microprocessor and the other is a pattern in which two commands are processed by each microprocessor) or other methods are processed by a microprogram on the command control circuit. Whether or not a termination report should be communicated is not a requirement of the present invention.
[0032]
According to the present invention, when command processing is performed by a plurality of microprocessors, the main purpose is to transfer a command to a plurality of microprocessors at once without performing one command transfer to a plurality of microprocessors. . By transferring a command to each microprocessor using the multiplex write function of such a command control circuit, command processing in the microprocessor is load-balanced among the microprocessors, and a bottleneck caused by the microprocessor is reduced. It is.
[0033]
Next, the suitability of the present invention with respect to a Fiber Channel (FC) command in RAID (DKC + DKU) to which the present invention is applied will be described. What the present invention is suitable for RAID is a data transfer command. That is, it is a command requiring cache access. Specifically, the FC command is indicated by FCP_CMND, the FCP_CDB in the FCP_CMND format is a command indicating a data transfer system, and the command names are Write and Read. When these commands are transmitted from the host server, the commands are transmitted to both microprocessors 113 and 116 by the multiplex write function of the present invention.
[0034]
When this command is received (an example of a Write command), the roles of the microprocessors 113 and 116 include the following processing examples other than the processing example shown in FIG. That is, when the command is received, the microprocessor 113 controls the external I / F transmission / reception unit 101 in advance, and another microprocessor 116 determines the data transfer control unit 131 located in the CHA in advance. Preparation and control for data transfer are performed in parallel. That is, the microprocessor 113 controls and prepares the external I / F transmission / reception unit 101 to perform data transfer with the host server, and transfers data based on the FCP_CMND transmitted by another microprocessor 116 in parallel. The controller 131 controls the data transfer to the cache. When the preparation by the microprocessor 116 ends, the microprocessor 113 is notified that the transfer preparation inside the CHA has ended. Then, the microprocessor 113 instructs the external I / F protocol control circuit 103 to start data transfer (GO).
[0035]
As described above, in the RAID to which the present invention is applied, one of the microprocessors controls an external I / F transmission / reception part, which is an I / F with an upper-level host server, by a data transfer command. It is suitable that one microprocessor controls the data transfer control unit in the RAID CHA.
[0036]
Note that the present invention is not suitable for commands other than the data transfer system. For example, there is an Inquiry command as FCP_CDB of FCP_CMND. This command is a command for obtaining RAID device information. Since the information is written in a flash memory (not shown) of the CHA, no exchange with the cache occurs, so that the microprocessor 116 controls the data transfer control unit. There is no need to do. Thus, a command that does not require access to the cache, which is not a data transfer command, is preferably processed by only one of the microprocessors.
[0037]
Next, another embodiment of the present invention will be described with reference to FIG. In the embodiment shown in FIG. 1, the number of microprocessor parts is two. However, as shown in FIG. 4, if the command control circuit can have more ports for interfacing with the microprocessor part, the number of microprocessor parts becomes larger. A microprocessor part and a microprocessor can be provided, and there is a possibility that further load distribution can be expected. Further, in the embodiment shown in FIG. 1, the number of external I / F transmission / reception parts is one, but a plurality of parts may be provided as shown in FIG. In this case, arbitration for acquiring the right to use the bus is performed in a bus-free state.
[0038]
【The invention's effect】
As described above, according to the present invention, processing of a command from an upper-level host server is transferred to each microprocessor by a command control circuit having a multiplex write function, and distributed by a plurality of microprocessors. With this method, it is possible to reduce the bottleneck of the microprocessor in the interface unit of the disk device and prevent the performance of the storage system from deteriorating due to the disk device.
[Brief description of the drawings]
FIG. 1 is a diagram showing a specific configuration of a CHA (channel adapter) which is an interface unit with an upper-level host server according to an embodiment of the present invention.
FIG. 2 is a flowchart showing processing contents in two processors in a CHA according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating a time course of a command phase in two processors according to the present embodiment in comparison with a conventional technique.
FIG. 4 is a diagram showing a specific configuration of a CHA (channel adapter) which is an interface unit with an upper-level host server according to another embodiment of the present invention.
FIG. 5 is a diagram showing an overall configuration of data transfer including a host computer, a DKC, and a DKU according to the related art.
[Explanation of symbols]
101, 501 External I / F transmission / reception part 102, 502 External I / F transmission / reception circuit 103, 503 External I / F protocol control circuit 111, 114, 511 Microprocessor part 112, 115, 512 Microprocessor control circuit 113, 116, 513 Microprocessors 121, 521 Command control circuits 131, 531 Data transfer control unit

Claims (3)

An external I / F transmission / reception unit connected to an upper host server, a microprocessor unit having a microprocessor for processing a command issued from the upper host server, and an external I / F transmission unit and the microprocessor unit. A command control circuit interposed between the command control circuit and an interface unit of the storage device,
A plurality of microprocessor units are connected to the command control circuit,
The command control circuit has a multiplex write function of simultaneously transferring a command from the upper host server to the plurality of microprocessor units at a time, and the multiplex write function of the command control circuit allows A command processing method wherein commands are distributed to and processed by respective microprocessors. In claim 1,
A command processing method, wherein, when processing commands by the microprocessors, processing of a plurality of command phases is performed in parallel by the microprocessors. In claim 1,
A command processing method comprising a plurality of the external I / F transmission / reception units.

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