JP2004134830A - Semiconductor integrated circuit device and design method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device operable at high speed with low current consumption in a stop or standby state. <P>SOLUTION: The semiconductor integrated circuit device is provided with a function of fixing a logic circuit between a flip-flop circuit and another flip-flop circuit of next stage to a prescribed state in a stop or standby state of the semiconductor integrated circuit device to determine an ON state or an OFF state of each MOSFET configuring the logic circuit. Then all or parts of the MOSFETs in the ON state are constituted of the MOSFETs having a low threshold voltage and all of the MOSFETs in the OFF state are constituted of the MOSFETs having a high threshold voltage, with the result that the semiconductor integrated circuit device is operated at high speed and an increase in the current consumption due to an off-leak current of the MOSFETs can be suppressed in the stop or standby state. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device that operates at high speed and consumes less current, and a method for designing the same.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor integrated circuit device used for a portable information device, a reduction in power consumption is required for a high speed operation and a long battery life. Therefore, the semiconductor integrated circuit device has a low power consumption operation mode such as an operation stop state or a standby state. In the operation stop state, the clock circuit stops operating, and all the circuits inside the semiconductor integrated circuit device stop. In the standby state, the clock circuit operates, but does not supply the clock to the non-operating part in the semiconductor integrated circuit device.
[0003]
In addition, since power consumption during operation is proportional to the square of the power supply voltage, lowering the power supply voltage is most effective for reducing power consumption. Therefore, the power supply voltage tends to be set low. However, if the power supply voltage is reduced to a voltage close to a voltage at which the MOSFET is turned on (hereinafter, referred to as a threshold voltage), the current driving capability of the MOSFET is significantly reduced. In order to prevent the decrease in the threshold voltage, it is necessary to reduce the threshold voltage of the MOSFET. However, when the threshold voltage of the MOSFET is reduced, another problem arises in that the current consumption during the stop or standby of the semiconductor circuit device increases. This is because the drain current shows an exponential dependence on the gate voltage in a sub-threshold region equal to or lower than the threshold voltage of the MOSFET. Therefore, when the threshold voltage is reduced, a significant increase in off-leakage current occurs. It is. In particular, in portable information devices, the stop or standby time is longer than the operation time, and the power consumption in this mode has a significant effect on the battery life.
[0004]
Several methods have been considered to solve this problem. Representative examples of these techniques include (1) a technique of controlling a threshold voltage by a substrate bias, and increasing the threshold voltage when the semiconductor integrated circuit device is stopped or in a standby state to reduce off-leakage current ( (See, for example, Non-Patent Document 1), (2) A circuit is configured using a plurality of threshold voltage MOSFETs, and a low threshold voltage MOSFET is used in a portion requiring an operation speed, and an operation speed However, there is a technique (for example, see Patent Document 1) for harmonizing current consumption and operation speed by using a MOSFET having a high threshold voltage in a portion where the operation is not so required.
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 11-195076 [Non-Patent Document 1]
Proceedings of the 1996 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, p. 53-56
[0006]
[Problems to be solved by the invention]
However, in the above-mentioned conventional technique (1), it is difficult to uniformly control the substrate bias of 1,000,000 or more MOSFETs such as a large-scale semiconductor integrated circuit device. Further, as the gate length becomes shorter or the threshold voltage becomes lower, the effect becomes smaller. Further, when the substrate bias is increased to enhance the effect of reducing the leakage current, there is a problem that the junction leakage increases. Further, in the conventional technique (2), all of the MOSFETs constituting the logic gate are formed of low threshold voltage MOSFETs or high threshold voltage MOSFETs, and the MOSFETs are reduced in accordance with desired current consumption and operation speed. Since the semiconductor integrated circuit device is designed by selecting a logic gate composed of a MOSFET having a threshold voltage or a logic gate composed of a MOSFET having a high threshold voltage, a design in which current consumption and operation speed are finely controlled is designed. It was difficult to do. In a semiconductor integrated circuit device such as a processor used for a portable information device, a stop or standby time is much longer than an operation time, and a required current consumption is considerably reduced due to a longer battery life. Therefore, it is very important to reduce the current consumption during stoppage or standby of the semiconductor integrated circuit device over the details of the circuit.
[0007]
[Means for Solving the Problems]
In order to solve the above problem, in a semiconductor integrated circuit device according to the present invention, a logic circuit between a flip-flop circuit and a next-stage flip-flop circuit is fixed at a predetermined state when the semiconductor integrated circuit device is stopped or on standby. By providing the function, the ON state or the OFF state of each MOSFET constituting the logic circuit is determined. Then, all or a part of the MOSFETs in the on state are constituted by low threshold voltage MOSFETs, and all of the MOSFETs in the off state are constituted by high threshold voltage MOSFETs. The device operates at high speed and suppresses an increase in current consumption due to off-leakage current of the MOSFET when stopped or in standby.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a conceptual diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.
[0009]
In FIG. 1, when the semiconductor integrated circuit device 1 is stopped or put into a standby state, the control circuit 100 turns on or off MOSFETs constituting the logic circuits 220 to 280 disposed between the flip-flop circuits 200 and 210. A signal for fixing the state to a predetermined state is output.
[0010]
FIG. 2 illustrates the logic circuits 220 to 280 of the semiconductor integrated circuit device 1 of FIG. 1 by MOSFETs, and FIG. 2 and FIG. 1 are equivalent circuit diagrams. Hereinafter, a configuration of a semiconductor integrated circuit device that operates at high speed and realizes low current consumption will be described with reference to FIG. When the semiconductor integrated circuit device 1 is stopped or put into a standby state, the control circuit 100 outputs a signal 101 to the flip-flop circuits 200 and 210. The signal 101 is set to a high level ("H" in FIG. 2; the same applies hereinafter), and the flip-flop circuits 200 and 210 are reset by the input of the signal 101, so that the flip-flop circuit 200 is reset. The signals 300 and 310 output from the signals 210 and 210 are at a low level (in FIG. 2, indicated as “L”; the same applies hereinafter). The signal 101 output from the control circuit 100 is connected to the NOR circuit 220, and the signal 320 output from the NOR circuit 220 is fixed at a low level. Accordingly, the signal 330 output from the inverter circuit 230 is at a high level, the signal 340 output from the NAND circuit 240 is at a high level, the signal 350 output from the NOR circuit 250 is at a low level, and the signal 360 output from the inverter circuit 260 Is fixed at a high level, the signal 370 output from the inverter circuit 270 is fixed at a low level, and the signal 380 output from the NAND circuit 280 is fixed at a high level. That is, when the semiconductor integrated circuit device 1 is stopped or put into the standby state, the MOSFETs 224, 231, 241, 253, 254, 261, 272, and 281 of the MOSFETs constituting the logic circuits 220 to 280 are turned on (see FIG. 2). MOSFETs 221, 232, 243, 251, 252, 262, 271, and 283 are turned off. The on-state MOSFET has a low threshold voltage (for example, 0.3 V for an N-channel MOSFET, −0.3 V for a P-channel MOSFET, and an off-leakage current of 200 pA when the power supply voltage is 1.5 V). The off-state MOSFET is configured with a high threshold voltage (for example, 0.45 V for an N-channel MOSFET, -0.45 V for a P-channel MOSFET, and the off-leakage current is 2 pA when the power supply voltage is 1.5 V). By doing so, it is possible to reduce the off-leak current of the entire logic circuits 220 to 280.
[0011]
Further, changing part of the MOSFETs constituting the logic circuits 220 to 280 from those having the high threshold voltage to those having the low threshold voltage has an effect of reducing the delay time generated in the logic circuits 220 to 280. . Since the delay time of a circuit composed of MOSFETs is determined by the charge / discharge time of the load capacitance of the circuit, the delay time should be reduced by improving the current drive capability of the MOSFET or reducing the input and output capacitances of the MOSFET. Can be. Therefore, when the MOSFET constituting the logic circuit is changed from a high threshold voltage to a low threshold voltage, the current driving capability is improved if the gate width is the same, which can contribute to a reduction in delay time. . Further, even when the current driving capability of the MOSFET is fixed, the gate width can be reduced by changing from a high threshold voltage to a low threshold voltage, and as a result, the input capacitance and the output capacitance are reduced. Is reduced, so that the delay time can be reduced.
[0012]
In the signal path from the flip-flop circuit 200 to the flip-flop circuit 210, if the delay time when the signal 300 output from the flip-flop 200 falls is too long to satisfy the required speed, the high threshold voltage By changing the MOSFET to a low threshold voltage MOSFET having the same gate width, the current driving capability is improved and the delay time can be shortened. The P-channel MOSFET 241 for shortening the rise time of the NAND circuit 240, the N-channel MOSFET 253 for shortening the fall time of the NOR circuit 250, the P-channel MOSFET 261 for shortening the rise time of the inverter circuit 260, and the fall of the inverter circuit 270 It is possible to reduce the delay time by N-channel MOSFET272 to reduce the time, of all or part of the P-channel MOSFET281 to shorten the rise time of the NAND circuit 280 to MOSEFT the MOSFET with a low threshold voltage.
[0013]
In the signal path from the output signal 300 of the flip-flop circuit 200 to the input 380 of the flip-flop circuit 210, if the delay time when the output signal 300 rises is too long and the required speed is not satisfied, By changing a high voltage MOSFET to a low threshold voltage MOSFET having the same current driving capability, the gate width can be reduced, the input capacitance and output capacitance can be reduced, and the delay time can be shortened. Among the ON MOSFETs, a P-channel MOSFET 241 for shortening the fall time of the NAND circuit 240, an N-channel MOSFET 253 for shortening the rise time of the NOR circuit 250, a P-channel MOSFET 261 for shortening the fall time of the inverter circuit 260, and an inverter Circuit 2 All or some of the MOSEFTs of the N-channel MOSFET 272 for shortening the rise time of the zero and the P-channel MOSFET 281 for shortening the fall time of the NAND circuit 280 are MOSFETs having a small gate width and a low threshold voltage, so that the delay time is reduced. Can be reduced.
[0014]
Further, when the MOSFETs are connected in series like the P-channel MOSFETs 251 and 252 in the NOR circuit 250, even if both of them are off when the semiconductor integrated circuit device 1 is stopped or in the standby state, one of them is turned off. Is a high threshold voltage MOSFET, the off-leak current does not increase even if the other is a low threshold voltage MOSFET. Further, the delay time can be reduced by using one of the MOSFETs 251 and 252 as a low threshold voltage MOSFET.
[0015]
In the above embodiment, a signal for fixing the state of the logic circuit when the semiconductor integrated circuit device 1 is stopped or on standby is input to the reset terminals of the flip-flop circuits 200 and 210 and output from the flip-flop circuit. Although the on or off state of the MOSFETs constituting the logic circuits 240 to 280 is fixed by a signal, the signal for fixing is directly input to the logic circuits 240 to 280 and the MOSFETs constituting the logic circuits 240 to 280 are fixed. May be fixed in an on or off state.
[0016]
Further, in the description of the above-described embodiment, the low threshold voltage MOSFET and the high threshold voltage MOSFET are used for both the N channel and the P channel, that is, four types of MOSFETs are used, but the P channel has a low threshold voltage. Value voltage MOSFET and high threshold voltage MOSFET, N channel should be only high threshold voltage MOSFET, N channel should be low threshold voltage MOSFET and high threshold voltage MOSFET, P channel should be high threshold voltage MOSFET If only three MOSFETs are used by using only voltage MOSFETs, the number of ion implantation steps required four times to form all MOSFETs can be reduced to three in the above-described embodiment. Further, the cost of the semiconductor integrated circuit device manufacturing process can be reduced.
[0017]
Next, FIG. 3 is a flowchart showing a method of designing the semiconductor integrated circuit device according to the embodiment. Hereinafter, a design method of the semiconductor integrated circuit device will be described with reference to FIG. First, logic synthesis of a target semiconductor integrated circuit device is performed using only a high threshold voltage MOSFET having a small off-leak current (step 1). As a result, if all paths satisfy the target delay time, the design is terminated (step 2). If there is a route that does not satisfy the target delay time, circuit status information indicating that the target semiconductor integrated circuit device is stopped or in a standby state is input (step 3). According to the circuit state information, only the MOSFET which is turned on in the stop or standby state is replaced with a logic cell constituted by a MOSFET having a low threshold voltage for the logic cell on the path which does not satisfy the target delay time. Perform (Step 4). For the logic cells used for replacement, prepare a logic cell with a reduced gate width to reduce the input and output capacitance to match the output current capability, and a logic cell with a reduced delay time by increasing the output current capability. The logic cell to be replaced is selected depending on whether the delay characteristic to be reduced is the rise time or the fall time. The replacement of the logic cells is sequentially performed, and the replacement of the logic cells is performed until the target delay time is satisfied (step 5).
[0018]
In the embodiment of the design method, the replacement of the logic cell is performed with the delay time as a design target, but the replacement of the logic cell may be performed with the target of the off-leak current, or both the delay time and the off-leak current. It is possible.
[0019]
Further, in the above-described embodiment of the design method, only the MOSFETs that are turned on in the stop or standby state are replaced with low threshold voltage MOSFETs. However, even in the MOSFETs that are turned off in the stop or standby state, these MOSFETs are connected in series. When connected, a method of setting at least one of the MOSFETs to a high threshold voltage and replacing all or a part of the remaining MOSFETs with a low threshold voltage may be performed simultaneously.
[0020]
【The invention's effect】
According to the semiconductor integrated circuit device of the present invention, when the semiconductor integrated circuit device is stopped or in a standby state, an increase in current consumption due to an off-leak current of the MOSFET can be suppressed, and a delay time of a path having a large delay time can be reduced. Thus, high-speed operation can be realized.
[Brief description of the drawings]
FIG. 1 is a logic circuit block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a MOSFET block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. Flow chart of design method of semiconductor integrated circuit device
1 Semiconductor Integrated Circuit Device 100 Control Circuits 200, 210 Flip-Flop Circuit 220, 250 NOR Circuits 221, 231, 241, 251, 252, 261, 271, 281 P-Channel MOSFET Outputting Signal During Stop or Standby
224,232,243,253,254,262,272,283 N-channel MOSFET
230, 260, 270 Inverter circuits 240, 280 NAND circuit

Claims (6)

A first threshold voltage MOSFET;
A semiconductor integrated circuit device including a MOSFET having a second threshold voltage lower than the first threshold voltage,
A control circuit that outputs a signal for fixing the on or off state of the MOSFET constituting the semiconductor integrated circuit to a predetermined state when the semiconductor integrated circuit is stopped or put into a standby state;
A semiconductor integrated circuit device in which all or a part of MOSFETs fixed in an on state by a signal output from the control circuit is configured by the MOSFET having the second threshold voltage. 2. The semiconductor integrated circuit device according to claim 1, wherein the MOSFET having the second threshold voltage is an N-channel MOSFET. 2. The semiconductor integrated circuit device according to claim 1, wherein the MOSFET having the second threshold voltage is a P-channel MOSFET. A first threshold voltage MOSFET;
A semiconductor integrated circuit device including a MOSFET having a second threshold voltage lower than the first threshold voltage,
A control circuit that outputs a signal for fixing an on or off state of a MOSFET constituting the semiconductor integrated circuit to a predetermined state when the semiconductor integrated circuit is stopped or put into a standby state;
At least one of a plurality of MOSFETs fixed in an OFF state by a signal output from the control circuit and connected in series is configured by a MOSFET having a first threshold voltage, and A semiconductor integrated circuit device in which all or some of the MOSFETs other than the threshold voltage MOSFETs are constituted by MOSFETs having a second threshold voltage. When stopping or putting a semiconductor integrated circuit configured by a MOSFET having a first threshold voltage and a MOSFET having a second threshold voltage lower than the first threshold voltage into a standby state, the semiconductor integrated circuit A design method of a semiconductor integrated circuit device including a control circuit that outputs a signal for fixing an on or off state of a MOSFET constituting a circuit to a predetermined state,
First, the semiconductor integrated circuit device is configured with a MOSFET having a first threshold voltage, and the delay time of the semiconductor integrated circuit device is verified,
If the delay time is larger than a desired value, all or a part of the MOSFET of the first threshold voltage, which is fixed to the ON state by a signal output from the control circuit, is subjected to a second operation. Convert to threshold voltage MOSFET,
A method for designing a semiconductor integrated circuit device for reducing a delay time. When stopping or putting a semiconductor integrated circuit configured by a MOSFET having a first threshold voltage and a MOSFET having a second threshold voltage lower than the first threshold voltage into a standby state, the semiconductor integrated circuit A design method of a semiconductor integrated circuit device including a control circuit that outputs a signal for fixing an on or off state of a MOSFET constituting a circuit to a predetermined state,
Detecting a plurality of MOSFETs that are fixed in an OFF state by a signal output from the control circuit and are connected in series,
At least one of the plurality of MOSFETs connected in series is a MOSFET having a first threshold voltage, and MOSFETs other than the MOSFET having the first threshold voltage are MOSFETs having a second threshold voltage. Design method for semiconductor integrated circuit devices composed of

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