JP2004134788A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make image quality uniform by suppressing the influences of a voltage drop due to wiring resistance in a display device, and moreover, to improve the operational speed of a drive circuit by suppressing the delay of wiring providing electrical connection between the drive circuit and input/output terminals. <P>SOLUTION: As wiring used for a semiconductor device, wiring containing copper for enabling reduction in wiring resistance is made minute and used. A conductive film of a barrier nature (referred to as barrier type conductive film, hereafter) preventing the diffusion of copper is provided between thin-film transistors (represented as TFTs, hereafter), so as to form the wiring containing copper without diffusing copper to the semiconductor layer of the TFT. In addition, the wiring containing copper is wiring comprising a laminated film of the conductive film having copper as a main component and the barrier type conductive film having a barrier nature to the diffusion of copper, and is subjected to microfabrication for reducing the line width of the conductive film having copper as the main component. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to wiring formation in the field of semiconductor devices using a semiconductor element (typically a transistor) as a device, and belongs to a technical field relating to resistance reduction of wiring and a technical field relating to miniaturization thereof.

In recent years, a technique for manufacturing a TFT using a semiconductor thin film (having a thickness of about several hundred to several thousand nm) formed on an insulating surface has been developed. TFTs are widely applied to semiconductor devices such as integrated circuits (ICs) and electro-optical devices, and development of switching elements for display devices including liquid crystal display devices and light-emitting devices is urgently being developed.

Above all, display devices such as monitors and televisions are expanding their applications and mass production is progressing, and the demand for larger screen size, higher definition, higher aperture ratio, and higher reliability is increasing. ing.

However, a voltage drop (also referred to as IR drop) due to wiring resistance is a phenomenon that causes a problem in driving the display device. This is a phenomenon in which the voltage drops as the distance from the power source increases even with the same wiring. This problem is particularly prominent when the wiring length is long, which is a major obstacle to increasing the screen size of the display device.

In other words, it becomes impossible to transmit a desired voltage due to a voltage drop caused by the wiring resistance, and as a result, there is a problem that the uniformity of image quality is remarkably impaired in the pixel portion. Attempts have been made to improve such problems by applying voltage from both ends of the wiring. However, since the wiring is drawn long, the influence of the voltage drop cannot be ignored in the end.

When a monolithic display device in which a driver circuit portion (typically including a gate driver circuit and a source driver circuit) is formed over the same substrate is formed between the driver circuit portion and an electric signal input terminal. The wiring resistance of the wiring that draws the wire becomes a problem. The wiring resistance may cause a delay of the electric signal and reduce the operation speed of the gate driving circuit and the source driving circuit.

As described above, problems such as voltage drop due to wiring resistance and signal delay significantly impair image quality uniformity, and drive circuit operation speed extremely decreases. Such a problem is particularly remarkable in a display device having a large screen such as several tens of inches diagonally.

On the other hand, it has been reported that the wiring resistance is reduced by using a low-resistance material (see, for example, Patent Document 1). However, in such a case, copper is used as a low-resistance material, and fine processing is difficult because copper wiring is formed by damascene technology, and there is a problem of particle contamination when using CMP technology. doing.

In addition, in order to suppress the influence of the voltage drop caused by the wiring resistance, the substrate on which the element is formed and the printed wiring board (PWB) having a high hardness are made of a conductor (anisotropic conductive film or bump). A technique is known that is electrically connected to reduce the resistance of various wirings (first wiring group) formed on the element formation substrate (see, for example, Patent Document 2).

JP 2000-58650 A Japanese Patent Laid-Open No. 2001-236025

An object of the present invention is to suppress the influence of the voltage drop caused by the wiring resistance as described above, and to make the image quality of the display device uniform. It is another object of the present invention to suppress the delay of the wiring that electrically connects the drive circuit unit and the input / output terminal and improve the operation speed of the drive circuit unit.

In the present invention, in order to solve the above problems, as a wiring used in a semiconductor device, a wiring containing copper that realizes a reduction in wiring resistance is miniaturized and used as a barrier conductive film (hereinafter referred to as a copper conductive film) that prevents copper diffusion. , A barrier conductive film is provided between a thin film transistor (hereinafter referred to as TFT), and a wiring containing copper is formed in the semiconductor layer of the TFT without diffusion of copper.

Note that the wiring containing copper in the present invention is a wiring made of a laminated film of a conductive film containing at least copper as a main component and a barrier conductive film having a barrier property against copper diffusion. In the case of forming a stacked structure of three or more layers, a conductive film containing copper as a main component may be provided between the layers. However, it is necessary to have a barrier conductive film between the conductive film mainly composed of copper and the active layer of the TFT. Here, the conductive film containing copper as a main component means a copper or a film having a copper content of 50% by weight, preferably 90% by weight or more.

In addition, the conductive film containing copper as a main component is formed by a DC sputtering method using a mask or a vapor deposition method, and further using a dry etching method to narrow the line width of the conductive film containing copper as a main component. It is characterized by fine processing. Note that the mask used here is made of stainless steel, nickel, glass, or quartz, and has a pitch of 5 μm or more in the openings. Moreover, in this invention, it is preferable to form the electrically conductive film which has copper as a main component with a film thickness of 0.1-1 micrometer.

In the present invention, the wiring containing copper forms a source line (signal line), a gate line (scanning line), a current supply line, and a routing wiring.

In addition, since copper used in the present invention is an unfavorable material for the electrical characteristics of the TFT as described above, in the present invention, at least the active layer and copper are the main components so that the copper does not enter the active layer of the TFT. A barrier conductive film having a barrier property against copper is provided between the conductive film and the conductive film. As the barrier conductive film, one or more kinds of laminated films selected from tantalum nitride (TaN), titanium nitride (TiN), and tungsten nitride (WN) can be used.

As described above, the structure of the present invention is a method for manufacturing a semiconductor device having a wiring formed by stacking conductive films, in which a first conductive film having a barrier property is formed over an insulating surface, and the first conductive A film is formed into a desired shape by an etching method, a second conductive film containing copper as a main component is formed on the first conductive film through an opening of a mask, and the second conductive film is further formed by a dry etching method. A method for manufacturing a semiconductor device is characterized in that the width of a film is narrowed.

In addition, the present invention includes a case where a scanning line is manufactured by the wiring manufacturing method of the present invention.

Note that another structure of the present invention is a method for manufacturing a semiconductor device having a wiring formed by stacking conductive films, in which a semiconductor layer is formed over an insulating surface, and the first insulating film is formed over the semiconductor layer. A first conductive film having a barrier property is formed on the first insulating film, the first conductive film is formed into a desired shape by an etching method, and copper is mainly formed on the first conductive film. A second conductive film as a component is formed through the opening of the mask, the width of the second conductive film is narrowed by dry etching, and the first conductive film made of the first and second conductive films is formed. An impurity element is added to the semiconductor layer by using the wiring as a mask to form an impurity region, a second insulating film is formed to cover the first wiring, and the impurity is formed in a part of the second insulating film. A contact hole reaching the region is formed, and the non-contact hole is formed on the second insulating film. A method for manufacturing a semiconductor device and forming a second wiring connected object region and electrically.

Note that in the above structure, the third conductive film having a barrier property over the second insulating film is formed into a desired shape by an etching method, and the fourth conductive film containing copper as a main component is formed over the third conductive film. In the method for manufacturing a semiconductor device, the second wiring is formed by forming a film through an opening of a mask and further reducing the width of the fourth conductive film by a dry etching method. is there.

Another structure of the present invention is a method for manufacturing a semiconductor device having a wiring formed by stacking conductive films, a semiconductor layer partially including an impurity region, and a first insulating film over the semiconductor layer A second insulating film is formed on the gate electrode formed through the contact hole, a contact hole reaching the impurity region is formed in a part of the second insulating film, and a barrier property is formed on the second insulating film. A first conductive film having a pattern is formed by an etching method, a second conductive film containing copper as a main component is formed over the first conductive film through a mask opening, and further, a dry etching method is used. In the method for manufacturing a semiconductor device, a wiring electrically connected to the impurity region is formed over the second insulating film by reducing a width of the second conductive film.

Further, in each of the above structures, an insulating film having a barrier property of any one of silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide is formed by a sputtering method so as to cover the second conductive film. This is a feature of a method for manufacturing a semiconductor device.

In the present invention, wiring resistance can be reduced and a large current can flow by forming a wiring containing copper. Therefore, voltage drop and signal waveform rounding can be reduced.

Further, in the present invention, since the wiring containing copper can be miniaturized, the area of the wiring and electrode can be reduced. In addition, when using the wiring containing copper formed according to the present invention, it is particularly effective when a medium-sized or large-sized panel of 5 inches or more is manufactured and a large current flows through the wiring.

By implementing the present invention, in a semiconductor device such as a light emitting device or a liquid crystal display device, a voltage drop and a signal delay caused by wiring resistance, which are problems when realizing a large screen, are reduced, and an operation speed of a driving circuit unit is reduced. And the uniformity of the image in the pixel portion can be improved.

Embodiments of the present invention will be described below.

(Embodiment 1)
A method for manufacturing a wiring containing copper in the present invention will be described with reference to FIGS.

In FIG. 1A, a first conductive film 102 is patterned on a substrate 101. Note that as a material of the first conductive film 102 formed here, TiN, TaN, WN having a barrier property for preventing intrusion of copper from a conductive film mainly composed of copper to be formed later, A conductive film containing TiC, TaC, or silicon can be used. Further, a material such as Ti, Al, Ta, or W can be used in combination with these materials.

Note that the first conductive film is formed by a sputtering method and patterned by a dry etching method. Further, the first conductive film at this time is formed with a line width of 30 to 40 μm.

Next, as shown in FIG. 1B, the second conductive film 104 is patterned by a sputtering method using the mask 103 (FIG. 1C). Here, a metal mask is used as the mask 103.

The second conductive film 104 formed here is made of a material mainly composed of copper and has a thickness of 0.1 to 1 μm.

Next, a resist 105 is formed over the second conductive film 104, and is finely processed by a dry etching method using the resist 105 as a mask to obtain a shape indicated by 106 (FIG. 1E). Note that the line width of the second conductive film 104 in this case is 5 to 20 μm. Note that as an etching method, dry etching is performed using a gas containing chlorine, and the inside of the etching treatment chamber is decompressed (including vacuum) and the substrate surface is heated or irradiated with light.

Although not shown here, after forming the wiring of FIG. 1E, an insulating film having a barrier property (barrier insulating film) is formed in order to prevent diffusion of copper contained in the second conductive film. Is preferred. As a material used for the barrier insulating film, silicon nitride, silicon oxynitride, aluminum nitride, aluminum nitride oxide, a DLC (diamond-like carbon) film, carbon nitride (CN), or the like can be used.

(Embodiment 2)
In Embodiment Mode 2, copper is used for a signal line (including a current supply line in this embodiment mode) that is formed in the pixel portion of the display device and inputs a signal from the source side driver circuit to each pixel. A case of using the wiring including the above will be described. Note that for the display device described in this embodiment, a case of a light-emitting device including a light-emitting element formed by sandwiching an electroluminescent layer between a pair of electrodes will be described.

The light-emitting device includes a plurality of pixels illustrated in FIG. 2A in a pixel portion in a matrix.
Note that each pixel includes a signal line 201, a current supply line 202, a scanning line 203, a plurality of TFTs (204, 205), a capacitor element 206, and a light emitting element 207. Each TFT (204, 205) is not limited to a single gate structure, and may have a multi-gate structure such as a double gate structure or a triple gate structure.

Next, FIG. 2B shows a top view of FIG. Note that here, a signal line 201, a current supply line 202, a scanning line 203, a plurality of TFTs (204, 205), and a capacitor element 206 are formed, and a pixel electrode before formation of a pixel electrode to be a first electrode of the light emitting element is formed. Indicates the state. Note that the pixel electrode is formed later on the broken line portion 209 in FIG.

Further, the signal line 201 and the current supply line 202 are each formed of a laminated film of barrier conductive films 201a and 202a) and conductive films (201b and 202b) containing copper as a main component.

2B, one of the source region and the drain region of the TFT 204 is connected to the signal line 201, and the other is connected to the capacitor element 206 and the gate electrode of the TFT 205. A part of the scanning line 203 is a gate electrode of the TFT 204. Further, one of the source region and the drain region of the TFT 205 is connected to a pixel electrode 209 to be formed later, and the other is connected to the current supply line 202. The capacitive element 206 is formed in a region where the current supply line 202 and the active layer are stacked.

Next, a different structure as a cross-sectional view of A-A ′ shown in FIG. 2B will be described in detail with reference to FIGS.

First, in FIG. 2C, reference numeral 211 denotes a substrate having an insulating surface, and a glass substrate, a ceramic substrate, a quartz substrate, a silicon substrate, or a plastic substrate (including a plastic film) can be used.

Next, a silicon oxynitride film 212a and a silicon oxynitride film 212b are stacked over the substrate 211 as a base film. Of course, it is not necessary to limit to these materials.

Next, over the silicon oxynitride film 212b, a semiconductor layer of the TFT 205 and a semiconductor layer provided in the capacitor element 206 region (hereinafter collectively referred to as a semiconductor layer 213) are provided. And a GOLD structure that overlaps with the LDD region and the gate electrode can be formed as appropriate.

The TFT semiconductor layer 213 is covered with a gate insulating film 214, and a gate electrode in which tantalum nitride (TaN) 215 and tungsten (W) 216 are stacked is provided thereon. Note that a silicon oxynitride film is used as the gate insulating film 214 in this embodiment. In addition, since the metal film of the gate electrode has a high selection ratio, it is possible to obtain such a structure by selecting an etching condition. Regarding this etching condition, Japanese Patent Application Laid-Open No. 2001-313397 by the present applicant may be referred to.

A silicon nitride film or a silicon nitride oxide film is provided as the insulating film 217 covering the gate electrode. In this embodiment, a silicon nitride oxide film is formed by a plasma CVD method. Further, on the insulating film 217, for the purpose of planarization, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, resist or benzocyclobutene), an inorganic material formed by a sputtering method, a CVD method, or a coating method is used. The interlayer insulating film 218a is formed using a material (silicon oxide, silicon nitride, silicon oxynitride, or the like) or a stacked layer thereof. In addition to the interlayer insulating film, a skeleton structure is formed by the bond of silicon (Si) and oxygen (O), and the material containing at least hydrogen as a substituent or fluorine, alkyl group, or aromatic hydrocarbon as a substituent You may form using the material (typically siloxane type polymer) which has at least 1 sort (s) among these.

Next, a first barrier insulating film 219 made of a nitride insulating film (typically a silicon nitride film or a silicon nitride oxide film) is formed over the interlayer insulating film 218a. In this embodiment, a silicon nitride film is used as the barrier insulating film 219. After that, contact holes (openings) are formed in the barrier insulating film 219, the interlayer insulating film 218a, the insulating film 217, and the gate insulating film 214 by using a wet etching method or a dry etching method.

Note that the contact hole provided in the interlayer insulating film 218a illustrated in FIG. 2C has a tapered shape that decreases in diameter toward the bottom, and the upper surface of the interlayer insulating film 218a, the slope of the contact hole, and the contact hole (contact hole). The angle formed by (a corner portion) (portion indicated by 221a in FIG. 2C) is about 95 to 135 degrees.

Next, barrier conductive films 201a and 202a are formed using a conductive material having a barrier property, and patterning is performed by an etching method (dry etching method or wet etching method).

Next, conductive films 201b and 202b mainly composed of copper are formed on the barrier conductive films 201a and 202a by a sputtering method using a metal mask, and then finely processed by a dry etching method. Note that Embodiment 1 may be referred to for a method for manufacturing the conductive films 201b and 202b.

Note that, as described above, the signal line 201 and the current supply line 202 which are formed of a laminated film of the barrier conductive films 201a and 202a and the conductive films 201b and 202b mainly composed of copper are formed.

Next, FIG. 2D shows a structure in which the corner of the contact hole (the portion indicated by 221b in FIG. 2D) is rounded and the diameter becomes smaller as it goes downward. Note that a material similar to that of 218a may be used for the interlayer insulating film 218b. In this case, a photosensitive or non-photosensitive organic material may be used as a material for the interlayer insulating film 218b, and a contact hole may be formed using a wet etching method or a dry etching method.

Further, in FIG. 2 (E), the contact taper shape is different from that in FIG. 2 (D), the corner of the contact hole (the portion indicated by 221c in FIG. 2 (E)) is rounded, and the contact A structure in which a hole has a slope having two or more different radii of curvature is shown. At this time, as a material of the interlayer insulating film 218c, a material similar to that of the interlayer insulating films 218a and 218b may be used, and a contact hole may be formed using a wet etching method or a dry etching method.

As described above, the shape of the contact hole formed in the interlayer insulating film can prevent disconnection of the wiring 220 provided in the TFT 205.

2C. After forming the conductive films (201b, 202b) containing copper as a main component as shown in FIGS. 2C to 2E, preferably, as shown in FIG. An insulating film 304 is formed to cover 201b and 202b). The insulating film 304 may be formed using silicon nitride (SiN) or silicon nitride oxide (SiNO). Note that in this embodiment mode, silicon nitride is formed by a high frequency sputtering method. Thus, by covering the conductive films (201b and 202b) containing copper as a main component with the insulating film 304, it is possible to prevent copper contained in the film from diffusing into the active layer of the TFT.

Next, an opening is formed at a position that is a part of the insulating film 304 and overlaps with the wiring 220 by photolithography, and a pixel electrode 222 is formed. At this time, the pixel electrode 222 and the wiring 220 are electrically connected through the opening (FIG. 3A).

Note that FIGS. 3B to 3D illustrate a configuration in which the manufacturing order of the wiring 220, the insulating film 304, or the pixel electrode 222 and the manufacturing method of the opening of the insulating film 304 are different.

For example, FIG. 3B is different from the structure shown in FIG. 2C in that after the pixel electrode 222 is formed, the wiring 220 made of the barrier conductive film, the conductive conductive film, and the conductive mainly composed of copper. In this configuration, the signal line 201 and the current supply line 202 are formed of a laminated film with the film, and finally the insulating film 304 is formed.

3C, the insulating film 304 is formed after the wiring 220, the signal line 201, and the current supply line 202 are formed as in FIG. 3A. However, in this case, the insulating film 305 is formed, and the second barrier insulating film 306 is formed over the insulating film 305. An opening is formed in the insulating film 305 and the second barrier insulating film 306, and a pixel electrode 222 electrically connected to the wiring 220 is formed in the opening. Note that the insulating film 305 may be formed using a material and a method similar to those of the interlayer insulating film 218a, and the second barrier insulating film 306 may be formed using a material and a method similar to those of the first barrier insulating film 219.

3D is different from FIGS. 3A to 3C in that the method for forming the insulating film 304 is different from that in FIGS. 3A to 3C, and the insulating film 304 is formed only over the wiring containing copper using a mask. is there. Therefore, in this case, it is not necessary to form an opening in the insulating film 304 using photolithography. Note that the structure illustrated in FIG. 3D can be applied to a method for manufacturing the insulating film 304 having the structure illustrated in FIGS.

Note that in the case where the insulating film 304 is formed only over the wiring containing copper as illustrated in FIG. 3D, the insulating film 304 can be formed using the same material as the barrier conductive films 201a and 202a.

Further, in FIG. 4, after forming up to the pixel electrode 222 in FIG. 3, a bank (also referred to as a partition wall, a barrier, a bank, or the like) is formed so as to cover the end of the pixel electrode, the wiring, the signal line, and the scanning line. A method for manufacturing the light-emitting layer of the light-emitting element and the second electrode over the electrode will be described.

4A is obtained by forming an opening over the pixel electrode 222 after forming the insulating film 305 over the entire surface in addition to the structure shown in FIG. The insulating film 305 is a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, resist or benzocyclobutene), an inorganic material (silicon oxide, silicon nitride, oxide) by a CVD method, a sputtering method, or a coating method. (Such as silicon nitride) or a stack of these. In addition, a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and at least one of a material containing at least hydrogen as a substituent or a fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. You may form using the material (typically siloxane type polymer) which has a seed. Note that in the case where a photosensitive organic material is used for the insulating film 305, the photosensitive organic material is roughly divided into two types, a negative type that becomes insoluble in an etchant by photosensitive light, or a soluble type in an etchant by light. There is a positive type as described above, but either can be used in the present invention.

Next, a light emitting layer 310 containing an organic compound is formed in the opening, and a second electrode 307 is formed on the light emitting layer 310. In addition, before or after the formation of the light emitting layer 310, it is preferable to perform deaeration by performing vacuum heating. Note that since the layer 310 containing an organic compound is extremely thin, the surface of the first electrode is preferably flat. For example, a process of chemically and mechanically polishing before or after patterning of the pixel electrode 222 (see FIG. Planarization may be performed by CMP technology or the like. Further, in order to improve the cleanliness on the surface of the pixel electrode 222, cleaning (brush cleaning or Bergrin cleaning) for cleaning foreign matter (dust or the like) may be performed.

Note that the opening portion of the insulating film 305 illustrated in FIG. 4A has a tapered shape with a diameter that decreases toward the bottom, and includes an upper surface of the insulating film 305, a slope of the opening portion, and a corner portion of the opening portion. The angle formed is about 95 to 135 degrees.

4B differs from FIG. 4A in which the corners of the opening are tapered, and the corners of the opening are rounded and the diameter decreases as it goes downward. ing. At this time, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, resist, or benzocyclobutene) is used as the material of the insulating film 305, and the opening is formed using a wet etching method or a dry etching method. May be formed.

In FIG. 4C, the shape of the taper of the opening is further different, the corner of the opening is rounded, and the opening has a slope having two or more different radii of curvature. . At this time, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, resist, or benzocyclobutene) is used as the material of the insulating film 305, and the opening is formed using a wet etching method or a dry etching method. May be formed.

Note that FIG. 4D is an enlarged view of a portion indicated by 308 with respect to the shape of the opening of the insulating film 305 in FIG. That is, the lower end portion of the insulating film 305 is in contact with the upper surface of the pixel electrode 222, and is a curved surface determined by the center of curvature (O ₁ ) and the first radius of curvature (R ₁ ) above the tangent line between the pixel electrode 222 and the lower end portion. Having a side surface. The upper end portion of the insulating film 305 is in contact with the upper surface of the insulating film 305 and has a curved side surface determined by the center of curvature (O ₂ ) and the second radius of curvature (R ₂ ) below the tangent line between the upper end portion and the upper surface. Have

4A to 4C have been described using the configuration shown in FIG. 3A, but are shown in FIGS. 3B to 3D and further to FIGS. 2A to 2E. It can be used in combination with any of the configurations described above.

Next, a specific laminated structure of the wiring formed in the present invention will be described with reference to FIG. FIG. 5 shows a structure of a portion indicated by a region b (309) in FIG.

In FIG. 5A, a Ti film and a TiN film are stacked on the insulating film 501 as a barrier conductive film 502. That is, a Ti film is first formed on the insulating film 501, and a TiN film having a barrier property against Cu is formed on the Ti film. Further, a Cu film is formed as the conductive film 503 containing copper as a main component over the barrier conductive film 502. Here, a barrier insulating film 504 made of a SiN film is formed on the copper film.

FIG. 5B shows a structure in which a barrier conductive film 502 is further stacked. That is, it is a laminated film of a Ti film, an Al film, and a TiN film.

FIG. 5C shows a case where the structure of the barrier conductive film 502 has a laminated structure of a Ti film and a TaN film, and FIG. 5D shows a laminated structure of the Ti film and the WN film. A case having a structure will be described. Note that a barrier insulating film 504 is formed in the same manner as in FIG.

Note that what is shown here is an example of a combination of wiring structures formed by stacking the conductive films of the present invention, and the combination of the materials described above is not limited to the structure shown in FIG. it can.

(Embodiment 3)
In this embodiment, an example in which a wiring including copper is applied to a gate electrode will be described with reference to FIG.

FIG. 6A shows an equivalent circuit of one pixel of the light emitting device. As shown in FIG. 6A, one pixel of the display device includes at least a signal line 601, a current supply line 602, a scanning line 603, a plurality of TFTs 604 and 605, a capacitor 606, and a light-emitting element 607. Each TFT may have a multi-gate structure such as a double gate structure or a triple gate structure instead of a single gate structure.

FIG. 6B is a top view of FIG. 6A in which the pixel electrode (first electrode of the light emitting element) 622 is formed. The signal line 601, the current supply line 602, the scanning line 603, and the TFT 604 are shown. 605, a capacitor element 606, and a pixel electrode 622 of a light emitting element, and a conductive film 603b containing copper as a main component is provided over the barrier conductive film 603a as the gate electrode of the scanning line 603 and the TFT 604.

FIG. 6C is a cross-sectional view taken along B-B ′ of FIG. First, as in FIG. 2, a substrate 611 having an insulating surface, a silicon oxynitride film 612a, a silicon oxynitride film 612b, and a semiconductor film 613 of the TFT 604 and the TFT 605 are provided as a base film. A gate insulating film 614 is provided so as to cover the semiconductor film 613, and a barrier conductive film 603a and a conductive film 603b containing copper as a main component are provided over the semiconductor film. That is, this embodiment is characterized in that a wiring containing copper is used for the gate electrode. Note that Embodiment 1 may be referred to for a method for forming a wiring containing copper. The barrier conductive film 603a is formed using one or more kinds of stacked films selected from tantalum nitride (TaN), titanium nitride (TiN), and tungsten nitride (WN). This barrier conductive film 603 a has a function as a protective film for preventing copper from entering the semiconductor film 613 by diffusion.

By patterning the same layer (same layer) as the gate electrode, the scanning line 603 is formed simultaneously with the gate electrode. That is, the scanning line 603 has a stacked structure of a barrier conductive film 603a and a conductive film 603b containing copper as a main component.

Then, using the gate electrode or resist as a mask, the semiconductor film forms a source region, a drain region, and a channel formation region, and further forms a GOLD structure that overlaps the LDD region and the gate electrode as appropriate. Note that a source region, a drain region, an LDD region, or a GOLD structure to which an impurity is added is referred to as an impurity region. Then, a silicon nitride film or a silicon nitride oxide film is provided as the insulating film 617 that covers the gate electrode.

Next, the impurity region is activated using a heating furnace or a laser. At this time, in order to prevent copper from diffusing and entering the semiconductor film due to heating during activation, a laser (for example, an excimer laser) is preferably applied from the back surface of the substrate (the surface opposite to the surface on which the semiconductor film is formed). Irradiate to activate. Still more preferably, after forming the barrier conductive film 603a, an impurity region is formed, and then the impurity region is activated using a heating furnace or a laser to form a conductive film 603b containing copper as a main component.

Furthermore, on the insulating film 617, for the purpose of planarization, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, resist, or benzocyclobutene), an inorganic material formed by a sputtering method, a CVD method, or a coating method is used. The interlayer insulating film 618 is formed using a material (silicon oxide, silicon nitride, silicon oxynitride, or the like), a siloxane-based polymer, or a stacked layer thereof.

Next, a barrier insulating film 619 made of a nitride insulating film (typically a silicon nitride film or a silicon nitride oxide film) is formed over the interlayer insulating film 618. Note that the barrier insulating film here refers to an insulating film having a function of preventing diffusion of copper. In this embodiment, a silicon nitride film is used as the barrier insulating film 619. After that, contacts (openings) are formed in the barrier insulating film 619, the interlayer insulating film 618, the insulating film 617, and the gate insulating film 614 by using a wet etching method or a dry etching method. Note that any of the structures shown in FIGS. 2C to 2E may be used for the shape of the contact hole, that is, the shape of the interlayer insulating film.

Then, a wiring is formed in the contact hole and connected to the source region or the drain region. At this time, by patterning the same layer (same layer), the signal line 601 and the current supply line 602 are formed at the same time. Thereafter, as shown in FIGS. 3 and 4, a light emitting layer and the like are formed. Note that any of the structures shown in FIGS. 3A to 3D may be used for the pixel electrode to be formed, and the structures of the insulating film and the like when the light emitting layer is formed are shown in FIGS. Any of the configurations may be used.

Thus, it is possible to adapt the wiring including copper to the gate electrode and the scanning line.

As described above, by applying a wiring containing copper to the gate electrode or the scanning line, a voltage drop and a rounded waveform can be reduced, and further, a narrow frame of the light emitting device can be achieved.

(Embodiment 4)
The wiring obtained by the manufacturing method of the present invention can also be used as a lead wiring for a display device.

A source side driver circuit 732, a gate side driver circuit 733, and a pixel portion 734 which are driver circuit portions are formed over a substrate 731 illustrated in FIG. 7A. The source side driver circuit 732 and the gate side driver circuit are provided. 733 is connected to the outside by a lead wiring 735. That is, the wiring of the present invention can be used for the routing wiring 735 shown here. Although not shown here, in the case of a light-emitting device, the current supply line and the second electrode of the light-emitting element formed in each pixel of the pixel portion 734 are also connected to the outside through a lead wiring. Note that it is preferable that the line width of the wiring containing copper formed as the lead wiring in this embodiment be 900 to 1500 μm. Moreover, it is preferable that the connection portion of the routing wiring with the FPC is about 100 to 200 μm.

Note that the routing wiring 735 is connected to the FPC 737 at the connection portion 736.

Here, the structure of the region a (738) shown in FIG. 7A is shown in detail in FIG. In FIG. 7B, reference numeral 701 denotes a barrier conductive film, and reference numeral 702 denotes a conductive film containing copper as a main component, which is formed over the barrier conductive film 701. A wiring 703 formed by stacking these layers is covered with a second insulating film 711. In addition, the barrier conductive film 701 is electrically connected to the scan line 715 in the contact hole 716 provided in the first insulating film 707. Further, the transparent conductive film 704 formed at the same time as the pixel electrode of the pixel portion 734 has the surface removed in the top view of FIG. 7B because the second insulating film 711 formed thereon is removed. Is exposed.

FIG. 7C is a cross-sectional view taken along line A-A ′ of FIG. First, the first insulating film 707 formed simultaneously with the interlayer insulating film is formed over the wiring 706 formed simultaneously with the scanning line. After that, a contact hole (opening) is formed in the first insulating film 707, a barrier conductive film 701 serving as a lead wiring is formed, and connected to the wiring 706 through a contact. Next, a conductive film 702 containing copper as a main component is formed over the barrier conductive film 701. The conductive film 702 containing copper as a main component is patterned so as to extend up to the front of the contact hole. Then, a transparent conductive film 704 is formed so as to be in contact with the barrier conductive film 701. At this time, the transparent conductive film 704 is formed to extend from the first insulating film 707.

Next, a second insulating film 711 is formed over the first insulating film so as to cover the barrier conductive film 701 and the conductive film 702 containing copper as a main component, and the periphery (also referred to as an edge or an edge) of the conductive film 704 is formed. ) To form an opening in the second insulating film 711. Then, the transparent conductive film 704 is exposed (see a top view in FIG. 7B). Note that the margin d between the first insulating film 707 and the second insulating film 711 is several μm, for example, 3 μm.

Next, FIG. 7D shows an enlarged view around the protection circuit 720. In the vicinity of the connection region with the FPC (hereinafter referred to as connection region), the semiconductor layer formed simultaneously with the semiconductor layer of the TFT has a rectangular shape and is provided in a staircase pattern (zigzag). The semiconductor layer 712 is connected to the barrier conductive film 701 and the wiring 706 through a contact hole and functions as a protective circuit. By providing such a protection circuit, the semiconductor film functions as a resistor, and an excessive current due to static electricity or the like can be prevented from flowing to the driver circuit portion or the pixel portion. Further, a TFT may be provided in addition to the semiconductor layer. Further, a combination of a semiconductor layer and a TFT may be provided.

Also, the connection between the FPC terminal and the lead wiring differs depending on the connection destination of the lead wiring depending on the electrode of the light emitting element and the wiring of the drive circuit section. That is, when the connection destination of the routing wiring is an electrode of a light emitting element, the wiring width is designed to be as low as possible so that two FPC terminals are connected to the routing wiring. On the other hand, when the connection destination of the routing wiring is the wiring of the drive circuit, the wiring width is designed to be narrower than the above, and one terminal is connected to the routing wiring. In this way, the number of FPC terminals to be connected is set in consideration of the connection destination of the routing wiring. A protective circuit may be provided for each electrode of the light emitting element and each wiring of the driver circuit portion.

Although not shown in the top view of FIG. 7A, a resin 718 including a conductor 708 is formed in the opening of the second insulating film 711, and the FPC 710 is connected through a wiring 709 provided on the FPC side. To do.

As described above, in this example, by providing the conductive film 702 containing copper as a main component at a necessary portion of the lead wiring, the wiring resistance can be reduced and heat generation from the wiring can be prevented. In particular, when a medium-sized or large-sized panel is used, it is necessary to pass a large current through the wiring. Using the conductive film 702 whose main component is copper having a low electrical resistance as in the present invention, a large current is required. It has the advantage of being able to flow and is useful.

(Embodiment 5)
In this Embodiment 5, an external view of an active matrix light-emitting device among the semiconductor devices of the present invention will be described with reference to FIG. 8A is a top view illustrating the light-emitting device, and FIG. 8B is a cross-sectional view taken along line AA ′ in FIG. 8A. Reference numeral 801 indicated by a dotted line denotes a drive circuit portion (source side drive circuit), 802 denotes a pixel portion, and 803 denotes a drive circuit portion (gate side drive circuit). Reference numeral 804 denotes a sealing substrate, reference numeral 805 denotes a sealing agent, and an inner side 807 surrounded by the sealing agent 805 is a space.

Reference numeral 808 denotes a routing wiring for transmitting signals input to the source side driver circuit 801 and the gate side driver circuit 803, and a video signal, a clock signal, and a start signal from an FPC (flexible printed circuit) 809 serving as an external input terminal. Receive signals, reset signals, etc. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only a light-emitting device body but also a state in which an FPC or a PWB is attached thereto.

Next, the cross-sectional structure will be described with reference to FIG. A driver circuit portion and a pixel portion are formed over the element substrate 810. Here, a source side driver circuit 801 which is a driver circuit portion and a pixel portion 802 are shown.

Note that the source side driver circuit 801 is a CMOS circuit in which an n-channel TFT 823 and a p-channel TFT 824 are combined. The TFT forming the driving circuit may be formed by a known CMOS circuit, PMOS circuit or NMOS circuit. In this embodiment mode, a driver integrated type in which a driver circuit is formed over a substrate is shown; however, this is not always necessary, and the driver circuit may be formed outside the substrate.

Further, the pixel portion 802 is formed by a plurality of pixels including a switching TFT 811, a current control TFT 812, and a first electrode 813 that is a pixel electrode electrically connected to the drain region thereof. Note that a bank 814 is formed to cover an end portion of the first electrode 813. The bank can be formed using a material similar to that of the interlayer insulating film 218a illustrated in FIG. Note that as a combination of the interlayer insulating film 850 and the bank 814, a combination of inorganic material-inorganic material, organic material-inorganic material, inorganic material-organic material, organic material-organic material, or the like can be appropriately applied. Here, the bank 814 is formed using a positive photosensitive acrylic resin film.

Also, in order to improve the coverage, a curved surface having a curvature is formed at the upper end or the lower end of the bank 814. For example, in the case where positive photosensitive acrylic is used as the material of the insulator 814, it is preferable that only the upper end portion of the bank 814 has a curved surface having a curvature radius (0.2 μm to 3 μm). As the bank 814, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

The electroluminescent layer 816 and the second electrode 817 are formed on the first electrode 813, respectively. Here, as a material used for the first electrode 813, a material having a high work function is preferably used. For example, in addition to a single layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a stack of titanium nitride and a film containing aluminum as a main component, a film containing a titanium nitride film and aluminum as a main component A three-layer structure of titanium nitride film and the like can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained.

The electroluminescent layer 816 is formed by a vapor deposition method using a vapor deposition mask or an ink jet method.

Further, as a material used for the second electrode (cathode) 817 formed on the electroluminescent layer 816, a material having a low work function (Al, Ag, Li, Ca, or alloys thereof MgAg, MgIn, AlLi, CaF) is used. ₂ or CaN). Here, as the second electrode (cathode) 817, a thin metal film, a transparent conductive film (ITO (indium tin oxide alloy), indium oxide zinc oxide alloy (In ₂ ) are used as the second electrode (cathode) 817 so as to transmit light. O ₃ —ZnO), zinc oxide (ZnO), or the like) is used.

Further, the second electrode 817 also functions as a wiring common to all pixels, and is electrically connected to the FPC 809 via a lead wiring 808.

Further, the above effect can be further enhanced by bonding the sealing substrate 804 to the element substrate 810 with the sealant 805.

That is, a light emitting element 818 is provided in a space 807 surrounded by the element substrate 801, the sealing substrate 804, and the sealant 805.

Note that an epoxy resin is preferably used for the sealant 805. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible.

In this embodiment mode, a glass substrate or a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like is used as a material constituting the sealing substrate 804. Can be used.

The fifth embodiment can be freely combined with the first to fourth embodiments.

(Embodiment 6)
Various electric appliances can be completed using a semiconductor device manufactured using the wiring of the present invention. A specific example will be described with reference to FIG.

FIG. 9A shows a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The semiconductor device having the wiring structure of the present invention is manufactured using the display portion 2003. Note that the semiconductor device having the wiring structure of the present invention is suitable for a large display device because it can reduce the wiring resistance. The display device includes a liquid crystal display device, a light emitting device, and the like, and specifically includes all information display devices such as a personal computer, a TV broadcast reception, and an advertisement display.

FIG. 9B shows a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The semiconductor device having the wiring structure of the present invention is used for the display portion 2203.

FIG. 9C illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. The display portion A 2403 mainly displays image information, and the display portion B 2404 mainly displays character information. The semiconductor device having the wiring structure of the present invention is used for the display portions A, B 2403 and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

As described above, the applicable range of the semiconductor device manufactured according to the present invention is so wide that the semiconductor device of the present invention can be applied to electric appliances in various fields. In addition, the electrical appliance of the sixth embodiment can be completed by using the semiconductor device manufactured by implementing the first to fifth embodiments.

8A and 8B illustrate a manufacturing process of a wiring according to the present invention. Sectional drawing explaining the case where the wiring of this invention is used for a signal wire | line. Sectional drawing explaining the case where the wiring of this invention is used for a signal wire | line. Sectional drawing explaining the case where the wiring of this invention is used for a signal wire | line. The figure explaining the specific example of the wiring structure of this invention. Sectional drawing explaining the case where the wiring of this invention is used for a scanning line. The figure explaining the case where the wiring of this invention is used for routing wiring. FIG. 6 illustrates a light-emitting device. The figure explaining an electric appliance.

Explanation of symbols

101 Substrate 102 First conductive film 103 Mask 104 Second conductive film 105 Resist 106 Wiring

Claims (9)

A method for manufacturing a semiconductor device having a wiring formed by stacking conductive films,
Forming a first conductive film having a barrier property on an insulating surface;
The first conductive film is formed into a desired shape by an etching method,
A second conductive film containing copper as a main component is formed on the first conductive film through an opening of a mask, and the width of the second conductive film is narrowed by dry etching. A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device having a wiring formed by stacking conductive films,
Forming a semiconductor layer on the insulating surface;
Forming a first insulating film on the semiconductor layer;
Forming a first conductive film having a barrier property on the first insulating film;
The first conductive film is formed into a desired shape by an etching method,
Forming a second conductive film containing copper as a main component on the first conductive film through a mask opening, and further reducing the width of the second conductive film by dry etching;
An impurity region is formed by adding an impurity element to the semiconductor layer using the first wiring formed of the first and second conductive films as a mask,
Forming a second insulating film covering the first wiring;
Forming a contact hole reaching the impurity region in a part of the second insulating film;
A method for manufacturing a semiconductor device, wherein a second wiring electrically connected to the impurity region is formed over the second insulating film. In claim 2,
A third conductive film having a barrier property on the second insulating film is formed into a desired shape by etching,
Forming a fourth conductive film containing copper as a main component on the third conductive film through the opening of the mask, and further reducing the width of the fourth conductive film by dry etching;
A method for manufacturing a semiconductor device, wherein the second wiring is formed. A method for manufacturing a semiconductor device having a wiring formed by stacking conductive films,
Forming a second insulating film on the semiconductor layer partially including the impurity region and the gate electrode formed on the semiconductor layer via the first insulating film;
Forming a contact hole reaching the impurity region in a part of the second insulating film;
Patterning the first conductive film having a barrier property on the second insulating film by an etching method;
Forming a second conductive film containing copper as a main component on the first conductive film through an opening of a mask, and further reducing the width of the second conductive film by dry etching;
A manufacturing method of a semiconductor device, wherein a wiring electrically connected to the impurity region is formed over the second insulating film. In any one of Claims 1 thru | or 4,
The method for manufacturing a semiconductor device, wherein the first conductive film is made of a material containing TiN as a main component. In any one of Claims 1 thru | or 4,
As the first conductive film, a stacked film of any one of a conductive film containing TiN, TaN, WN, TiC, TaC, or silicon and a material containing Ti as a main component is used. Manufacturing method. In any one of Claims 1 thru | or 4,
The first conductive film is any one of a conductive film containing TiN, TaN, WN, TiC, TaC, or silicon on a conductive film formed of one or more of Ti, Al, Ta, and W. A method for manufacturing a semiconductor device, comprising using a stacked film in which a conductive film of one kind is formed. In any one of Claims 1 thru | or 7,
An insulating film having a barrier property made of any one of silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide is formed by a sputtering method so as to cover the second conductive film. Manufacturing method. In claim 3,
A method for manufacturing a semiconductor device, wherein an insulating film made of silicon nitride or silicon nitride oxide is formed by a sputtering method so as to cover the third or fourth conductive film.

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