JP2004133961A - Data inversion circuit and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel data output circuit for facilitating a timing design in achieving a data inversion function for reducing the number of signals inverted in the output. <P>SOLUTION: In the data inversion circuit, each P pieces of data comparison means 21, 22-(2P), majority decision means 31, 32-(3P), inverted flag generating means 41, 42-(4P) and data inversion means 51, 52-(5P) are in existence, respectively, and each of them is operated in parallel in a single cycle. Furthermore, when generating an inverted flag 40k indicating whether or not parallel data 101, 102-(10P) should be output in inverse, inverted flags 401, 402-(40P) are calculated from outputs from the generating means 41, 42-(4P) and from the generating means (4P) of the cycle that is one cycle prior to the single cycle. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data inversion circuit for sequentially outputting multi-bit parallel data in time, and more particularly to a data inversion circuit suitable for a read-out circuit of a clock synchronous semiconductor device and a semiconductor device to which the circuit is applied. .
[0002]
[Prior art]
In a device that outputs multiple bits in parallel, noise generated at the time of data transition becomes a problem. This noise is remarkably generated particularly at the time of transition when the CMOS logic circuit is inverted, and at the same time, much power is consumed. A data inversion function is known as a technique for reducing the number of transitions when a logic circuit is inverted. The data inversion compares the data of the cycle with the output data of the previous cycle, and when many bits out of all N bits, for example, N / 2 bits or more, are inverted, the logic of the data in the cycle is inverted. This function is intended to reduce the number of bits of data actually output on an external bus to N / 2 bits or less, thereby reducing noise and current consumption.
[0003]
FIG. 8 is a block diagram showing a configuration of a conventional data inversion circuit. The data inversion circuit includes a data comparison circuit 210, a majority decision circuit and a data inversion flag generation circuit 310, a data inversion circuit 510, and a previous data holding circuit 810. The operation of the circuit having the data inversion function will be described below step by step.
[0004]
1. The data comparison circuit 210 compares the data 110 of the data bus with the data 820 of the previous cycle output from the previous data holding circuit 810 for each bit position. The comparison flag 220 is set (high level).
[0005]
2. The majority decision circuit and the data inversion flag generation circuit 310 count the number of the comparison flags 220 at the high level, and set the inversion flag 410 when the data 110 is switched at N / 2 or more bit positions. (To high level).
3. When the inversion flag 410 is on, the data inversion circuit 510 inverts the data 110 on the data bus and outputs it as output data 500.
[0006]
4. The previous data holding circuit 810 holds the output data 500 actually output.
[0007]
5. Steps 1 to 4 are repeated during burst reading.
[0008]
Note that the previous data holding circuit 810 is provided with a reset signal 830 for setting the previous data signal to an initial state (for example, low level) before starting reading.
[0009]
As described above, by operating the data inversion circuit shown in FIG. 8, the number of inverted data bits in the output data 500 is suppressed to N / 2 bits or less, and noise and current consumption generated by the output circuit are reduced. Can be reduced.
[0010]
In addition, the technique disclosed in Patent Document 1 compares (exclusive OR) read data of a corresponding cycle and read data of one cycle before by the number of bits (exclusive OR) in an LSI chip, and determines the majority of the number of changed values. If the number of changes (the number of bits inverted compared to the read data one cycle before) is large (N / 2 or more), an inverted flag signal (for example, low level) is output, and the output data is simultaneously output. To output the reversed-phase data. As a result, when the number of inverted bits is more than half, by outputting the opposite phase data, the number of inverted bits in the data output from the output buffer can be suppressed to less than half. In addition, a function is provided for notifying an external device whether the output data is inverted by simultaneously outputting a flag signal indicating inversion to the outside. Therefore, this technique has a basic circuit configuration of the data inversion function, and corresponds to the technical content of the conventional example.
[0011]
Further, the techniques disclosed in Patent Literature 2 and Patent Literature 3 have substantially the same problems, effects, and solutions as Patent Literature 1, and correspond to the technical content of the conventional example.
[0012]
[Patent Document 1]
JP-A-7-20973 (pages 2-4, FIG. 1)
[Patent Document 2]
JP-A-8-101813 (page 3, FIG. 1)
[Patent Document 3]
JP-A-10-198475 (page 4, FIG. 1)
[0013]
[Problems to be solved by the invention]
However, when the conventional data inversion technique is applied to a semiconductor device operating with a high-speed clock signal, for example, a double data rate synchronous dynamic random access memory (DDR-SDRAM) or the like, the following problems occur. There is.
[0014]
The DDR-SDRAM outputs data at both a rising edge and a falling edge of a clock signal in one cycle of a given clock signal. Therefore, in the case of the circuit configuration of FIG. 8, the determination of data inversion (from data comparison to generation of an inversion flag signal and inversion of data on the data bus) must be performed within a half cycle of the clock signal. For example, when the frequency of the clock signal is 300 MHz, the time that can be used to determine the data inversion is about 1.67 nS, and the standard specification of the high-level width and low-level width of the clock signal (period of the cycle) (45%), the minimum is 1.5 ns, which makes timing design extremely difficult.
[0015]
Accordingly, a main object of the present invention is to provide a circuit for implementing a data inversion function which can be applied to a semiconductor device or the like which outputs data twice at the rising and falling edges of a clock signal, and to use the data inversion circuit. To provide a semiconductor device that performs data inversion by using the same.
[0016]
[Means for Solving the Problems]
To achieve the above object, according to a first aspect, a semiconductor device according to a first aspect compares data of a certain cycle with output data of a previous cycle and determines a majority of data output from a plurality of output terminals. Is inverted, in a semiconductor device having a data inversion function of inverting and outputting the data of the cycle, a plurality of data in which the order of output from one output terminal among the data is defined are parallelized. A plurality of data comparison circuits for comparing data before and after in time corresponding to each of a plurality of paths to be transferred to the plurality of paths; And a plurality of majority circuits that take the form of a plurality of majority circuits, and invert the data from the plurality of output terminals based on the determination result in the plurality of majority circuits. A plurality of inversion flag generation circuit for generating a lag, the determination of the data inversion of multiple cycles and are configured to perform in parallel.
[0017]
In the present invention, preferably, the semiconductor device is configured such that the data comparison circuit, the majority circuit, the data defined by the rising edge of the double-rate clock signal, and the path through which the data defined by the falling edge are transferred. And a plurality of inversion flag generation circuits.
[0018]
Further, according to a second aspect of the present invention, in a semiconductor device, the semiconductor device has a plurality of data output terminals, and outputs one data output terminal via the one data output terminal. First to P-th ports that output first to P-th (P is a predetermined integer of 2 or more) bit data to be performed in parallel, and the first to P-th bit data are The data is output from one of the data output terminals in order, and includes the first to P-th data comparison circuits corresponding to the first to P-th ports. The data comparison circuit of (1 to P integer) compares the data of the (i-1) th port (however, when i is 1, the Pth port or the initial value) with the data of the ith port. i, and outputs the plurality of data of the semiconductor device. Depending on the terminal, the i-th comparison flag signal corresponding to the number of data output terminals is input corresponding to each of the data comparison circuits of the first to P-th ports, and whether the number of mismatches exceeds a majority A first to a P-th majority decision circuit to be determined; and the first to the P-th inversion flag generation circuits corresponding to the first to the P-th majority decision circuits, wherein an i-th (where i is 1 to 1) The inversion flag generation circuit of (P integer) outputs the inversion flag signal of the (i-1) th port (however, when i is 1, the Pth port or the initial value) and the determination result of the i-th majority circuit. In comparison, an i-th inversion flag signal is output, and when the i-th inversion flag signal indicates inversion, the data of the i-th port is inverted and output from the data output terminal. .
[0019]
In the present invention, preferably, in the semiconductor device, the data of the first to P-th ports for one data output terminal are arranged in the order of the first to P-th ports, and the data is serially converted and output. May be adopted.
[0020]
Further, according to a third aspect of the present invention, a semiconductor device includes a transition of a clock signal from a first logical value to a second logical value, and a transition from the second logical value to the first logical value. A first transition from a first logical value of the clock signal to a second logical value, and a second transition of the second logical value, in the semiconductor device outputting data twice from one data terminal in one clock cycle based on A first and a second data comparison circuit connected to first and second paths through which data respectively output at a second transition from a logical value to the first logical value is transferred; The first data comparison circuit may be configured to control the data at the first transition timing of the clock signal in the first path and the second data of the clock signal immediately before the first transition timing in the second path. The data at the transition timing By comparing and determining whether or not they match, it is determined whether or not data has been switched between the second transition and the first transition before the first transition, and the determination result is used as a first output signal. The second data comparison circuit outputs the data at the first transition timing of the clock signal on the first path and a second transition of the clock signal following the first transition. By comparing and determining whether or not the data at the timing coincides, it is determined whether or not data has switched between the first transition and the second transition following the first transition. 2 as output signals, and the first output signal group from the first data comparison circuit for the number of data terminals of the semiconductor device is input, and the majority of the data in the first output signal group is Switched A first majority circuit that outputs a first determination result signal and a second output signal group from the second data comparison circuits for the number of data output terminals of the semiconductor device. A second majority circuit that determines whether or not a majority of the data in the second output signal group has been switched, and outputs a second determination result signal; and a second majority circuit from the first majority circuit. A first inversion flag generation circuit for generating a first inversion flag from the determination result signal of the first clock signal and the value of the second inversion flag at least one transition before the clock signal; A second inversion flag generation circuit that generates a second inversion flag from the second determination result signal from the circuit and the value of the first inversion flag at least one transition before the clock signal; , Based on the value of the first inversion flag, When the first inversion flag indicates that the majority of the data has been switched, a first data inversion circuit that inverts and outputs the data of the first path and a value based on the second inversion flag are used. A second data inverting circuit that inverts and outputs the data of the second path when the first inversion flag indicates that the majority of the data has been switched, The inversion flag generation circuit is configured to output the first and second inversion flag signals from a control terminal of the semiconductor device as a flag indicating that the output data has been inverted.
[0021]
In the present invention, preferably, in the semiconductor device, the first and second data comparison circuits and the first and second data inversion circuits transfer data of the first and second paths to an output circuit. May be provided at a stage of a latch circuit section provided on a data bus to be provided.
[0022]
In the present invention, preferably, the semiconductor device comprises: a parallel / serial conversion circuit which inputs respective outputs from the first and second data inversion circuits in parallel, converts the parallel / serial data, and outputs the parallel / serial data; An output buffer circuit that inputs output data from the conversion circuit and outputs the output data from the output terminal may be provided.
[0023]
In the present invention, preferably, in the semiconductor device, the latch circuit section is connected to the first and second paths, and the first and second data are output in parallel to the first and second paths. And a second latch circuit for latching and outputting at the first and second transitions of the first clock signal for sampling, and an output of the first latch circuit for the first clock signal for sampling. A third latch circuit which takes in one of the first and second transitions of the clock signal and outputs it at the other transition; and an input of the output of the second latch circuit, the first clock for sampling. A fourth latch circuit that latches and outputs the one of the first and second transitions of the signal, an input of the output of the fourth latch circuit, and the first and second signals of the first clock signal for sampling. Latch out on one of the second transitions And a sixth latch circuit that receives an output of the fifth latch circuit, and latches and outputs the output at the other of the first and second transitions of the sampling clock signal. May be adopted.
[0024]
In the present invention, preferably, in the semiconductor device, the first data inverting circuit inputs an output of the third latch circuit and an inverted signal thereof, and inputs the first inverted flag signal as a selection control signal. A first selection circuit that outputs the inverted signal when the first inverted flag signal indicates inversion, and wherein the second data inversion circuit includes an output of the sixth latch circuit and an inverted signal thereof. And a second selection circuit that inputs the second inverted flag signal as a selection control signal and outputs the inverted signal when the second inverted flag signal indicates inversion. .
[0025]
In the present invention, preferably, in the semiconductor device, the first data comparison circuit inputs data of the first path and an output of the fourth latch circuit, detects a match, and outputs the second data. The comparison circuit may be configured to input the data of the first and second paths and detect a match.
[0026]
In the present invention, preferably, in the semiconductor device, the first inversion flag generation circuit outputs the first determination result signal from the first majority circuit and the second inversion flag generation circuit from the second inversion flag generation circuit. A first comparison circuit for determining whether the two inversion flags match, and an output of the first comparison circuit in response to one of the first and second transitions of the second clock signal for sampling. A seventh latch circuit that outputs the second determination result signal from the second majority circuit. The seventh latch circuit outputs the second determination result signal from the second majority circuit. An eighth latch circuit for latching and outputting at the other of the first and second transitions of the clock signal, the first inversion flag from the first inversion flag generation circuit, and the eighth latch circuit Judge whether the output of A second comparison circuit, and a ninth latch which takes in the output of the eighth comparison circuit at one of the first and second transitions of the second clock signal for sampling and outputs at the other transition And a circuit.
[0027]
In the present invention, preferably, the semiconductor device may be provided with means for resetting the fourth latch circuit. Further, in the present invention, preferably, the semiconductor device may be provided with means for resetting the ninth latch circuit.
[0028]
In the present invention, preferably, the semiconductor device may have a configuration in which the first and second clock signals for sampling are generated from a clock signal supplied to the semiconductor device from outside the semiconductor device and are synchronized with each other. .
[0029]
In the present invention, preferably, the semiconductor device includes a clock-synchronous semiconductor memory that outputs read data from a cell array at rising and falling edges of a clock signal, and clocks read data from the cell array of the semiconductor memory. A configuration may be adopted in which the signal is output from the output terminal at the rising and falling edges of the signal.
[0030]
According to a fourth aspect of the present invention, there is provided the following data inversion circuit. A data inversion circuit according to the present invention is a data inversion circuit for outputting parallel data composed of N (N is an integer of 2 or more) bits, wherein P (P is 2 or more) The logical values at the same bit position of the first to P-th parallel data and the parallel data to be output immediately before are compared for each of the first to P-th parallel data. N sets of first to P-th data comparing means for outputting whether or not the data are logical values are provided in correspondence with the N bits, and the N sets of the p-th (p is an integer of 1 or more and P or less) It is determined whether or not the number of mismatches among the N logical values output from the data comparing means is greater than a predetermined number, and the p-th majority determining means that outputs the determination result as a logical value is 1 To P, the p-1 inversion The p-th inversion flag generation means for judging the coincidence between the output logic value of the lag and the output logic value of the p-th majority judgment means and outputting the logical value of the judgment result as the p-th inversion flag is from p = 2. P, the output logic value of the P-th inversion flag generating means is determined by a data holding means to determine a match between the output logical value held by the data holding means and the output logical value of the first majority determining means. A first inversion flag generating means for outputting the logical value of the first as a first inversion flag, and in accordance with the first to P-th inversion flags, each bit position in the first to P-th parallel data is N sets of first to P-th data inversion means for inverting a logical value are provided corresponding to the N bits, and flag output means for converting the first to P-th inversion flags from parallel to serial and outputting them in time order is provided. The p-th data inversion N sets of data output means corresponding to the N bits are provided, which perform parallel-to-serial conversion of the output of the stage corresponding to p from 1 to P, and output in synchronization with the time of the inversion flag output by the flag output means. It is configured as follows.
[0031]
In the present invention, preferably, at least one of the data comparing unit, the majority determining unit, the inversion flag generating unit, the data inverting unit, the flag output unit and the data output unit operates in synchronization with the clock signal, and synchronizes with the clock signal. The data output unit may output data in synchronization with the data output of the flag output unit and the clock signal.
[0032]
In the present invention, preferably, at least one of the data comparison means, the majority judgment means, the inversion flag generation means, the data inversion means, the flag output means and the data output means operates in synchronization with the rise and fall of the clock signal. The data output of the flag output means synchronized with the rising and falling edges of the clock signal and the data output means may be configured to output the data in synchronization with the rising and falling edges of the clock signal.
[0033]
In the present invention, it is preferable that the data output from the flag output means is the data output from the data output means inverted from the logical value of the original data input to the data inversion circuit. Have information.
[0034]
In the present invention, P is preferably 2 or 4. Also, in the present invention, preferably, the predetermined number is N / 2 or an integer value before and after N / 2.
[0035]
Further, the data inversion circuit according to the present invention may be provided as a semiconductor device provided in a readout circuit.
[0036]
In the present invention, preferably, the semiconductor device converts a plurality of data read from the memory array at a time by the prefetch operation into data corresponding to the rising side of the clock signal and data corresponding to the falling side of the clock signal. It may be configured to include a data inversion circuit of the present invention in which inputs are separated and P is 2.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings.
[0038]
FIG. 1 is a block diagram showing a configuration of a data inversion circuit according to one embodiment of the present invention. The data inversion circuit includes data comparison means 21, 22,... 2P, majority determination means 31, 32,... 3P, inversion flag generation means 41, 42,. , A flag output unit 6, a data output unit 7, and a data holding unit 8. In this embodiment, P is an integer of 2 or more.
[0039]
2P, the data inverting means 51, 52,... 5P, and the data reading means 9 constituting the data output means 7 are composed of N (N is an integer of 2 or more) parallel data. Exists in correspondence with a predetermined one bit.
[0040]
N-bit parallel data 10k (k is an integer indicating 1 to P) output from the parallel data supply unit 1 is input to the data inversion unit 5k, and is also compared with the data comparison unit 2k and the data comparison unit 2 (k + 1). Supplied to However, the parallel data 10P is input to the data inversion means 5P and is also supplied to the data comparison means 2P. The parallel data 100 is supplied to the data comparing unit 21.
[0041]
It is assumed that the smaller the k is, the earlier the parallel data 10k is output by the data output means 7 in time, and the parallel data 100 is the same as the parallel data 10P in the P set of parallel data corresponding to the immediately preceding one. The content is the same.
[0042]
The data comparison means 2k compares the logical values of the corresponding bit positions of the parallel data 10k and the parallel data 10 (k-1), and outputs whether or not they match as a logical value 20k.
[0043]
The majority determination unit 3k inputs the logical value 20k for N bits, determines whether the number of mismatches among the N logical values 20k is larger than a predetermined number, and sets the determination result as the logical value 30k. Output. In this case, the predetermined number is, for example, N / 2 or an integer before and after N / 2.
[0044]
The inversion flag generation unit 4k determines whether the output logical value of the (k-1) th inversion flag 40 (k-1) matches the logical value 30k output from the k-th majority determination unit 3k, and determines the logic of the determination result. The value is output as the k-th inversion flag 40k. However, the inversion flag 400 is output from the data holding unit 8, and the data holding unit 8 holds the inversion flag 40P output from the immediately preceding inversion flag generation unit 4P, and stores the held content in the inversion flag. Output as 400.
[0045]
The data inversion means 5k inverts (logically negates) the logical value of the corresponding bit of the parallel data 10k according to the inversion flag 40k, and outputs it as an output 50k.
[0046]
The flag output means 6 outputs the inversion flag 40k. For example, the inversion flags 40k input in parallel are arranged in chronological order and output from one output terminal in synchronization with a predetermined clock signal (not shown). is there.
[0047]
The data output means 7 outputs the output 50k. For example, the data output means 7 arranges the outputs 50k input in parallel in time order and outputs them from one output terminal in synchronization with a predetermined clock signal (not shown).
[0048]
The data inversion circuit according to one embodiment of the present invention is configured as described above, and the parallel data 10k composed of N bits output from the parallel data supply means 1 is arranged one by one in chronological order. Is compared with the parallel data of the cycle, and if a large number of bits out of all N bits, for example, N / 2 or an integer greater than or equal to N / 2, are inverted, the logic of the parallel data in the cycle is inverted and output. The number of bits of data inverted when output to an external bus or the like by the data output means 7 is suppressed to N / 2 or an integer value before or after N / 2, thereby reducing noise and current consumption generated by the output circuit. You.
[0049]
.. 2P, a large number of determination means 31, 32,... 3P, inversion flag generation means 41,,... 4P, and data inversion means 51, 52,. Each operates in parallel within one cycle. This facilitates the timing design when implementing a data inversion circuit that operates stably even when the operating frequency increases.
[0050]
Further, when generating the inversion flag 40k, the data inversion circuit according to one embodiment of the present invention includes the data actually output from the data inversion circuit immediately before the corresponding cycle and the parallel data of the corresponding cycle. .. 4P and the inversion flag generation unit 4P before the corresponding cycle and the inversion flag generation unit 4P before the inversion flag generation unit 4P. 40P are calculated. This facilitates the timing design when implementing a data inversion circuit that operates stably even when the operating frequency increases.
[0051]
【Example】
Next, in order to describe in more detail, a case where P = 2 and P = 4 will be described in accordance with an embodiment to which the present invention is applied. In the signal names described below, a signal name with _B attached like a signal XYZ_B means an inverted signal (complementary signal) of the signal XYZ. Further, the terminal name / A means an input or output terminal representing an inverted (complementary) signal of the terminal name A.
[0052]
[Example 1]
FIG. 2 is a block diagram showing the configuration of the data inversion circuit according to the first embodiment of the present invention, which corresponds to the case where P = 2. The data inversion circuit according to the first embodiment includes main amplifiers 11, 12, 13, and 14, a parallel-to-serial conversion circuit 15, bus drivers 16 and 17, a latency latch circuit 18, and data comparison circuits 211 and 212. , Majority circuits 311, 312, an inversion flag generation circuit 40, data inversion circuits 511, 512, parallel / serial conversion circuits 61, 71, output buffer circuits 62, 72, and output pins 63, 73. I have.
[0053]
The main amplifiers 11, 12, 13, and 14, the parallel-to-serial conversion circuit 15, the bus drivers 16 and 17, the latency latch circuit 18, the data comparison circuits 211 and 212, the data inversion circuits 511 and 512, the parallel-serial conversion circuit 71, and the output The data read section 90 constituting the buffer circuit 72 and the output pin 73 is provided corresponding to a predetermined bit of parallel data composed of N (N is an integer of 2 or more) bits.
[0054]
Four data read at once from a memory array (not shown) by a prefetch operation or the like are amplified by main amplifiers 11, 12, 13, and 14, respectively, and output as signals of MAQ0, MAQ1, MAQ2, and MAQ3. You. The parallel-to-serial conversion circuit 15 performs parallel-to-serial conversion of the signals MAQ0 and MAQ2 into data MAQR corresponding to the rising side of a clock signal (not shown), and converts the signals MAQ1 and MAQ3 into data MAQF corresponding to the falling side of the clock signal, for example. To parallel-serial conversion. The bus drivers 16 and 17 transmit the data MAQR and the data MAQF as a data signal DATAR_B and a data signal DATAF_B, respectively.
[0055]
The data signal DATAR_B and the data signal DATAF_B are sent to the latency latch circuit 18 and the data comparison circuits 211 and 212. Latency latch circuit 18 delays data signal DATAR_B and outputs data signal DATAR3 to data inverting circuit 511 at a predetermined timing. In addition, the latency latch circuit 18 delays the data signal DATAF_B, outputs the data signal DATAF2_B to the data comparison circuit 211 at a predetermined timing, and outputs the data signal DATAF3 to the data inversion circuit 512 at a predetermined timing.
[0056]
The data comparison circuit 211 compares the data signal DATAR_B on the rising side of the cycle with the data signal DATAF2_B on the falling side of the previous cycle output from the latency latch circuit 18 (exclusive OR), and compares the data on the rising side. The signal INVR is output. Further, the data comparison circuit 212 compares the falling data signal DATAF_B of the cycle with the rising data signal DATAR_B of the cycle to output a falling comparison signal INVF.
[0057]
The meaning of the comparison signals INVR and INVF is whether or not there is data switching. When there is data switching, a high level is output to the comparison signals INVR and INVF.
[0058]
The N comparison signals INVR are input to the majority circuit 311 corresponding to the rising side, and the N comparison signals INVF are input to the majority circuit 312 corresponding to the falling side. The majority decision circuit 311 determines whether or not half or more of the input data is switched, that is, whether or not the number of the high-level comparison signals INVR is equal to or more than N / 2, and determines a majority decision signal according to the determination result. Outputs DATAINVR. The majority decision circuit 312 determines whether or not more than half of the input data is switched, that is, whether or not the number of the high-level comparison signals INVF is greater than or equal to N / 2. It outputs the determination signal DATAINVF. When more than half of the data is switched, the majority decision signals DATAINVR and DATAINVF are each at a high level. Further, the majority decision signals DATAINVR and DATAINVF are sent to the inversion flag generation circuit 40.
[0059]
In the inversion flag generation circuit 40, the inversion flag signal DINVR on the rising side is an arithmetic processing (eg, exclusive OR) of the majority decision signal DATAINVR on the rising side in the cycle and the inversion flag signal DINVF on the falling side in the previous cycle. Generated. The inverted flag signal DINVF on the falling side is generated by performing arithmetic processing (for example, exclusive OR) on the majority decision signal DATAINVF on the falling side of the cycle and the inverted flag signal DINVR on the rising side of the cycle. .
[0060]
In the above, the operation (for example, exclusive OR) of the majority decision signals DATAINVR and DATAINVF and the inverted flag signals DINVR and DINVF is performed on the data of the internal data bus as the data to be compared. This is because the data is different from the data actually output from the output pin 73 to the outside. For example, if the majority circuits 311 and 312 continue to determine that more than half of the data has been switched, the subsequent data must be output without inversion when actually output from the pins. .
[0061]
On the other hand, the inverted flag signal DINVR is sent to the data inverting circuit 511, and the inverted flag signal DINVF is sent to the data inverting circuit 512. The data inversion circuit 511 inverts the data of the data signal DATAR3 when the inversion flag signal DINVR is at the high level, that is, when half or more of the data are switched, and when the inversion flag signal DINVR is at the low level, that is, less than half. Is switched, the data of the data signal DATAR3 is sent to the parallel-to-serial conversion circuit 71 as the output data signal DOR without being inverted.
[0062]
The data inversion circuit 512 inverts the data of the data signal DATAF3 when the inversion flag signal DINVF is at the high level, that is, when half or more of the data are switched, and when the inversion flag signal DINVF is at the low level, If less than half of the data has been switched, the data of the data signal DATAR3 is sent to the parallel-to-serial conversion circuit 71 as an output data signal DOF without inversion. Note that an exclusive OR circuit can be used as a circuit for inverting the output data described above.
[0063]
The parallel-to-serial conversion circuit 71 converts the output data signal DOR corresponding to the rising data and the output data signal DOF corresponding to the falling data from parallel to serial, and sends them to the output buffer circuit 72 in time order as the signal DO. The output buffer circuit 72 amplifies the signal DO and outputs it from the output pin 73 as a signal DQj (j = 1 to N).
[0064]
On the other hand, the inversion flag signals DINVR and DINVF are sent to the serial / parallel conversion circuit 61, where they are converted into parallel / serial, and sent out to the output buffer circuit 62 in time order as the signal DINV. The output buffer circuit 62 amplifies the signal DINV and outputs it from the output pin 63 as a signal DQM. Note that the signal DINV is output in synchronization with the corresponding signal DO.
[0065]
Next, the latency latch circuit 18, the data comparison circuits 211 and 212, the inversion flag generation circuit 40, and the data inversion circuits 511 and 512, which are main parts in the first embodiment described above, will be described in detail. FIG. 3 is a circuit block diagram of a main part according to the first embodiment of the present invention. FIG. 4 is a diagram showing an equivalent circuit of the circuit symbol in FIG.
[0066]
In FIG. 3, reference numerals 1801, 1802, 1804, 1811, 2111, 2112, 2121, 2122, 4001, 4004, 4005, 4007, 4011, 4012, 5111, and 5121 denote inverter circuits. Reference numeral 1807 denotes a NAND circuit. 4009 is a NOR circuit. Reference numerals 2113, 2123, 4002, 4008, 5112, and 5122 denote selection circuits, the equivalent circuits of which are shown in FIG.
[0067]
Reference numerals 1805, 4003, and 4010 denote edge-triggered D flip-flop circuits, the equivalent circuits of which are shown in FIG. Reference numeral 1808 denotes a D flip-flop circuit, an equivalent circuit of which is shown in FIG. Reference numerals 1803, 1806, 1809, 1810, and 4006 denote D flip-flop circuits which output a NOT logic, and an equivalent circuit thereof is shown in FIG.
[0068]
The signals QCLKFF and QCLKFF_B are clock signals having phases opposite to each other. The signals QCLKDINV and QCLKDINV_B are clock signals having phases opposite to each other. These clock signals are synchronized with a clock signal (CLK) (not shown) supplied from outside the data inversion circuit.
[0069]
The signal RSTQ_B is a reset signal for initializing the latency latch circuit 18. The signal RSTDINV is a reset signal for initializing the inversion flag generation circuit 40.
[0070]
Each of the inverter circuits 2111, 2112, 2121, 2122, 4001, 4005, 4007, 4012, 5111, and 5121 generates an inversion signal required at each connection destination.
[0071]
Next, the operation of the signals in FIGS. 2 and 3 will be described. FIG. 5 is a diagram showing a time chart of the operation of the signals in FIG. 2 and FIG.
[0072]
When a read instruction (COMMAND is READ) is received at the timing T0 of the rising edge of the clock signal (CLK) by a circuit (not shown), the main amplifiers 11, 12, 13, and 14 delay the 4-bit data (Q0, Q0, respectively). Q1, Q2, and Q3) are output as signals MAQ0, MAQ1, MAQ2, and MAQ3. Next, the signals MAQ0 and MAQ2 are arranged in chronological order via the parallel / serial conversion circuit 15 and the bus driver 16, and are output as the signal DATAR_B. The signals MAQ1 and MAQ3 are arranged in chronological order via the parallel / serial conversion circuit 15 and the bus driver 17, and are output as a signal DATAF_B.
[0073]
At timing T2 of CLK, data Q0 is output to signal DATAR_B, and data Q1 is output to signal DATAF_B. Further, at the timing of T3 of CLK, the data Q2 is output to the signal DATAR_B and the data Q3 is output to the signal DATAF_B. It is assumed that data Q-1 (initial state) is output from the signal DATAR_B before the timing of T2 of CLK.
[0074]
The signal DATAR_B is input to the latency latch circuit 18, the data comparison circuit 211, and the data comparison circuit 212, and the signal DATAF_B is input to the latency latch circuit 18 and the data comparison circuit 212. The signal DATAR_B input to the latency latch circuit 18 is delayed by about 1.5 clocks via a D flip-flop circuit 1803, an inverter circuit 1804, and an edge trigger type D flip-flop circuit 1805, and the data is inverted as a signal DATAR3. The signal is input to the circuit 511.
[0075]
The signal DATAF_B input to the latency latch circuit 18 is output as a signal DATAF2_B delayed by about one clock through a D flip-flop circuit 1806, a NAND circuit 1808, and a D flip-flop circuit 1808, and furthermore, a D flip-flop circuit The signal is delayed by about 2 clocks via 1809, a D flip-flop circuit 1810, and an inverter circuit 1811 and input to the data inversion circuit 512 as a signal DATAF3. When the low-level signal RSTQ_B is input to the NAND circuit 1808, the D flip-flop circuit 1808, the D flip-flop circuit 1809, and the D flip-flop circuit 1810 are initialized.
[0076]
On the other hand, the signal DATAR_B and the signal DATAF2_B input to the data comparison circuit 211 are input to the data comparison circuit 211, and an exclusive OR operation is performed by the inverter circuit 2111, the inverter circuit 2112, and the selection circuit 2113, and the data comparison is performed. Be done.
[0077]
That is, the signal DATAR_B is supplied to the terminal S of the selection circuit 2113, the signal DATAR_B inverted (logically negated) by the inverter circuit 2111 is supplied to the terminal / S of the selection circuit 2113, the signal DATAF2_B is supplied to the terminal A of the selection circuit 2113, and the signal DATAF2_B is supplied. Is input to the terminal B of the selection circuit 2113 by inverting (logically negating) by the inverter circuit 2112, the logical expression
/Y=DATAF2_B./DATAR_B+/DATAF2_B.DATAR_B
Is performed, and data comparison between the signal DATAF2_B and the signal DATAR_B is performed, and the comparison result is output to the terminal / Y of the selection circuit 2113. That is, if the logical values of the signal DATAF2_B and the signal DATAR_B do not match, the terminal / Y becomes high level and is output as the signal INVR. Here, / represents negation, • represents logical product, and + represents logical sum.
[0078]
The result of the data comparison is input from the data comparison circuit 211 to the majority decision circuit 311 as a signal INVR.
[0079]
On the other hand, the signal DATAR_B and the signal DATAF_B input to the data comparison circuit 212 are input to the data comparison circuit 212, and an exclusive OR operation is performed by the inverter circuit 2121, the inverter circuit 2122, and the selection circuit 2123, and the data comparison is performed. Be done. An operation equivalent to the exclusive OR operation described above is performed, and the result of the data comparison is input from the data comparison circuit 212 to the majority circuit 312 as a signal INVF.
[0080]
N comparison signals INVR are input to the majority circuit 311 corresponding to the rising side, and N comparison signals INVF are input to the majority circuit 312 corresponding to the falling side. The majority circuit 311 determines whether or not half or more of the input data is switched, that is, whether or not the number of the high-level comparison signals INVR is N / 2 or more. A high level is output to the determination signal DATAINVR. Further, the majority decision circuit 312 determines whether or not half or more of the input data is switched, that is, whether or not the number of the high-level comparison signals INVF is equal to or more than N / 2. For example, it outputs a high level to the majority decision signal DATAINVF. Note that a known majority circuit can be used for the majority circuits 311, 312.
[0081]
An exclusive OR operation is performed between the majority decision signal DATAINVR and the inverted flag signal DINVF by the inverter circuit 4001 and the selection circuit 4002, and data comparison is performed. An operation equivalent to the exclusive OR operation described above is performed, and the result of the data comparison is delayed by about one clock through an edge trigger type D flip-flop circuit 4003 and an inverter circuit 4004 and output as a signal DINVR. Is done.
[0082]
Further, the majority decision signal DATAINVF and the inverted flag signal DINVR delayed by about 0.5 clock by the D flip-flop circuit 4006 are subjected to exclusive OR operation by the inverter circuit 4007 and the selection circuit 4008, and data comparison is performed. . An operation equivalent to the exclusive OR operation described above is performed, and the result of the data comparison is delayed by about one clock via a NOR circuit 4009, an edge trigger type D flip-flop circuit 4010, and an inverter circuit 4011. It is output as a signal DINVF. Note that when the high-level signal RSTDINV is input to the NOR circuit 4009, the edge-triggered D flip-flop circuit 4010 is initialized.
[0083]
An exclusive OR operation is performed on the inverted flag signal DINVR and the signal DATAR3 by the inverter circuit 5111 and the selection circuit 5112 in the data inverting circuit 511, and when the inverted flag signal DINVR is at a high level, the inverted signal of the signal DATAR3 is used as the signal DOR. Is output. That is, the data Q0 of the signal DATAR_B appears as data Q0 of the signal DOR or data Q0 whose logic is inverted with a delay of about 2 clocks. Similarly, the data Q2 of the signal DATAR_B is delayed by about 2 clocks and appears as the data Q2 of the signal DOR or the data Q2 whose logic is inverted.
[0084]
An exclusive OR operation is performed on the inverted flag signal DINVF and the signal DATAF3 by the inverter circuit 5121 and the selection circuit 5122 in the data inverting circuit 512. When the inverted flag signal DINVF is at a high level, the inverted signal of the signal DATAF3 is output. Output as DOF. That is, the data Q1 of the signal DATAF_B appears as the data Q1 of the signal DOF or the data Q1 whose logic is inverted with a delay of about 2.5 clocks. Similarly, data Q3 of signal DATAF_B appears as data Q3 of signal DOF or data Q3 whose logic is inverted with a delay of about 2.5 clocks.
[0085]
The data Q0 and Q2 of the signal DOR and the data Q1 and Q3 of the signal DOF are arranged in serial data output in chronological order by the parallel-serial conversion circuit 71, and output from the output pin 73 as a signal DQj by the output buffer circuit 72. .
[0086]
The Q0 flag and Q2 flag of the inverted flag signal DINVR and the Q1 flag and Q3 flag of the inverted flag signal DINVF are arranged in serial data output in chronological order by the parallel / serial conversion circuit 61, and output buffer. The signal DQM is output from the output pin 63 by the circuit 62.
[0087]
Next, changes in each signal will be described using specific examples of numerical data. FIG. 6 is a diagram illustrating an example of a change in data of each signal in the data inversion circuit according to the first embodiment of the present invention.
[0088]
As a specific example, consider a case in which four 8-bit data (Q0, Q1, Q2, and Q3) of “11111111”, “00000000”, “11111111”, and “00000000” are sequentially and sequentially read from the memory. . Each of the signals DATAR_B and DATAF_B output from the bus drivers 16 and 17 is an inverted signal of the data read from the memory in FIGS. 2 and 3. However, in the following description, the non-inverted signal DATAR_B is used for clarity. , DATAF are output.
[0089]
In the cycle in which the data Q0 and Q1 are read, when the value “11111111” of the rising signal DATAR and the initial state “00000000” of the falling signal DATAF are compared (exclusive ethics), all 8 bits are switched. Therefore, “11111111” is output as the rising-side comparison flag signal INVR. When the value of the falling signal DATAF “00000000” is compared with the value of the rising signal DATAR “11111111”, all the 8 bits have been switched, so that the comparison flag signal INVF on the falling side is obtained. “11111111” is output. Since the eight bits are switched, the majority decision signals DATAINVR and DATAINVF are both at a high level (High).
[0090]
The majority decision signal DATAINVR (high level) on the rising side and the initial value (low level) of the inversion flag signal DINVF for the falling side data are subjected to arithmetic processing (exclusive OR), and the inverted flag signal DINVR for the rising side data is obtained. A high level (High) is output. The majority decision signal DATAINVF (high level) on the falling side and the inverted flag signal DINVR (high level) for the data on the rising side are arithmetically processed (exclusive OR), and the inverted flag signal DINVF for the data on the falling side is set to the low level. (Low) is output.
[0091]
Since the inverted flag signal DINVR for the rising-side data is at the high level, the data “11111111” in the cycle Q0 is inverted and output as “00000000” to the signal DQj to indicate that the data is inverted. (High level) is output from the DQM.
[0092]
On the other hand, since the inverted flag signal DINVF for the falling data is at the low level, the data “00000000” in the cycle Q1 is output as “00000000” to the signal DQj without being inverted, and the data is not inverted. Is output as a signal DQM.
[0093]
Similarly, in the cycle in which the data Q2 and Q3 are read, when the value “11111111” of the rising-side signal DATAR and the value “00000000” on the falling side of the previous cycle are compared (exclusive OR), all 8 bits are obtained. Switching. Therefore, “11111111” is output as the rising-side comparison flag signal INVR. When the value of the falling signal DATAF “00000000” and the value of the rising signal DATAR “11111111” are compared, all eight bits are switched. Therefore, “11111111” is output as the falling-side comparison flag signal INVF.
[0094]
Since the eight bits are switched, the majority decision signals DATAINVR and DATAINVF are both at a high level. The majority decision signal DATAINVR (high level) on the rising side and the value (low level) of the inverted flag signal for falling data in the previous cycle are arithmetically processed (exclusive OR), and the inverted flag signal DINVR for the rising data. Output a high level. The majority decision signal DATAINVF (high level) on the falling side and the inverted flag signal DINVR (high level) for the data on the rising side are processed (exclusive OR), and the inverted flag signal DINVF for the data on the falling side is set to low. The level is output.
[0095]
Since the inverted flag signal DINVR for the rising-side data is at the high level, the data “11111111” in the cycle Q2 is inverted and output as “00000000” to the signal DQj to indicate that the data is inverted. (High level) is output as the signal DQM.
[0096]
On the other hand, since the inversion flag signal DINVF for the falling data is at the low level, the data “00000000” in the cycle Q3 is output as “00000000” from DQj without being inverted, indicating that the data is not inverted. The indicated flag signal (low level) is output as signal DQM.
[0097]
In the above description, the data comparison circuits 211 and 212 input data in the internal signals DATAR_B, DATAF_B, and DATAF2_B instead of the data actually output from the output pin 73 to the outside in the data comparison. Therefore, the results of the output signals of the majority circuits 311 and 312 do not match the signals DINVR and DINVF indicating whether the data should be actually inverted.
[0098]
Accordingly, the determination flag generation circuit 40 performs an operation (exclusive OR) between the output signal of the majority circuit 311 and the inverted flag signal DINVF of the previous cycle, and generates signals DINVR and DINVF indicating whether or not the data should be actually inverted. It has gained.
[0099]
The data inversion circuit according to the first embodiment of the present invention is configured as described above, and four data read out from the memory array at a time by a prefetch operation or the like correspond to the rising side of the clock signal. And the data corresponding to the falling side of the clock signal are divided, and each data is operated in parallel within one clock cycle. This facilitates the timing design when implementing a data inversion circuit that operates stably even when the operating frequency increases. Therefore, a data inversion circuit suitable for a DDR-SDRAM or the like can be provided.
[0100]
[Example 2]
FIG. 7 is a block diagram showing the configuration of the data inversion circuit according to the second embodiment of the present invention, which corresponds to the case where P = 4. FIG. 7 shows connection of blocks of a data comparison circuit, a majority decision circuit, and an inversion flag generation circuit, which are main parts of a data inversion circuit, and is an example of a circuit configuration in a case where four systems are serially provided.
[0101]
The exclusive OR circuits 213, 214, 215, and 216 correspond to a data comparison circuit, and exist corresponding to a predetermined bit of parallel data composed of N (N is an integer of 2 or more) bits. The exclusive OR circuits 413, 414, 415, and 416 correspond to an inversion flag generation circuit. Further, the D flip-flop circuit 418 holds the inverted flag signal DINV3 output from the exclusive OR circuit 416 with a clock signal K supplied from a timing circuit or a clock circuit (not shown). The output signal DINV3D of the D flip-flop circuit 418 is input to the exclusive OR circuit 413. Further, the AND circuit 417 initializes the D flip-flop circuit 418 by setting the reset signal RST to low level.
[0102]
Next, processing of a data signal will be described. It is assumed that four bits of prefetched data transmitted serially are input as data Q0, Q1, Q2, and Q3.
[0103]
The exclusive OR circuit 213 compares the data Q-1 corresponding to the initial state (or the data Q3 in the previous cycle) with the data Q0, and outputs a comparison flag signal INV0 as a logical value indicating whether or not they match. Further, the exclusive OR circuit 214 compares the data Q0 and the data Q1, and outputs a comparison flag signal INV1 as a logical value indicating whether or not they match. Further, the exclusive OR circuit 215 compares the data Q1 and the data Q2, and outputs a comparison flag signal INV2 as a logical value indicating whether or not they match. Further, the exclusive OR circuit 216 compares the data Q2 and the data Q3, and outputs a comparison flag signal INV3 as a logical value indicating whether or not the data Q2 matches the data Q3.
[0104]
The comparison flag signal INV0 for N bits is input to the majority circuit 313, and the majority circuit 313 determines whether or not the number of mismatches among the N logical values is greater than a predetermined number, and determines the determination result as a logical value. The majority decision signal DTAINV0 is output. In this case, the predetermined number is, for example, N / 2 or an integer before and after N / 2. In the following description, the predetermined number is a similar value.
[0105]
The N-bit comparison flag signal INV1 is input to the majority circuit 314, and the majority circuit 314 determines whether or not the number of mismatches among the N logical values is larger than a predetermined number, and determines the determination result as a logical value. The majority decision signal DTAINV1 is output. Further, the comparison flag signal INV2 for N bits is input to the majority decision circuit 315, and the majority decision circuit 315 determines whether or not the number of mismatches among the N logical values is larger than a predetermined number, and determines the logical result. The majority decision signal DTAINV2 is output as a value. Further, the comparison flag signal INV3 for N bits is input to the majority decision circuit 316, and the majority decision circuit 316 determines whether or not the number of unmatched N logic values is greater than a predetermined number, and determines the determination result as a logical value. The majority decision signal DTAINV3 is output as a value.
[0106]
The exclusive OR circuit 413 compares the inverted flag signal DINV3D for the initial state or the previous cycle with the majority decision signal DTAINV0, and outputs the inverted flag signal DINV0 as a logical value indicating whether or not they match. Further, the exclusive OR circuit 414 compares the inverted flag signal DINV0 with the majority decision signal DTAINV1, and outputs the inverted flag signal DINV1 as a logical value indicating whether or not they match.
[0107]
The exclusive OR circuit 415 compares the inverted flag signal DINV1 with the majority decision signal DTAINV2, and outputs an inverted flag signal DINV2 as a logical value indicating whether or not they match. Further, the exclusive OR circuit 416 compares the inverted flag signal DINV2 with the majority decision signal DTAINV3, and outputs an inverted flag signal DINV3 as a logical value indicating whether or not they match. The inverted flag signal DINV3 is held by the D flip-flop 418 via the AND circuit 417, and is output as the inverted flag signal DINV3D in the next cycle.
[0108]
In the case of the circuit configuration described above, since four data are processed in parallel, the data inversion need be determined only once for two cycles of the clock signal. Therefore, the timing design for realizing a data inversion circuit that operates stably even when the clock signal frequency increases becomes easy.
[0109]
As described above, the present invention has been described with reference to the above embodiments. However, the present invention is not limited only to the configuration of the above embodiments, and a person skilled in the art should be within the scope of the claims of the present application. Of course, various changes and modifications that could be made are included.
[0110]
【The invention's effect】
As described above, the data inversion circuit according to the present invention has a plurality of processing circuits, and performs the data inversion determination in parallel, thereby facilitating the timing design for realizing the data inversion function. It becomes. Further, by applying the data inversion circuit according to the present invention to a semiconductor device (such as DDR-SDRAM) having a double data rate function, even if the frequency of the clock signal is increased, the data inversion function can be realized. Timing design becomes easy.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a data inversion circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a data inversion circuit according to a first example of the present invention.
FIG. 3 is a circuit block diagram of a main part according to the first embodiment of the present invention.
4 is a diagram showing an equivalent circuit of the circuit symbol in FIG.
FIG. 5 is a diagram showing a time chart of the operation of the signals in FIGS. 2 and 3;
FIG. 6 is a diagram illustrating an example of a change in data of each signal in the data inversion circuit according to the first example of the present invention.
FIG. 7 is a block diagram illustrating a configuration of a data inversion circuit according to a second example of the present invention.
FIG. 8 is a block diagram showing a configuration of a conventional data inversion circuit.
[Explanation of symbols]
1 Parallel data supply means
6 Flag output means
7 Data output means
8 Data holding means
9 Data reading means
11, 12, 13, 14 Main amplifier
15,61,71 Parallel / serial conversion circuit
16, 17 bus driver
18 Latency latch circuit
21, 21,... 2P data comparison means
31, 32,... 3P majority determination means
40 Inversion flag generation circuit
41, 42,... 4P inversion flag generation means
51, 52,... 5P data inversion means
62, 72 output buffer circuit
63, 73 output pin
90 Data reading unit
100, 101, 102, ... 10P parallel data
201, 202,... 20P logical value
211, 212 Data comparison circuit
213, 214, 215, 216, 413, 414, 415, 416 Exclusive OR circuit
.., 30P logical value
311, 312, 313, 314, 315, 316 majority circuit
.., 40P inversion flag
417 AND circuit
418, 1808 D flip-flop circuit
501, 502, ... 50P output
511, 512 Data inversion circuit
1801, 1802, 1804, 1811, 2111, 2112, 2121, 2122, 4001, 4004, 4005, 4007, 4011, 4012, 5111, 5121 Inverter circuit
1803, 1806, 1809, 1810, 4006 D flip-flop circuit outputting negative logic
1805, 4003, 4010 Edge trigger type D flip-flop circuit
1807 NAND circuit
2113, 2123, 4002, 4008, 5112, 5122 Selection circuit
4009 NOR circuit

Claims (23)

A semiconductor having a data inversion function of comparing data of a certain cycle with output data of a previous cycle and inverting and outputting the data of the cycle when a majority of data output from a plurality of output terminals is inverted. In the device,
A data comparison circuit that compares the data before and after in time corresponding to each of a plurality of paths in which a plurality of data, the order of which is output from one output terminal between data, is transferred in parallel. Multiple,
The comparison result in the data comparison circuit is input for a plurality of output terminals, and a plurality of majority circuits for taking a majority decision are provided.
A plurality of inversion flag generation circuits that generate an inversion flag indicating that data from the plurality of output terminals is inverted and output based on the determination result in the plurality of majority circuits;
A semiconductor device having a configuration in which data inversion for a plurality of cycles is determined in parallel. The data comparison circuit, the majority circuit, and the inversion flag generation circuit each include a plurality of data paths for data defined by rising edges and falling edges of the double-rate clock signal. The semiconductor device according to claim 1, wherein A semiconductor device having a plurality of data output terminals,
A first to a P-th (P is a predetermined integer of 2 or more) bit data to be output via the one data output terminal per one data output terminal in parallel. A first to a P-th port, and the first to the P-th bit data are output from one of the data output terminals in this order;
The first to P-th data comparison circuits are provided corresponding to the first to P-th ports, and the i-th (where i is an integer of 1 to P) data comparison circuit is an (i−1) -th data comparison circuit. Comparing the data of the port (where i is 1, the P-th port or the initial value) with the data of the i-th port to output an i-th comparison flag signal;
According to the plurality of data output terminals of the semiconductor device, i-th comparison flag signals corresponding to the number of data output terminals are input corresponding to the data comparison circuits of the first to Pth ports. A first to P-th majority circuit for determining whether the number of mismatches exceeds a majority,
The first to P-th inversion flag generation circuits corresponding to the first to P-th majority decision circuits;
The i-th (where i is an integer of 1 to P) inversion flag generation circuit outputs the inversion flag signal of the (i-1) -th port (however, when i is 1, the P-th port or the initial value) And a comparison result of the i-th majority circuit and outputs an i-th inversion flag signal,
When the i-th inversion flag signal indicates inversion, the data of the i-th port is inverted and output from the data output terminal. The data of the first to P-th ports for one data output terminal are arranged in the order of the first to P-th ports, and the data is converted and output serially, and is output. Semiconductor device. Based on the transition of the clock signal from the first logical value to the second logical value and the transition from the second logical value to the first logical value, the data is transmitted twice from one data terminal during one clock cycle. In a semiconductor device that outputs
Data output at a first transition from a first logical value to a second logical value of the clock signal and at a second transition from the second logical value to the first logical value are transferred. And first and second data comparison circuits connected to the first and second paths, respectively, wherein the first data comparison circuit operates at a first transition timing of the clock signal on the first path. Is compared with the data at the second transition timing of the clock signal immediately before the first transition timing on the second path to determine whether the first transition occurs. Determining whether there is a data switch between the second transition and the first transition before and outputting a determination result as a first output signal;
The second data comparison circuit may be configured to control the data at the first transition timing of the clock signal and the data at a second transition timing of the clock signal following the first transition in the first path. By comparing and determining whether or not the data matches, it is determined whether or not data has switched between the first transition and the second transition following the first transition, and the determination result is output to a second output. Output as a signal,
A first output signal group from the first data comparison circuit for the number of data terminals of the semiconductor device is input, and it is determined whether or not a majority of the first output signal group has been switched. A first majority circuit that outputs a first determination result signal;
The second output signal group from the second data comparison circuit corresponding to the number of data output terminals of the semiconductor device is input, and it is determined whether or not a majority of the second output signal group is switched. A second majority circuit that outputs a second determination result signal;
A first inversion flag for generating a first inversion flag from the first determination result signal from the first majority circuit and a value of a second inversion flag at least one transition before the clock signal; A flag generation circuit;
A second inversion flag for generating a second inversion flag from the second determination result signal from the second majority circuit and the value of the first inversion flag at least one transition before the clock signal; An inversion flag generation circuit;
A first data inverting circuit that inverts and outputs the data of the first path when the first inversion flag indicates that a majority of the data has been switched based on the value of the first inversion flag; ,
A second data inverting circuit that inverts and outputs data of the second path when the first inversion flag indicates that majority data has been switched based on the value of the second inversion flag; ,
With
The first and second inversion flag generation circuits output the first and second inversion flag signals from a control terminal of a semiconductor device as a flag indicating that output data has been inverted. apparatus. A latch circuit unit, wherein the first and second data comparison circuits and the first and second data inversion circuits are provided on a data bus through which data of the first and second paths is transferred to an output circuit 6. The semiconductor device according to claim 5, wherein the semiconductor device is provided in a stage. A parallel-to-serial conversion circuit that inputs respective outputs from the first and second data inversion circuits in parallel, converts the data from parallel to serial, and outputs the result;
6. The semiconductor device according to claim 5, further comprising: an output buffer circuit that inputs output data from the parallel / serial conversion circuit and outputs the output data from an output terminal. The latch circuit section includes:
The first and second data connected to the first and second paths and output in parallel to the first and second paths are converted to the first and second data of the first clock signal for sampling. First and second latch circuits that output latches at the transition of
A third latch circuit that takes in the output of the first latch circuit at one of the first and second transitions of the first clock signal for sampling and outputs the other at the other transition;
A fourth latch circuit that receives an output of the second latch circuit, and that latches and outputs at the one of the first and second transitions of the first clock signal for sampling;
A fifth latch circuit that receives an output of the fourth latch circuit and latches and outputs the first clock signal for sampling at the one of the first and second transitions;
A sixth latch circuit which receives the output of the fifth latch circuit, and latches and outputs the output at the other of the first and second transitions of the sampling clock signal;
7. The semiconductor device according to claim 6, comprising: The first data inverting circuit inputs the output of the third latch circuit and its inverted signal, inputs the first inverted flag signal as a selection control signal, and the first inverted flag signal And a first selection circuit for outputting the inverted signal.
The second data inverting circuit inputs the output of the sixth latch circuit and its inverted signal, inputs the second inverted flag signal as a selection control signal, and the second inverted flag signal 9. The semiconductor device according to claim 8, further comprising a second selection circuit that outputs the inverted signal when indicated. The first data comparison circuit inputs data of the first path and an output of the fourth latch circuit to detect a match,
9. The semiconductor device according to claim 8, wherein the second data comparison circuit inputs data of the first and second paths and detects a match. The first inversion flag generation circuit determines whether the first determination result signal from the first majority circuit matches the second inversion flag from the second inversion flag generation circuit. A first comparison circuit;
A seventh latch circuit that captures an output of the first comparison circuit at one of the first and second transitions of the second clock signal for sampling and outputs the output at the other transition,
The second inversion flag generation circuit latches the second determination result signal from the second majority circuit at the other of the first and second transitions of the second clock signal for sampling. An eighth latch circuit for outputting,
A second comparison circuit that determines whether the first inversion flag from the first inversion flag generation circuit matches the output of the eighth latch circuit,
A ninth latch circuit which takes in the output of the eighth comparison circuit at one of the first and second transitions of the second clock signal for sampling and outputs at the other transition;
9. The semiconductor device according to claim 8, comprising: 9. The semiconductor device according to claim 8, further comprising: means for resetting said fourth latch circuit. 12. The semiconductor device according to claim 11, further comprising means for resetting said ninth latch circuit. 12. The semiconductor device according to claim 11, wherein the first and second clock signals for sampling are generated from clock signals supplied to the semiconductor device from outside the semiconductor device, and are synchronized with each other. The semiconductor device includes a clock-synchronous semiconductor memory that outputs read data from a cell array at rising and falling edges of a clock signal, and reads read data from the cell array of the semiconductor memory with rising and falling clock signals. 12. The semiconductor device according to claim 11, wherein the signal is output from an output terminal at an edge of the signal. In a data inversion circuit that outputs parallel data composed of N (N is an integer of 2 or more) bits,
The parallel data is classified into sets of P (P is an integer of 2 or more) adjacent to each other in the order of time of output, and each of the first to P-th parallel data is output as the immediately preceding output target. N sets of first to P-th data comparing means for comparing logical values at the same bit position with the parallel data and outputting whether or not they match as logical values, corresponding to the N bits,
It is determined whether or not the number of mismatches among the N logical values output from the N sets of the p-th (p is an integer not less than 1 and not more than P) data comparison means is greater than a predetermined number. , P is provided corresponding to P from 1 to P,
Generating a p-th inversion flag that determines whether the output logic value of the (p−1) -th inversion flag matches the output logic value of the p-th majority determination unit and outputs the logical value of the determination result as the p-th inversion flag Means are provided for p from 2 to P,
It is determined whether the output logical value of the P-th inversion flag generating means matches the output logical value held by the data holding means with the output logical value of the first majority determining means, and the logical value of the determination result is set to the first logical value. A first inversion flag generation unit that outputs the inversion flag,
First to P-th data inversion means for inverting logical values of respective bit positions in the first to P-th parallel data according to the first to P-th inversion flags correspond to the N bits. N sets
A flag output unit configured to convert the first to Pth inversion flags from parallel to serial and output them in chronological order;
Data output means for performing parallel-to-serial conversion on the output of the p-th data inversion means in accordance with p from 1 to P, and outputting in synchronization with the time of the inversion flag output by the flag output means, A data inversion circuit comprising N sets correspondingly. At least one of the data comparison unit, the majority determination unit, the inversion flag generation unit, the data inversion unit, the flag output unit, and the data output unit operates in synchronization with a clock signal and synchronizes with the clock signal. 17. The data inversion circuit according to claim 16, wherein the data output means outputs data in synchronization with the data output of the flag output means and the clock signal. At least one of the data comparison unit, the majority determination unit, the inversion flag generation unit, the data inversion unit, the flag output unit, and the data output unit operate in synchronization with rising and falling of a clock signal, 17. The data output of the flag output means synchronized with rising and falling of the clock signal and outputting data from the data outputting means synchronized with rising and falling of the clock signal. Data inversion circuit. The data output from the flag output means has information on whether or not the data output from the data output means is the logical value of the original data input to the data inversion circuit inverted. 17. The data inversion circuit according to claim 16, wherein: 17. The data inversion circuit according to claim 16, wherein said P is 2 or 4. 17. The data inversion circuit according to claim 16, wherein the predetermined number is N / 2 or an integer before and after N / 2. A semiconductor device comprising the data inversion circuit according to any one of claims 16 to 21. A plurality of data read at one time from the memory array by the prefetch operation are separately input into data corresponding to the rising side of the clock signal and data corresponding to the falling side of the clock signal, and P is 2 17. A semiconductor device comprising the data inversion circuit according to claim 16.

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