JP2004128934A - Video signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a pseudo contour enhancement signal generated in the boundary section of a video display region in order to display images without quality deterioration in a video signal processing circuit used in a image display device. <P>SOLUTION: A luminance level and a threshold YH level for a top pixel and a bottom pixel of a target pixel are determined by a luminance level determining circuits 151 and 152, and the AND output is counted for a period of 50% or more of 1H duration by a 1H counter circuit 154. The result of the count is compared with a determination value by a count value determining circuit 155 to detect a video display region. According to the control of a switch circuit 130 only for the detected video display region to turn on a contour enhancement signal, a pseudo contour enhancement signal is not superimposed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides an image signal processing circuit for enhancing the contour of an image display device, which detects a video display region of a video signal and removes an error signal generated at a boundary between the video display region and a blanking region to improve image quality. The present invention relates to an image signal processing circuit.
[0002]
[Prior art]
2. Description of the Related Art In recent years, there has been an increasing demand for large-screen image display devices for enjoying powerful images with the enhancement of video equipment such as video disc players and video software.
[0003]
FIG. 5 is a configuration diagram showing a configuration of an example of a projection type image display device using a liquid crystal panel as an example of a large screen display device.
[0004]
In FIG. 5, 1 is a liquid crystal panel, 2 is a light source for illuminating the liquid crystal panel 1, 3 is a reflecting mirror for reflecting light emitted from the light source 2, and 4 is light and a reflecting mirror emitted from the light source 2. A condensing lens for condensing the light reflected at 3, a projection lens 5 for enlarging and projecting an image displayed on the liquid crystal panel 1, a screen 6 and a processing unit 11 for processing an input image signal. A video signal processing unit for converting the data into a format to be displayed on the liquid crystal panel 1; a synchronization signal separation unit 12; a liquid crystal panel drive control unit 13 for generating a control signal for driving the liquid crystal panel 1 from the synchronization signal; The horizontal scanning driver section of the panel 1, 15 is a vertical scanning driver section of the liquid crystal panel 1, 16 is a light source driving section of the light source 2, and 17 is a whole system control section.
[0005]
FIG. 6 is a block diagram illustrating an example of the configuration of the video signal processing unit 11.
[0006]
In FIG. 6, reference numeral 20 denotes a color signal demodulation unit for separating a video signal into a luminance signal and a color difference signal, 30 denotes a luminance signal adjustment unit that performs various image quality adjustments on the luminance signal, and 40 performs various image quality adjustments on the color difference signal. A color difference signal adjustment unit 50 is a matrix circuit unit for converting the luminance signal and the color difference signal into red, green, and blue video signals. The luminance signal adjustment unit 30 includes a black level adjustment unit 31, a contrast adjustment unit 32, an outline emphasis unit 33, and the like. The color difference signal adjustment unit 40 includes a hue adjustment unit 41, a color density adjustment unit 42, and the like.
[0007]
When images are displayed on a conventional small screen, even if the image quality of the displayed image is considered to be at a sufficient level, the image is displayed when the image is displayed on a large screen using a projection image display device. Image quality often seems insufficient, and various methods for improving the quality of displayed images have been proposed.
[0008]
As one means for improving the image quality of an image, there is a method of edge enhancement in which a correction signal for enhancing the edge of the image is superimposed on the image signal by the edge enhancement unit 33 to sharpen the edge as shown in FIG. is there.
[0009]
A well-known method of contour enhancement is to generate a second derivative signal of the luminance signal of the video signal in the horizontal or vertical direction and convert the signal into an appropriate level as an original signal for contour enhancement. There is a method of adding to the luminance signal. Here, adding a contour enhancement signal generated from the secondary differential signal in the horizontal direction is horizontal contour enhancement, and adding a vertical enhancement signal is vertical contour enhancement.
[0010]
As described above, the contour emphasis signal is generated from the second derivative signal of the video signal. At the boundary between the video display area and the blanking area, the second derivative signal is generated in principle due to the discontinuity of the video signal. Would. By using this as a contour emphasizing signal and performing the subsequent processing, a contour correction signal is added to the boundary, and the luminance level of the boundary rises to create an edge (hereinafter, this state is referred to as a false edge). Name). In a conventional television receiver, the image display area of the image signal is made larger than the display area of the cathode ray tube, that is, so-called overscanning is performed so that the above-described defective portion is not displayed.
[0011]
On the other hand, a large screen display device such as a projection type image display device often displays a 16: 9 image on a display screen having an aspect ratio of 4: 3, for example, like a letterbox image. In this case, blanking areas are displayed in the upper and lower parts of the screen, so that a boundary with the video display area is inevitably displayed on the screen, and a false edge is generated by an error signal generated at the boundary. Was displayed.
[0012]
As an example of a conventional video signal processing circuit, there is one described in Japanese Patent Application Laid-Open No. 10-834411.
[0013]
FIG. 7 is a block diagram showing an example of the configuration of a conventional video signal processing circuit. Reference numeral 60 denotes a luminance signal processing unit, and reference numeral 70 denotes an outline emphasis unit. The contour emphasizing unit 70 includes a contour extracting circuit 71, a coefficient multiplying circuit 72, an adding circuit 73, an enable signal generating circuit 74, and a switch circuit 75. The contour extraction circuit 71 is, for example, a secondary partial circuit as described above, and extracts a contour portion of a video signal. The contour signal (b) extracted by the contour extraction unit 71 is converted to an appropriate level by a coefficient multiplication circuit 72, and the addition circuit 73 adds the image signal and the video luminance signal processed by the luminance signal processing unit 60 to enhance the contour. . The enable signal generation circuit 74 generates an enable signal (A) from the video display area indicated by the horizontal display area signal and the vertical display area signal. The switch circuit 75 is controlled by the enable signal (a) so that the contour signal (b) is not added to the video luminance signal in areas other than the video display area.
[0014]
FIG. 8 is a block diagram showing a configuration of an example of a conventional vertical display area signal generation circuit. The input video signal is separated by a sync separation circuit 80 into a horizontal sync signal and a vertical sync signal. The vertical synchronizing signal activates a blanking period counter 81, and the blanking period counter 81 counts H pulses by the set count. When the counting by the blanking period counter 81 ends, the blanking period counter 81 activates the video display period counter 82. The video display period counter 82 counts H pulses by the set number similarly. If the period from the vertical synchronization signal to the start of the video display area is set in the blanking period counter 81 and the period of the video display area is set in the video display period counter 82, the video display period counter 82 performs counting. The period of time represents a vertical display area. The horizontal display area signal A can be generated in the same manner.
[0015]
An example of such a conventional display area signal generating circuit is described in, for example, JP-A-7-44125.
[0016]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 10-834411 [Patent Document 2]
JP-A-7-44125
[Problems to be solved by the invention]
In the video signal processing circuit of the conventional system as described above, a display area signal indicating a video display period is counted by a counter with reference to a vertical or horizontal synchronizing signal, and a signal indicating a certain period is counted by counting H pulses or dot clocks. Had been generated. For this reason, it is necessary to set in advance the data indicating the start position of the image area and the display period in the counter, but in the case of a letterbox image signal such as a cinema source, the image display position may differ depending on the source. Also, in a projection-type image display device, the image display position is often shifted vertically or horizontally and displayed, so that the data set in the counter matches the display position of the image actually displayed. There is a problem that it may not occur. The mismatch between the setting data and the image display position often occurs particularly in the vertical direction.
[0018]
The present invention is to automatically detect a boundary of a video display area and control a region where contour enhancement is performed when displaying a video signal having a different video display area or when moving and displaying a video display position. Accordingly, an object of the present invention is to provide a video signal processing circuit in which a false edge is not displayed at a boundary portion.
[0019]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a video signal processing circuit according to a first aspect of the present invention provides a video signal processing circuit for emphasizing an outline of an input video signal by discriminating a video display region and a blanking region. It does not operate at the boundary.
[0020]
As described above, according to the video signal processing circuit of the first invention, there is obtained an effect that a false edge does not occur at the boundary between the video display area and the blanking area due to contour enhancement.
[0021]
A video signal processing circuit according to a second aspect of the present invention comprises: a video edge extraction means for extracting a video component from an input video luminance signal and converting the video component to an appropriate level to generate a video edge enhancement signal; Adding means for adding the obtained video edge enhancement signal to the input video brightness signal, video display area detection means for determining a video display area and a blanking area of the input video brightness signal, and an input video brightness signal of the video edge enhancement signal Switching means for switching the addition to the image display area, and controlling the changeover switch means for the image display area detected by the image display area detecting means to add the image contour emphasis signal to the input image luminance signal. And
[0022]
As described above, according to the video signal processing circuit of the second invention, by detecting the video display area and controlling not to add the video contour signal in the blanking area, a false edge is detected at the boundary. Is obtained.
[0023]
A video signal processing circuit according to a third aspect of the present invention is the video signal processing circuit according to the second aspect, wherein the video area detecting means sets the brightness level of a pixel at least one line above the pixel of interest in advance. First luminance level determining means for comparing the luminance level of at least one line lower pixel with a preset threshold value; and the first and second luminance levels First and second counting means for counting the determination result of the determining means for a set period of one horizontal scanning period, minimum value detecting means for obtaining the minimum value of the first and second counting means, A count value judging means for comparing the result detected by the minimum value detecting means with a predetermined judgment value to generate a signal for controlling the changeover switch means; And it features.
[0024]
As described above, according to the video signal processing circuit of the third invention, the luminance levels of the pixels on the upper and lower lines of the pixel of interest are compared with the threshold value for a set period in one horizontal scanning period. By judging the boundary between the video display area and the blanking area based on the count result of the comparison result, it is possible to obtain an effect that the video display area can be automatically detected.
[0025]
A video signal processing circuit according to a fourth aspect of the present invention is the video signal processing circuit according to the second aspect, wherein the video area detection means sets a luminance level of a pixel at least one line above the target pixel in advance. First luminance level determining means for comparing the luminance level of a pixel at least one line lower with a preset threshold value; and the first and second luminance levels. AND means for calculating the logical product of the judgment results of the level judgment means, counting means for counting the output of the AND means for a set period of one horizontal scanning period, and comparing the output of the counting means with a predetermined judgment value set And a count value judging means for generating a signal for controlling the changeover switch means.
[0026]
As described above, according to the video signal processing circuit of the fourth invention, the luminance levels of the pixels on the upper and lower lines of the target pixel are compared with the threshold value for a set period in one horizontal scanning period, By judging the boundary between the video display area and the blanking area based on the count result of the AND output of the comparison result, it is possible to obtain an effect that the video display area can be automatically detected.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, various embodiments of the present invention will be described with reference to the drawings.
[0028]
(Embodiment 1)
FIG. 1 is a block diagram showing an example of a configuration of a video signal processing circuit according to the first embodiment of the present invention. FIG. 1 shows a vertical video edge enhancement processing circuit.
[0029]
In FIG. 1, reference numeral 100 denotes a vertical video contour extracting unit (corresponding to a means for enhancing the contour of an input video signal or a video contour extracting means in the claims), and 110 denotes a contour created by the vertical video contour extracting unit 100. An addition circuit for adding the emphasis signal to the original video luminance signal (corresponding to an adding means in the claims); 120, a vertical video display area detecting unit (corresponding to a video display area detecting means in the claims); 130 is a one-line delay circuit for adjusting the signal timing, and 140 is a switch circuit (corresponding to a switch means in the claims) for controlling the addition of the edge enhancement signal.
[0030]
The vertical direction video contour extraction unit 100 has a general second-order differentiating circuit configuration, and applies two 1-line delay circuits 101, 102 and 3H for vertically delaying a video luminance signal for 1H period to each data of the 3H period. Filter coefficient multiplying circuits 103, 104 and 105 for multiplying the filter coefficients, adder circuits 106 and 107 for adding the results, and a coefficient multiplying circuit 108 for adjusting the second derivative signal of the operation result to an appropriate level. It is configured. The vertical video contour extraction unit 100 obtains a contour emphasis signal (a) by performing a second derivative of the video luminance signal in the vertical direction and adjusting the level. The operation of the vertical video image contour extraction unit 100 composed of these components 101 to 108 is generally well known, and a detailed description thereof will be omitted.
[0031]
The vertical image display area detection unit 120 compares a luminance level of a pixel above the target pixel and a luminance level of a pixel below the target pixel with a set threshold value YH, and a second luminance level determination circuit 121. The level determination circuit 122, a first 1H counter circuit 123 that counts the determination result of the first luminance level determination circuit 121 for a set period, and similarly counts the determination result of the second luminance level determination circuit 122 for a set period. The second 1H counter circuit 124, the minimum value circuit 125 which takes the smaller value of the count result among the first 1H counter circuit 123 and the second 1H counter circuit 124, and the output value of the minimum value circuit 125 are set. And a count value determination circuit 126 that compares the count value with the determined determination value C.
[0032]
FIG. 2 is an explanatory diagram for explaining the operation of the vertical image display area detection unit 120. FIG. 2 shows a screen of 5 vertical lines and 10 horizontal pixels as a part of the display screen, where the upper two lines are a blanking area and the lower three lines are a video display area.
[0033]
FIG. 2A shows a case where the target pixel is located on the line V2 in the blanking area. In this case, it is assumed that the upper pixel of the target pixel is a pixel on the line V1 and the lower pixel is a pixel on the line V3. The threshold value YH is set to a level at which the luminance level of the pixels in the video display area and the luminance level of the pixels in the blanking area can be sufficiently determined. In this state, the output of the first luminance level determination circuit 121 is all "0" over the set period of the 1H period, and the output of the second luminance level determination circuit 122 is at the set period of the 1H period. All become "1". Therefore, the count value of the first 1H counter circuit 123 that counts the output of the first luminance level determination circuit 121 is “0”, and the second 1H counter that counts the output of the second luminance level determination circuit 122 The count value of the circuit 124 becomes “10”. Since the smaller one of the count values of the 1H counters 123 and 124 is “0”, the output of the minimum value determination circuit 125 becomes “0”.
[0034]
The count value judgment circuit 126 compares the output value of the minimum value judgment circuit 125 with the set judgment value C, and outputs an output signal according to the magnitude. In other words, the determination value C is a determination value for determining that the line is a “video display area” when the number of pixels whose luminance level is YH or more is C or more in the 1H period. Here, for example, if YH = 1 is set, the output of the count value determination circuit 126 in this case becomes “0”.
[0035]
Next, a case where the pixel of interest moves to the line V3 in the video area in FIG. In this case, since the upper pixel of the target pixel is still in the blanking area, the count value of the first 1H counter 123 is “0”, and as a result, the output of the count value determination circuit 126 remains “0”. It is.
[0036]
In FIG. 2C, when the target pixel shifts to the line V4, the upper pixel of the target pixel also shifts to the line V3 in the video display area, so that the count value of the first 1H counter 123 becomes “10”, and the count value determination is performed. Since the output of the circuit 126 becomes "1", the image display area can be determined from this.
[0037]
As described above, according to the vertical image display area detection unit 120 which is a component of the present invention, since the video signal area can be detected by the output of the count value determination circuit 126, the output of the count value determination circuit 126 becomes "1". "", The switch circuit 140 can be controlled to turn on the contour emphasis. In particular, in the vertical image display area detection unit 120, the output of the counter value determination circuit 126 becomes "0" even when the pixel of interest is at the outermost part of the image display area. As described above, the addition of the contour emphasizing signal at the boundary can be turned off without newly modifying the signal.
[0038]
Here, the 1H counters 123 and 124 are configured to count the outputs of the luminance level determination circuits 121 and 122 for the set period because, for example, an almost black area such as a caption inserted in a blanking area is used. Is set as a boundary to prevent erroneous detection as a boundary, and the set period is desirably 50% or more of the 1H period.
[0039]
In this embodiment, a case has been described in which the pixels for detecting the luminance level are pixels one line above and below the pixel of interest. However, the present invention is not limited to this. The effect can be obtained.
[0040]
As described above, according to the first embodiment, the result of comparing the luminance level of the pixel above the target pixel and the luminance level of the pixel below the target pixel with a preset threshold value is set in one horizontal scanning period. The image display area can be automatically detected by controlling the switch circuit for turning on / off the contour enhancement by comparing the minimum value of the count result with the set determination value and counting the number of periods that have been counted. In any position, there is an effect that no false edge is generated at the boundary.
[0041]
(Embodiment 2)
FIG. 3 is a block diagram showing an example of the configuration of a video signal processing circuit according to the second embodiment of the present invention. FIG. 3 shows a vertical video edge enhancement processing circuit. Note that the same components as those of the video signal processing circuit according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0042]
In FIG. 3, reference numeral 100 denotes a vertical video contour extracting unit; 110, an adding circuit for adding the contour emphasis signal created by the vertical video contour extracting unit 100 to the original video luminance signal; 150, a vertical video display area detecting unit , 130 is a one-line delay circuit for adjusting the timing of the signal, and 140 is a switch circuit for controlling the addition of the edge enhancement signal.
[0043]
The vertical image display area detection unit 150 compares a luminance level of a pixel above the target pixel and a luminance level of a pixel below the target pixel with a set threshold value YH, and a second luminance level determination circuit 151 and a second luminance level. A level judging circuit 152, an AND circuit 153 for calculating a logical product of output signals of the first luminance level judging circuit 151 and the second luminance level judging circuit 152, and a 1H counter circuit 154 for counting an output of the AND circuit 153 for a set period. And a count value determination circuit 155 for comparing the output value of the 1H counter circuit 154 with the set determination value C.
[0044]
FIG. 4 is an explanatory diagram for explaining the operation of the vertical image display area detection unit 150. FIG. 4 shows a screen of 5 vertical lines and 10 horizontal pixels as a part of the display screen, where the upper two lines are a blanking area and the lower three lines are a video display area.
[0045]
FIG. 4A shows a case where the target pixel is located on the line V2 in the blanking area. In this state, the output of the first luminance level determination circuit 151 is all "0" over the set period of the 1H period, and the output of the second luminance level determination circuit 152 is at the set period of the 1H period. All become "1". Therefore, the output of the AND circuit 153 becomes “0”, and the count value of the 1H counter circuit 154 that counts the output of the AND circuit 153 becomes “0”. Here, for example, if the determination value of the count value determination circuit 155 is set to YH = 1, the output of the count value determination circuit 155 in this case becomes “0”.
[0046]
Next, in FIG. 4B, consider the case where the target pixel has moved to the line V3 in the video area. In this case, since the upper pixel of the target pixel is still in the blanking area, the output of the AND circuit 153 is “0”, and the output of the count value determination circuit 155 remains “0”.
[0047]
In FIG. 4C, when the target pixel shifts to the line V4, the upper pixel of the target pixel also shifts to the line V3 in the video display area, so that the output of the first luminance level determination circuit 151 and the second luminance level determination circuit The outputs 152 all become "1" over a set period of the 1H period. Therefore, the output of the AND circuit 153 becomes “1”, and the count value of the 1H counter circuit 154 that counts the output of the AND circuit 153 becomes “10”. Here, since YH = 1, the output of the count value determination circuit 155 becomes “1”, and from this, the video display area can be determined.
[0048]
As described above, according to the vertical image display area detection unit 150 which is a component of the present invention, since the video signal area can be detected by the output of the count value determination circuit 155, the output of the count value determination circuit 155 becomes "1". "", The switch circuit 140 can be controlled to turn on the contour emphasis. In particular, in the vertical image display area detection unit 150, the output of the counter value determination circuit 155 becomes "0" even when the pixel of interest is located at the outermost part of the image display area, so that the addition of the edge emphasis signal is turned off. As described above, the addition of the contour emphasizing signal at the boundary can be turned off without newly modifying the signal.
[0049]
Here, the 1H counter 154 is configured to count the outputs of the luminance level determination circuits 151 and 152 for the set period in order to prevent erroneous detection as a boundary such as a caption inserted in a blanking area. Yes, the set period is desirably 50% or more of the 1H period.
[0050]
In the case of the present embodiment, the luminance level of the pixel above the pixel of interest and the luminance level of the pixel below the target pixel are determined by the first luminance level determination circuit 151 and the threshold value preset by the second luminance level determination circuit 152. The result of comparison with YH is ANDed by the AND circuit 153, and the result is counted by the 1H counter circuit 154. With this configuration, the circuit configuration is simpler than the configuration of the first embodiment. There is an advantage that can be made. On the other hand, when the luminance level of the upper pixel of the target pixel is equal to or lower than YH, the luminance level of the lower pixel is equal to or higher than YH, or vice versa, the state is established for all the pixels in the 1H period. Although the determination is erroneous, there is no practical problem since the video signal rarely satisfies such a condition.
[0051]
In this embodiment, a case has been described in which the pixels for detecting the luminance level are pixels one line above and below the pixel of interest. However, the present invention is not limited to this. The effect can be obtained.
[0052]
As described above, according to the second embodiment, an AND of the result of comparing the luminance level of the pixel above and the luminance level of the pixel below the target pixel with one set of one horizontal The video display area can be automatically detected by controlling a switch circuit that counts a preset period in the scanning period, compares the count result with a preset judgment value, and turns on / off the contour emphasis. Thus, an effect is obtained that no false edge is generated at the boundary portion regardless of the position of the video display area.
[0053]
In the first and second embodiments described above, the detection of the video display area is performed by paying attention to the vertical direction. However, if the configuration of this embodiment is applied, the detection of the video display area in the horizontal direction is performed. Clearly it is possible to do so.
[0054]
【The invention's effect】
As described above, according to the present invention, the result of comparing the luminance levels of the upper pixel and the lower pixel of the target pixel with the threshold value is counted for a period of 50% or more of the 1H period, and the count value and the determination value are compared. By detecting the video display area by comparing the video display area, the video display area can be automatically detected even if the start position and the period of the video display area are not known, and the area where the outline is emphasized is displayed in the video display area. Therefore, it is possible to prevent the display quality from being degraded due to the display of the false edge at the boundary of the video display area.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a video signal processing circuit according to a first embodiment of the present invention. FIG. 2 is a state diagram showing an operation of a vertical display area detecting unit by the circuit. FIG. 4 is a block diagram showing a configuration of a video signal processing circuit according to a second embodiment of the present invention. FIG. 4 is a state diagram showing an operation of a vertical display area detecting unit by the circuit. FIG. FIG. 6 is a block diagram showing a configuration of an image processing unit in the apparatus. FIG. 7 is a block diagram showing a configuration of an example of a conventional edge enhancement circuit. FIG. 8 is a conventional display. Block diagram showing a configuration of an example of a region detection circuit.
REFERENCE SIGNS LIST 100 vertical image contour extracting section 110 adding circuit 120 vertical image display area detecting section 121 first luminance level determining circuit 122 second luminance level determining circuit 123 first 1H counter circuit 124 second luminance level determining circuit 125 minimum Value circuit 126 count value determination circuit 130 one-line delay circuit 140 switch circuit

Claims (4)

A video signal processing circuit characterized in that means for emphasizing the contour of an input video signal is not operated at a boundary between the video display area and the blanking area by determining a video display area and a blanking area. A video contour extracting means for extracting a contour component from an input video luminance signal and converting the extracted contour component to an appropriate level to generate a video contour emphasis signal; , An image display area detecting means for determining an image display area and a blanking area of an input image luminance signal, and a changeover switch means for switching the addition of the image edge enhancement signal to the input image luminance signal. A video signal processing circuit for controlling the changeover switch means for the video display area detected by the video display area detection means to add the video edge enhancement signal to an input video luminance signal. A first brightness level for comparing a brightness level of a pixel on at least one line above a pixel to which a video edge enhancement signal is added (hereinafter referred to as a target pixel) with a preset threshold value; Judging means, second luminance level judging means for comparing the luminance level of at least one line lower pixel with a preset threshold value, and judging results of the first and second luminance level judging means by one horizontal First and second counting means for respectively counting for a set period in the scanning period, minimum value detecting means for obtaining the minimum value of the first and second counting means, and detection by the minimum value detecting means. 3. A count value judging means for comparing the result with a preset judgment value and generating a signal for controlling the changeover switch means. The video signal processing circuit. A first brightness level determining means for comparing the brightness level of a pixel at least one line above the target pixel with a preset threshold value; and a brightness of at least one line below the pixel of interest. A second brightness level determining means for comparing the level with a preset threshold value; an AND means for calculating a logical product of the determination results of the first and second brightness level determining means; It is composed of a counting means for counting for a set period in the horizontal scanning period, and a count value judging means for comparing the output of the counting means with a predetermined judgment value to generate a signal for controlling the changeover switch means. 3. The video signal processing circuit according to claim 2, wherein:

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