JP2004128535A - Network synchronizing clock supply apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain an accurate freerunning frequency by correcting an aging deviation of a freerunning center frequency of a voltage-controlled crystal oscillator. <P>SOLUTION: When the clock accuracy of a digital channel, to which a subordinate synchronization section 131 applies subordinate synchronization, satisfies specified accuracy, a correction section 133 receiving a correction instruction from a monitoring control section 108 performs a correction operation to use a subordinate synchronization control voltage obtained during the subordinate synchronization operation and given to a VC-OCXO 105 for a control voltage to determine the freerunning center frequency of the VC-OCXO 105 at freerunning by a freerunning setting section 132. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a communication device connected to a digital circuit network that is frequency-synchronized by a highly stable clock source. The communication device generates a high-precision clock synchronized with the connected digital line and, if necessary, free-runs. The present invention relates to a network synchronous clock supply device that generates a clock and supplies the clock to the device.
[0002]
[Prior art]
FIG. 3 is a block diagram showing a configuration example of a conventional network synchronous clock supply device. In FIG. 3, a line interface unit 301 extracts an 8 kHz clock from a data signal on a digital line and supplies the clock signal to a phase comparator 302.
[0003]
The network synchronous clock supply device includes a phase comparator 302, an oscillator control unit 303 receiving an output of the phase comparator 302, a D / A converter 304 receiving an output of the oscillator control unit 303, and an output of the D / A converter 304. It comprises a closed circuit of a voltage-controlled crystal oscillator (VC-OCXO) 305 to be received and a frequency divider 306 for providing an 8 kHz clock obtained by dividing the output of the VC-OCXO 305 to the phase comparator 302.
[0004]
The phase comparator 302 compares the 8 kHz clock input from the line interface unit 301 with the 8 kHz clock input from the frequency divider 306, and outputs phase difference information to the oscillator control unit 303.
[0005]
The oscillator control unit 303 includes a slave synchronization unit 331 and a free-running setting unit 332. The slave synchronization unit 331 sets the slave synchronization control to the D / A converter 304 based on the phase difference information from the phase comparator 302 in order to synchronize the output phase of the VC-OCXO 305 with the network clock extracted by the line interface unit 301. Find the value. The D / A converter 304 converts the set dependent synchronization control value into an analog voltage, and supplies a frequency control voltage to the VC-OCXO 305. The VC-OCXO 305 outputs a clock having a frequency according to the control voltage output from the D / A converter 304.
[0006]
The free-running setting unit 332 sets a value corresponding to a predetermined free-running center frequency to the D / A converter 304 in order to cause the VC-OCXO 305 to self-run when a failure occurs in a digital line or when measuring wireless characteristics. . The D / A converter 304 converts the set free-running frequency control value into an analog voltage, and provides the VC-OCXO 305 with the free-running frequency control voltage. The VC-OCXO 305 receives the free-running frequency control voltage output from the D / A converter 304 and outputs a high-precision free-running clock.
[0007]
The various clock generation unit 307 receives various clocks from the VC-OCXO 305, generates various clocks, and supplies them to the device.
[0008]
[Patent Document 1]
JP-A-11-32384
[Problems to be solved by the invention]
However, in the conventional network synchronous clock supply device, the self-running center frequency gradually fluctuates due to aging over a long period of time due to the characteristics of the VC-OCXO 305. However, there is a possibility that a frequency different from the initial frequency setting value is output. Therefore, conventionally, there has been a problem that the free-running frequency of the VC-OCXO 305 must be measured periodically and adjusted if necessary.
[0010]
The present invention has been made in view of such a point, and has a self-running accuracy correction function capable of correcting an aging deviation of a free-running center frequency of a voltage-controlled crystal oscillator and maintaining an accurate free-running frequency. An object of the present invention is to provide a network synchronous clock supply device.
[0011]
[Means for Solving the Problems]
A network synchronous clock supply device according to the present invention is a communication device connected to a digital line network frequency-synchronized by a highly stable clock source, wherein a high-precision clock synchronized with the connected digital line is output from a voltage controlled oscillator. A network synchronization clock supply device for outputting a free-running clock from the voltage-controlled oscillator as necessary and supplying the clock to the device, wherein the clock accuracy of a digital line performing slave synchronization is specified. When the accuracy is satisfied, the slave synchronous control voltage applied to the voltage-controlled oscillator obtained during the slave synchronous operation is corrected to a control voltage that determines a free-running center frequency of the voltage-controlled oscillator during the free-run. A configuration including a correction unit for performing an operation is adopted.
[0012]
According to this configuration, when the clock accuracy of the digital line performing the slave synchronization satisfies the specified accuracy, the correction means sets the slave synchronization control voltage given to the voltage controlled oscillator obtained during the slave synchronization operation. Since the control voltage determines the free-running center frequency of the voltage-controlled oscillator during free-running, the aging deviation of the free-running center frequency of the voltage-controlled crystal oscillator can be corrected, and the accurate free-running frequency can be maintained. . Therefore, a network synchronous clock supply device excellent in maintainability can be obtained.
[0013]
The network synchronization clock supply device of the present invention is the above-mentioned invention, wherein in the above invention, a monitoring control terminal for converting the correction operation content input by the operator into an electric signal, and a correction operation of the correction means in accordance with a control instruction from the monitoring control terminal And a monitoring control means for giving an instruction.
[0014]
According to this configuration, in the above invention, when the clock accuracy of the digital line performing the slave synchronization satisfies the specified accuracy, the accuracy of the free-running frequency can be obtained only by giving an instruction from the supervisory control terminal to the supervisory control means. Can be corrected, so that significant labor saving in maintenance work can be expected.
[0015]
The network synchronous clock supply device of the present invention according to the above invention, wherein the monitor control terminal is disposed on a digital circuit network to which the communication device is connected, and converts a correction operation content input by an operator into an electric signal; Monitoring control means for giving a correction operation instruction to the correction means in accordance with a control instruction sent from a control terminal via a digital line.
[0016]
According to this configuration, in the above invention, when it is clear that the clock quality of the digital network to be connected is ensured, the accuracy of the free-running frequency is controlled by a monitor and control terminal located at a remote place. Since the correction can be performed, the number of maintenance steps can be significantly reduced.
[0017]
The network synchronization clock supply device according to the present invention, in the above invention, statistically processes phase difference information between a clock of the digital line obtained during the slave synchronization operation and an output clock of the voltage controlled oscillator, and Monitoring control means for autonomously judging the accuracy of the correction and giving an instruction for a correction operation to the correction means.
[0018]
According to this configuration, in the above invention, the supervisory control means statistically processes the phase difference information between the clock of the digital line and the output clock of the voltage-controlled oscillator obtained during the subordinate synchronization operation, and Can be autonomously determined and a correction operation instruction can be given to the correction means, so that significant labor saving in maintenance work can be expected.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
The gist of the present invention is that when the clock accuracy of a phase-synchronized digital line satisfies a specified accuracy, the VC-OCXO control value during the subordinate synchronization operation is set as the free-running center frequency setting value, so that The purpose of the present invention is to correct the aging deviation of the free-running frequency of the OCXO and to greatly reduce the maintenance work for maintaining the accuracy of the free-running frequency.
[0020]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0021]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a network synchronous clock supply device according to Embodiment 1 of the present invention. In this embodiment, an example of application to a wireless base station of a WCDMA mobile communication system as a communication device connected to a digital circuit network frequency-synchronized by a highly stable clock source is shown.
[0022]
A WCDMA wireless base station is connected to a higher-level control device on a digital circuit network via a circuit interface unit 101. The digital network is synchronized with a highly stable clock source having an accuracy of the order of ^10.sup.-11 .
[0023]
The line interface unit 101 extracts an 8 kHz clock from the data signal on the digital line and supplies the clock to the phase comparator 102.
[0024]
The network synchronization clock supply device includes a phase comparator 102, an oscillator control unit 103 receiving an output of the phase comparator 102, a D / A converter 104 receiving an output of the oscillator control unit 103, and an output of the D / A converter 104. The circuit comprises a closed circuit including a voltage-controlled crystal oscillator (VC-OCXO) 105 that receives the signal and a frequency divider 106 that supplies an 8 kHz clock obtained by dividing the output of the VC-OCXO 105 to the phase comparator 102.
[0025]
The phase comparator 102 compares the 8 kHz clock input from the line interface unit 101 with the 8 kHz clock input from the frequency divider 106, and outputs phase difference information to the oscillator control unit 103.
[0026]
The oscillator control unit 103 includes a correction unit 133 in addition to the slave synchronization unit 131 and the free-running setting unit 132.
[0027]
The slave synchronization unit 131 sets the slave synchronization control in the D / A converter 104 based on the phase difference information from the phase comparator 102 in order to synchronize the output phase of the VC-OCXO 105 with the network clock extracted by the line interface unit 101. Find the value. The D / A converter 104 converts the set dependent synchronization control value into an analog voltage, and supplies a frequency control voltage to the VC-OCXO 105. The VC-OCXO 105 outputs a clock having a frequency corresponding to the control voltage output from the D / A converter 104.
[0028]
The free-running setting unit 132 sets a value corresponding to a predetermined free-running center frequency in the D / A converter 104 in order to cause the VC-OCXO 105 to self-run at the time of a digital line failure or measurement of wireless characteristics. I do. The D / A converter 104 converts the set free-running frequency control value into an analog voltage, and supplies the VC-OCXO 105 with the free-running frequency control voltage. The VC-OCXO 105 receives the free-running frequency control voltage output from the D / A converter 104 and outputs a high-precision free-running clock.
[0029]
Various clock generation units 107 receive a clock from the VC-OCXO 105, generate a chip rate clock for assembling a radio frame, and a radio reference clock that is a reference for a radio carrier, and supply them to the apparatus.
[0030]
Here, in WCDMA, it is recommended that the radio reference clock and the chip rate clock be generated from the same source. According to this recommendation, it is required that the VC-OCXO 105 can always generate a clock stably with an accuracy within ± 0.05 ppm.
[0031]
On the other hand, the VC-OCXO 105 is synchronized with the clock extracted from the digital line at the time of subordinate synchronization. Since the frequency accuracy of the digital network is about 10 ⁻¹¹ , the above accuracy can be satisfied. However, it is difficult to always maintain the self-running accuracy within ± 0.05 ppm over a long period of time when a self-propelled system is used at the time of a failure in a digital line or measurement of wireless characteristics.
[0032]
That is, due to the characteristics of the VC-OCXO 105, the free-running center frequency gradually fluctuates due to aging over a long period of time. The fluctuation rate is usually about ± 0.01 ppm / year. Therefore, when the slave synchronization is stopped and the self-running is performed by giving the self-running frequency control value set at the time of factory shipment or the like, the VC-OCXO 105 generates a clock having a frequency outside the set self-running frequency control value. May be done. Therefore, conventionally, it was necessary to periodically measure the free-running frequency and adjust the frequency.
[0033]
Therefore, in the present embodiment, a correction unit 133 is provided in the oscillator control unit 103. The correction unit 133 replaces the control value obtained when the clock accuracy of the digital line that is slave-synchronized by the slave synchronization unit 131 is sufficiently high with the self-running frequency control value set in the self-running setting unit 132. Do the settings.
[0034]
In addition, a monitoring control unit 108 is provided in the wireless base station as a mechanism for instructing the correction unit 133 when to perform the substitution operation. Further, a monitoring control terminal 109 for giving a control instruction to the monitoring control unit 108 is provided.
[0035]
The monitoring control terminal 109 converts the correction operation content input by the operator into an electric signal, and instructs the monitoring control unit 108. The monitoring control unit 108 gives a correction instruction to the correction unit 133 according to the instruction from the monitoring control terminal 109.
[0036]
As a result, the aging deviation of the VC-OCXO 105 is corrected, so that an accurate free-running frequency can be maintained, and significant labor saving in maintenance work can be expected.
[0037]
(Embodiment 2)
FIG. 2 is a block diagram showing a configuration of a network synchronous clock supply device according to Embodiment 2 of the present invention. In FIG. 2, the same reference numerals are given to the same or similar components as those described in the first embodiment (FIG. 1). Here, a description will be given focusing on a portion relating to the second embodiment.
[0038]
As shown in FIG. 2, in the second embodiment, the supervisory control terminal 201 is arranged on a digital network 202, and the supervisory control terminal 201 and the supervisory control 204 exchange control instructions via the digital line and the line interface unit 203. To do.
[0039]
According to this configuration, when it is clear that the clock quality of the digital circuit network is ensured, the self-propelled frequency can be corrected by control from a remote place, so that the number of maintenance steps is greatly reduced. be able to.
[0040]
Note that the present invention is not limited to the embodiments described above, and various other modifications are possible. For example, statistically processing the phase difference information between the clock of the digital line obtained at the time of the slave synchronization operation and the output clock of the VC-OCXO 105, that is, the output of the phase comparator 102, autonomously determines the accuracy of the digital line, The same effect can be obtained by providing the correction unit 133 with monitoring control means for giving an instruction for a correction operation.
[0041]
【The invention's effect】
As described above, according to the present invention, the function of correcting the aging deviation of the free-running frequency of the voltage-controlled crystal oscillator is provided, so that the maintenance work for maintaining the free-running frequency can be largely saved. Is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a network synchronous clock supply device according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a network synchronous clock supply device according to a second embodiment of the present invention. 3 is a block diagram showing a configuration example of a conventional network synchronous clock supply device.
101, 203 Line interface unit 102 Phase comparator 103 Oscillator control unit 104 D / A converter 105 Voltage controlled crystal oscillator (VC-OCXO)
106 frequency divider 107 various clock generation units 108, 204 monitoring control units 109, 201 monitoring control terminals 131 subordinate synchronization units 132 self-running setting units 133 correction units 202 digital network

Claims (4)

In a communication device connected to a digital circuit network that is frequency-synchronized by a highly stable clock source, a high-precision clock synchronized with the connected digital line is output from a voltage-controlled oscillator. A clock output from the voltage-controlled oscillator, and supplies the clock to the apparatus. When the clock accuracy of a digital line performing slave synchronization satisfies a specified accuracy, the slave synchronization operation is performed. Correction means for performing a correction operation to make the dependent synchronous control voltage given to the voltage-controlled oscillator obtained during the self-running to a control voltage that determines the free-running center frequency of the voltage-controlled oscillator. A network synchronous clock supply device, characterized in that: A monitoring control terminal that converts the correction operation content input by the operator into an electric signal, and a monitoring control unit that gives a correction operation instruction to the correction unit in accordance with a control instruction from the monitoring control terminal. 2. The network synchronization clock supply device according to claim 1, wherein: A monitoring control terminal that is arranged on a digital circuit network to which the communication device is connected and converts correction operation contents input by an operator into an electric signal; and a control instruction sent from the monitoring control terminal via a digital line. 2. A network synchronous clock supply device according to claim 1, further comprising: a monitoring control unit for giving a correction operation instruction to said correction unit. Statistical processing of phase difference information between the clock of the digital line obtained at the time of the slave synchronization operation and the output clock of the voltage-controlled oscillator, autonomously determines the accuracy of the digital line, and performs a correction operation on the correction means. 2. A network synchronous clock supply device according to claim 1, further comprising a monitoring control unit for giving an instruction of (1).

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