JP2004120254A - Image reader - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate troubles, e.g. deterioration of image quality or glitch of output clock, when an image reader is driven with a plurality of frequencies. <P>SOLUTION: Switching can be made between a low clock rate and a high clock rate by means of switches 114, 119, and the like. When a clock is switched, a CPU turns on a stop flag to stop IPCLK temporarily and turns off the stop flag after switching to resume clock supply. Shading correction, detection of a document and reading in color mode are performed at a low clock rate whereas reading in monochromatic mode is performed at a high clock rate. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image reading apparatus for reading, for example, a document, and more particularly to an image reading apparatus suitable for achieving both high productivity and high image quality.
[0002]
[Prior art]
2. Description of the Related Art In recent years, image reading apparatuses typified by digital copiers and image scanners for personal computers (PCs) have been widely and generally used. In particular, digital copiers have been attracting attention as image platforms that provide not only copying functions but also network functions and provide a wide range of applications as printers, facsimile machines, and image scanners.
[0003]
The digital copying machine is capable of simultaneously processing a composite operation such as transmitting a document read by a scanner during a printing operation to a PC or facsimile transmission. There is a great demand for digitizing documents, such as digitizing and distributing document images read in this way, and digitizing and storing paper documents, and higher productivity is also required for image reading devices. ing.
[0004]
The general configuration of an image reading device is to scan a document placed on a platen glass with a high-intensity light source, collect the reflected light, guide it to a focal plane, and use a CCD or the like installed on the focal plane. That is, a photoelectric conversion element converts the signal into an analog electric signal and digitizes the signal. A general method for increasing the productivity in such a configuration is to increase the scanning speed and the driving speed of the CCD.
[0005]
In order to improve the productivity of the image reading apparatus, for example, for a black-and-white document, the reading clock is increased to increase the scanning speed and the driving speed of the CCD, thereby improving the productivity. On the other hand, a method of giving priority to image quality with a normal clock is known.
[0006]
[Problems to be solved by the invention]
However, there is the following problem in a system for increasing the scanning speed and the driving speed of the CCD by switching the reading clock.
(1) In the case of high-speed driving, the temperature of the CCD and other high-speed devices is higher than in the case of low-speed driving. For this reason, it is necessary to prepare a cooling system having a capacity suitable for high-speed driving.
(2) The image quality of the image reading device is greatly influenced by the exposure amount per line cycle of the CCD. If high-speed driving is performed with the light amount at the time of low-speed driving, the signal SN is deteriorated due to insufficient light amount. Therefore, in addition to the deterioration of the image quality, erroneous detection may occur in dust detection, presence of a document, and detection of the size of the document, which are realized by determining the read image based on a predetermined reference. In order to maintain image quality and prevent erroneous detection, it is necessary to increase the light amount of a document illumination lamp as a light source.
(3) When switching between low-speed driving and high-speed driving by switching the clock frequency, it is necessary to improve the ability to follow the clock switching at the interface to the outside.
[0007]
The present invention has been made in view of the above conventional example, and provides an image reading apparatus capable of reducing standby power by waiting at a low-speed clock and suppressing a rise in device temperature while maintaining productivity. With the goal.
[0008]
It is another object of the present invention to provide an image reading apparatus in which erroneous determination caused by the signal SN is reduced by detecting the presence or absence of dust or a document or its size by a low-speed clock operation.
[0009]
It is another object of the present invention to provide an image reading apparatus in which clock switching is performed without stop control for an interface using a transmitter with a clock recovery function, thereby improving the ability to follow clock switching in the interface.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has the following configuration.
[0011]
An image reading device capable of reading a document image in synchronization with a plurality of clock frequencies,
Switching means for selectively switching the plurality of clock frequencies,
In the image reading standby state, the clock frequency is set to the lowest clock frequency, and at the start of reading, the document image is read by setting the clock frequency to any one of the plurality of clock frequencies. Reading control means for resetting the clock frequency.
[0012]
More preferably, the apparatus further comprises a stopping means for stopping a clock when the switching is performed by the switching means.
[0013]
Alternatively, an image reading apparatus capable of reading a document image in synchronization with a plurality of clock frequencies,
Switching means for selectively switching the plurality of clock frequencies,
A clock reproducing unit that reproduces a clock having a frequency that continuously follows the clock frequency switched by the switching unit and outputs the reproduced clock as a synchronization signal of the document image.
[0014]
More preferably, the reading control means sets the highest clock frequency to read a document image and output color image data in a monochrome mode for outputting monochrome image data when reading a document image. In the mode, the original image is read with the lowest clock frequency set.
[0015]
More preferably, the reading control means further performs shading correction, and sets the lowest clock frequency when performing shading correction.
[0016]
More preferably, the reading control means further performs document detection, and sets the lowest clock frequency when performing document detection.
[0017]
Alternatively, means for reading a document image at a plurality of clock speeds and selectively switching the plurality of clock speeds;
First determining means for determining the state of the image reading apparatus from the read image,
The first determination means makes a determination at the slowest clock speed among the plurality of clock speeds.
[0018]
More preferably, a second determination means for determining the state of the document from the read image is provided instead of the first determination means.
[0019]
Alternatively, an image processing apparatus comprising an output device capable of printing out, facsimile outputting or directly outputting an image signal of a document image read by any one of the above image reading devices.
Things.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
<First embodiment>
Hereinafter, a scanner unit in a digital copying machine will be described as a first embodiment of an image reading apparatus.
[0021]
[Configuration of Digital Copier]
FIG. 10 is a configuration diagram of a digital copying machine system including the image reading device 3000. The entire digital copying machine includes an image reading device 3000 and an image forming device 4000. The image forming apparatus 4000 incorporates a controller 5000 for performing system control and image processing, and an operation unit 6000.
[0022]
The image forming apparatus 4000 is equipped with a system power supply, and the image reading apparatus 3000 is supplied with DC power via a power cable 4001. The image forming apparatus 4000 includes a print engine of an electrophotographic system or the like, and forms a print image based on an image signal input from an external terminal or a video signal input from the image reading device 3000. In the present embodiment, the image forming apparatus 4000 is an apparatus capable of performing color printing.
[0023]
A control signal for controlling the image reading device 3000 and a video signal and a video clock output from the image reading device 3000 are connected to the controller 5000 via the signal cable 4002.
[0024]
The controller 5000 centrally manages the image reading device 3000, the image forming device 4000, and the operation unit 6000, and also controls network applications such as printing, facsimile, and scanning. Further, the controller 5000 is equipped with various image processing blocks such as color calibration of image data, image area separation, and color determination, and these image processing blocks are driven by a video clock supplied from the image reading device 3000.
[0025]
The image reading unit 3000 controls a scanner engine unit 3100 for optically reading a document image, a reading control unit 3103, and the entire reading unit 3000 including the reading control unit in response to an instruction from the controller 5000. A CPU 3101 and a memory 3102 including a ROM and a RAM are included. The memory 3102 stores programs executed by the CPU 3101, data, and the like. The scanner engine can switch the scanning speed in a plurality of ways. Further, either a color mode for outputting color image data or a monochrome mode for outputting monochrome image data can be selected. Therefore, for example, white light is used as the light source light, and in the color mode, a color filter of each color component is applied before the CCD sensor to output image data for each color component. Output image data.
[0026]
The operation unit 6000 is for inputting an instruction from a user.
[0027]
[Configuration of Scanner Engine]
FIG. 14 is a cross-sectional view of the scanner engine unit 3100 in FIG. 10, and shows a typical configuration of an image reading apparatus such as a digital copying machine.
[0028]
The scanner engine unit 3100 has a reduction optical system configuration, and the original reflected light illuminated by the original illumination lamp 3004 forms an image on the CCD 3011 via the first mirror 3005, the second mirror 3006, the third mirror 3007, and the optical lens 3010. Is done. The reading of the original image is performed by scanning the first mirror base 3008 and the second mirror base 3009 in the direction of arrow A or B at a speed of 2: 1 by the optical motor 3012. By switching the scanning drive speed to a plurality of stages, for example, two stages, it is possible to read a document at multiple speeds different from each other.
[0029]
A xenon tube of an external electrode type is used for the original illumination lamp 3004, and the original is illuminated by the reflected light from the reflectors 3013 and 3014.
[0030]
The document is placed on a document glass 3001 and pressed by a document pressure plate 3003. The document pressing plate 3003 also has a function as a cover for preventing the document glass 3001 from being stained or damaged.
[0031]
The reference white plate 3002 is used when obtaining a reference signal for performing shading correction. Materials that do not fluctuate in color due to environmental conditions such as temperature and humidity and durability are generally used.
[0032]
[Configuration of the reading control unit]
FIG. 1 is a block diagram of the reading control unit 3103 in the image reading device 3000.
[0033]
In FIG. 1, an original image converted into an electric signal by the CCD 3011 is converted into 10-bit digital video data by the AD converter 101. In the converted video data, digital video data in the effective pixel area of the CCD 3011 is written to the FIFO 102. At the same time, it is supplied to the linear interpolation circuit 103.
[0034]
The effective image area to be written to the FIFO 102 is determined by the CCDHENABLE signal generated by the CCD timing generation unit 107. In the present embodiment, 7020 pixels corresponding to 297 mm from the indexing position of the original glass 3001 are set. In general, since the index abutting position has a tolerance, the setting of the CCDHENABLE signal also has a function of adjusting the registration in the main scanning direction between the apparatuses.
[0035]
The CCD timing generation unit 107 is a block that generates various timing signals for driving the CCD 3011, the AD converter 101, and the FIFO 102 from clock sets (CLKHP, CLKHN, VCLK, and TGCLK) described later. Of the decoder.
[0036]
Reading from the FIFO 102 is determined by the IPHENABLE signal generated by the IP timing generation unit 108. In a default state, the sigA signal read from the FIFO 102 and supplied to the linear interpolation circuit 103 and the sigA signal input to the FIFO 102 and The sigB signal supplied to the other input of the signal 103 is set to have the same phase.
[0037]
Further, the write clock and the read clock are supplied to the FIFO 102 independently of each other, so that frequency conversion of video data can be performed.
[0038]
The IP timing generation unit 108 is a block that generates a control pulse after reading out the FIFO 102 using an IPCLK signal described later as a clock, and includes a counter and a decoder for setting each pulse phase.
[0039]
An IPTRIGGER pulse is supplied from the CCD timing generation unit 107 to the IP timing generation unit 108. The IP timing generation unit 108 resets an internal counter in synchronization with the IPTRIGGER pulse and generates various pulses. Therefore, adjustment of the phase relationship between the various pulses generated by the IP timing generation unit 108 and the video data can be performed only by setting the IPTRIGGER pulse.
[0040]
The linear interpolation circuit 103 performs weighted addition of the two input signals sigA and sigB at a set ratio, and operates so that the sum of the weights becomes 1. By default, sigA is set to output through.
[0041]
The shading circuit 104 performs a process of calibrating the sensitivity unevenness of the CCD 3011, the light distribution of the illumination lamp 3004, the deterioration of the light amount at the end of the lens 3010, and the like with the reference white plate 3002. The calibration processing of the shading circuit 104 is realized by performing a multiplication with a shading coefficient stored in a shading memory 152 connected to the shading circuit 104. The shading coefficient stored in the shading memory 152 is updated each time the document is read, and after the document reading is completed, the shading coefficient is held for a size detection operation described later.
[0042]
Image data VDO after shading correction <23. . 0> is supplied to the differential buffer group 150, and is supplied to the controller 5000 via the signal cable 4002 as 24 pairs of differential signals of (VDO23 +, VDO23−) to (VDO0 +, VDO0−).
[0043]
The dust detection circuit 105 is a circuit for detecting a reference white plate 3002, a reading position, or dust on a document. The dust detection circuit 105 operates as follows.
[0044]
FIG. 2 is a diagram illustrating an example of the reading surface of the reference white plate 3002. Lines indicated by dashed lines a, b, and c are parallel to the scanning lines at the time of document scanning, and are three areas on the reference white plate 3002 where shading correction data can be obtained. There is no dust on the broken lines a and b, and uniform density characteristics are achieved in the entire main scanning area. On the other hand, black dust 201 adheres to the broken line c during manufacturing.
[0045]
FIG. 3 is a diagram for explaining the dust detection algorithm. In one line section between the broken lines 304 and 305, a solid line 303 shows a waveform after shading correction of the line c in FIG. A pulse-like variation occurs in the signal level corresponding to the black dust 201. The alternate long and short dash lines 301 and 302 indicate upper and lower limit levels for the dust detection circuit 105 to judge dust.
[0046]
The dust detection circuit 105 has two upper and lower determination levels 301 and 302 (see FIG. 3) for the signal waveform 303 after shading correction, and determines a pixel exceeding one of the determination levels as dust. Works as follows. Since the signal waveform 303 in FIG. 3 is less than the lower limit 302 in the black dust 201 portion, the dust detection circuit 105 recognizes that there is dust.
[0047]
The size detection circuit 106 calculates an average value of a plurality of predetermined areas in the main scanning direction (line direction) with respect to the video data after the shading correction, and compares the average value with a determination level individually set. It is.
[0048]
The size detection operation is performed in conjunction with the opening and closing of the document pressure plate 3003, turns on the lamp 3004, and determines the presence and size of the document based on the change in the presence or absence of reflected light due to the opening and closing of the document pressure plate 3003.
[0049]
[Generation of clock signal]
Next, the clock configuration will be described.
[0050]
The reference clock of the system is the crystal oscillator 111, and the output signal REF1 is 25 MHz in this example. The REF1 clock is supplied to the PLL circuit 109 and the PLL circuit 110, and various clocks used by the CCD timing generation unit 107 are generated.
[0051]
The PLL circuit 109 outputs a clock set 1 including four types of clocks, CLKHP1 (100 MHz normal phase), CLKHN1 (100 MHz reverse phase), VCLK1 (25 MHz), and TGCLK1 (12.5 MHz). On the other hand, the PLL circuit 110 outputs a clock set 2 composed of CLKHP2 (200 MHz positive phase), CLKHN2 (200 MHz negative phase), VCLK2 (50 MHz), and TGCLK2 (25 MHz).
[0052]
The clock sets 1 and 2 are connected to two input terminals of the switch 114, and one of them is selected and output as a clock set. The switch 114 is controlled by the CPU 3101. For example, a port number that can be uniquely identified by the CPU 3101 is assigned to the switch 114. When the CPU 3101 outputs a value corresponding to the state 1 to the port corresponding to the switch 114, the switch 114 is switched to the PLL 109 side, and when a value corresponding to the state 2 is output, the switch 114 is switched to the PLL 110 side. The CPU 3101 can also read the state of the switch 114 by designating the port number. This configuration is not limited to the switch 114, and the same applies to the switches 117, 118, and 119.
[0053]
The switch 114 is connected to the PLL 109 in a default state (initial state), and the clock set 1 is selected.
[0054]
The clock sets 1 and 2 are composed of signals CLKHP, CLKHN, VCLK and TGCLK, respectively, and are supplied to the CCD timing generator 107. In the following, the clock sets 1 and 2 may be simply referred to as a clock set.
[0055]
In the clock set, the VCLK signal is also connected to one input terminal of the switch 119. The other input of the switch 119 is connected to an EXCLK signal used for synchronizing with an external device, and one is selected and output as an IPCLK signal. In the default state, the VCLK signal is selected.
[0056]
The IPCLK signal is supplied to the IP timing generation unit 108 via the synchronization stop circuit 112. The IPCLK signal is inverted by the inversion buffer 121 and supplied to the differential buffer 151 as a DCLK signal. The DCLK signal is converted into a differential signal (DCLK +, DCLK-) by the differential buffer 151 and supplied to the controller 5000. This is a synchronization signal for each pixel of the video signal.
[0057]
The EXCLK signal input to the switch 119 is generated based on the output REF2 signal of the crystal oscillator 116. The REF2 signal is supplied to one input terminal of the switch 118 via the SSCG 115 that performs frequency modulation with a clock of 40 MHz in this example, and is also frequency-divided by the frequency divider 117 by two. The output of the frequency divider 117 is supplied to the other input terminal of the switch 118, one of which is selected by the switch 118 and output as the EXCLK signal. In the default state, switch 118 selects the output of divider 117. Note that the EXCLK signal is set to have a lower frequency than the VCLK signal.
[0058]
The synchronization stop circuit 112 is a circuit for preventing the occurrence of glitches when stopping and resupplying the IPCLK signal. The synchronization stop circuit 112 inverts the output signal (input clock) of the switch 119 and latches the value of the stop flag. D-type flip-flop 112b (hereinafter, referred to as DFF), and an AND gate 112c having an input clock and an inverted output of DFF 112b as inputs.
[0059]
The synchronization stop circuit 112 is controlled by the CPU 3101. Specifically, the stop flag shown in FIG. 1 is connected to the port of the CPU 3101, and the CPU 3101 stops the output of the IPCLK signal by controlling the stop flag to a high level.
[0060]
FIG. 4 shows the operation timing of the synchronization stop circuit 112. In the figure, the stop flag is latched by the inverted clock output from the inversion buffer 112a and output from the DFF 112b.
[0061]
An input clock and a stop flag latched by the DFF 112b are input to two inputs of the AND gate 112c, and a clock for stopping the output of the DFF 112b in a low level section is output. That is, when the CPU 3101 sets the stop flag to the high level, the IPCLK signal stops in synchronization with the inverted clock (output of the inverted buffer 112a) while the stop flag is at the high level.
[0062]
Since the output / Q of the DFF 112b (the inverted code in the figure is represented by "/" in the present specification) has a transition point in the low level section of the clock, no glitch is generated at the output of the AND gate 112c. .
[0063]
[Initialization and preparation operation]
The operation of the image reading device 3000 in the above configuration will be described.
[0064]
First, the operation at the time of startup will be described. In FIG. 10, the image reading device 3000 starts when DC power supplied from the image forming device 4000 via the power cable 4001 is turned on. When the DC power is turned off, the power supplied to the image reading device 3000 is completely shut off. The control of turning off the DC power supplied from the outside is executed after the CPU 3101 has communicated with the controller 5000 in advance and it is acknowledged that the power is to be turned off.
[0065]
For example, when an abnormality occurs in the image reading apparatus 3000, the CPU 3101 notifies the controller 5000 of the abnormality of the image reading apparatus 3000, and the image forming apparatus 4000 controls the DC power supply to be turned off according to an instruction from the controller 5000.
[0066]
At the time of startup, the switches 114, 118 and 119 are in a default state. That is, when the supply of the DC power from the image forming apparatus 4000 is started, the CPU 3101 initializes the settings of the switches 114, 118, and 119 in the initialization processing. In the initial state, as described above, the switch 114 is set so that the low-speed clock set 1 is selected, the VCLK signal is set to 25 MHz, and the IPCLK signal is set to 25 MHz, which is equal to the VCLK signal. The switch 118 is set so that the output of the half frequency divider 117 is selected, and the switch 119 is set so that the VCLK signal is selected. That is, in this default setting, the clock set 1 is selected, and the VCLK1 signal is selected as the IPCLK signal.
[0067]
Next, after the position reference control of the optical motor 3012 is completed as a start-up process, under the control of the CPU 3101, a gain adjustment for correcting the output variation of the CCD line sensor 3012 is performed.
[0068]
The gain adjustment is performed in accordance with a plurality of image reading speeds of the image reading apparatus 3000. First, adjustment is performed on the low-speed clock set 1 in which the switches 114, 118, and 119 are in a default state.
[0069]
The gain adjustment is performed such that the reference white plate 3002 is read and the read level becomes a predetermined value.
[0070]
After completing the adjustment for the clock set 1, the CPU 3101 changes the setting so that the clock set 2 is selected by the switch 114, and performs the gain adjustment in the same manner as for the clock set 1. The gain adjustment result in each clock set is stored in the RAM 3102 in association with each clock set. The gain adjustment result may be stored in association with the state of the switch 119.
[0071]
After the gain adjustment by the clock set 2 is completed, the switch 114 is switched to the default state, and the startup processing is continued. After the start-up is completed, the switch 114 is in the state where the clock set 1 is selected, and the image reading device 3000 enters a standby state with the low-speed clock. Further, the switch 119 is changed to a setting for selecting EXCLK, and the frequency modulated clock of 20 MHz divided by the frequency divider 117 is set in the IPCLK signal.
[0072]
FIG. 5 shows the state of the output waveform of the CCD timing generator 107 after activation.
[0073]
Since the paper conveyance (movement of the mirror base 3008) speed is 100 mm / s and the resolution is 600 DPI (dot / inch), the line cycle is 1 / (100 / 25.4 * 600) = 423.3 μs.
[0074]
The driving waveform of the CCD 3011 includes a TG pulse (TGCLK) for transferring charges from the photodiode and two-phase transfer clocks φ1 and φ2. These signals are input from the CCD timing generation unit 107 to the CCD 3011 and the AD converter 101. The CCD 3011 has 7500 effective pixels, and is configured to be output in an even-numbered pixel column and an odd-numbered pixel column. The transfer frequency is equal to TGCLK and is 12.5 MHz, so the number of transfer pixels per line is 423.3 us / (1/125 MHz) = 5291 pixels.
[0075]
Since the number of effective pixels is 7500/2 = 3750 pixels, 5291-3750 = 1541 pixels are the number of pixels that can be allocated to the TG pulse and the idle transfer unit. The empty transfer unit is for filling a video signal with an empty signal in which an actually read image signal is absent.
[0076]
The CCDHENABLE signal is set to a low level in an effective pixel section of the CCD 3011, and the IPHENABLE signal is set with a phase delayed by 4 pixels.
[0077]
After the gain adjustment, the dust detection operation is performed with the clock set 1 selected. As described above, since the dust detection operation is performed by comparing the image data with the determination level, the determination result may be affected by the SN (signal-to-noise ratio) of the image data. When the clock set 1 is selected, the CCD line sensor 3011 is driven at a low speed, so that a sufficient SN is secured, and erroneous determination in dust detection is prevented.
[0078]
The above processing is performed at the time of startup, and the apparatus enters a reading standby state with the clock set 1 selected. The reading standby state is continued until there is a reading instruction from the controller 5000.
[0079]
According to the above procedure, the clock set 1 having a low clock frequency is selected in the standby state among the plurality of clock speeds, so that the power consumption in the standby state can be suppressed and unnecessary heat generation can be prevented. Further, erroneous detection of dust can be prevented by detecting dust using the clock set 1 having a low clock frequency.
[0080]
[Image scanning operation]
Next, an image reading operation will be described.
[0081]
The image reading process is started when the controller 5000 interprets a user command input from the operation unit 6000 and a reading instruction from the controller 5000 is transmitted to the image reading device 3000 via the signal cable 4002.
[0082]
In the present embodiment, when the reading mode is the color or color / monochrome automatic selection, the operation is performed such that the same-size reading is performed by the clock set 1 and in the case of the monochrome mode, the same-size reading is performed by the clock set 2.
[0083]
FIG. 6 shows a flowchart of image reading. This flowchart shows an operation procedure of the image reading device 3000 under the control of the CPU 3101.
[0084]
S1 indicates a standby state of the image reading device 3000. When the document pressure plate 3003 is opened and closed in the S1 state, a document size detection process using the size detection circuit 106 is performed in conjunction with the opening and closing operation. For example, when the document pressure plate 3003 is closed from an open state, a document size detection process is performed. In the document size detection process, the presence or absence of a document is also detected. The document size detection process is a process including an average value calculation of the image data, and the determination result may be affected by the SN of the image data.
[0085]
In the present embodiment, the state of S1 is a state in which the clock set 1 is selected, and the document size detection processing is performed in a state where the CCD line sensor 3011 is driven by the low-speed clock. Therefore, a sufficient SN is secured for the image data, and no erroneous determination due to the SN occurs.
[0086]
S2 is a step in which a reading instruction is issued from the controller 5000. If the process proceeds to this step with the document pressure plate 3003 open, document size detection is performed in this step S2. Since the size detection process performed from the S2 state is also performed with the clock set 1 selected, no erroneous determination due to SN occurs.
[0087]
In S3, the mirror base or the like is moved to the shading position (the reading position of the reference white plate 3002).
[0088]
Next, in S4, the reading mode is confirmed, and in the case of the monochrome mode, the process proceeds to S7. In the case of the color mode and the automatic determination mode, the process proceeds to S5. The reading mode is notified together with a reading instruction from the controller 5000, and is held in, for example, the memory 3102 or the like.
[0089]
In S5, the shading correction is performed while the clock set 1 is selected, and the image is read in S6. In this case, the image is read at the timing shown in FIG.
[0090]
After the reading is completed, reshading is performed in S11, and the reading is completed. However, in the case of the color mode, since shading is performed at a low speed in S5, reshading can be omitted.
[0091]
On the other hand, if the monochrome mode is determined in S4, switching to the high-speed clock is performed in S7. Switching to the high-speed clock is performed by switching the switch 114 to the selection of the clock set 2 and the switch 118 to the selection side of the SSCG 115 output.
[0092]
When switching to the high-speed clock, the CPU 3101 controls the stop flag to a high level in order to prevent a malfunction of the image processing block of the controller 5000 due to the glitch. Thus, the clock (IPCLK) is temporarily stopped by the synchronization stop circuit 112. After switching the switches 114 and 118 to select the high-speed clock, the stop flag is controlled to low level to restart the supply of the IPCLK.
[0093]
FIG. 7 shows an output waveform of the CCD timing generation unit 107 at the time of monochrome reading. Since the clock set supplied to the CCD timing generation unit 107 has a frequency twice that at the time of color reading, the line cycle is also halved to 211.6 us. The clock signals TGCLK, φ1, φ2, CCDHENABLE, IPTRGGER, and IPHENABLE output from the CCD timing generation unit 107 have twice the frequency during low-speed driving.
[0094]
After switching to the high-speed clock, shading correction during high-speed driving is performed in S8, and then image reading by high-speed driving is performed in S9.
[0095]
After the image reading is completed, switching to the low-speed clock is performed in S10. Switching of the low-speed clock is performed by switching the switch 114 to the clock set 1 side and switching the switch 118 to the frequency divider 117 output side. Also at the time of switching to the low-speed clock, the CPU 3101 turns on the stop flag, the clock is temporarily stopped by the synchronization stop circuit 112, and control is performed again after the clock is switched, and the image processing block of the controller 5000 malfunctions. Is prevented.
[0096]
After switching to the low-speed clock, shading correction is performed again in S11, a shading coefficient for size detection performed in the standby state is created, and reading is completed in S12.
[0097]
[Standby mode]
Next, control during standby will be described.
[0098]
The image reading device 3000 has a standby mode for reducing power consumption. In the standby mode, the CPU 3101 sets the stop flag for the synchronization stop circuit 112 to a high level.
[0099]
The synchronization stop circuit 112 stops the IPCLK signal without generating a glitch, and the power consumption of the logic circuit after reading the FIFO 102 driven by the IPCLK signal is reduced.
[0100]
Generally, when a glitch occurs in a clock signal, particularly in a system using a memory, a read / write error occurs, and in the worst case, the held data is destroyed. Since the IPCLK signal is also supplied to the shading memory 152 as a synchronization signal, the occurrence of glitches is suppressed by stopping the IPCLK by using the synchronization stop circuit 112, and the shading coefficient data held in the shading memory 152 has the same content. Is guaranteed, and the size detection operation after the release of the standby mode can be performed normally.
[0101]
The image reading device 3000 realizes image reading at a plurality of clock speeds with the above operation, suppresses power consumption in a standby state, and improves dust detection and size detection accuracy.
[0102]
<Second embodiment>
Next, a second embodiment will be described. FIG. 12 is a circuit block diagram showing a second embodiment of the present invention, in which the transmitter 120 having a clock recovery function is used for the interface with the controller 5000 in the circuit block described in FIG. 1 of the first embodiment. The other circuit configuration is the same as that of FIG. Therefore, description of the configuration and operation common to the first embodiment is omitted in this embodiment.
[0103]
FIG. 9 is an internal block diagram of the transmitter 120. In FIG. 9, a PLL circuit 901 detects a phase difference between an input DCLK signal and an INTCLK signal, and outputs a DC voltage according to the phase difference.
[0104]
An oscillator (VCO) 902 is a voltage-controlled oscillator controlled by a DC voltage output from the PLL circuit 901 and has an oscillation range of 140 to 420 MHz.
[0105]
The SCLK signal is supplied to a parallel-serial converter (parallel-serial converter) 904 and a frequency divider 903 with a clock output from an oscillator 902.
[0106]
A frequency divider 903 is a frequency divider that divides the SCLK signal by １ ／, and the divided clock is output as an INTCLK signal.
[0107]
The parallel-serial converter 904 converts the input 28-bit data VIN <27: 0> into four sets of high-speed differential signals (TX1 +, TX1-), (TX2 +, TX2-), (TX3 +, TX3-), (TX4 +, This is a parallel-to-serial converter for converting to TX4-), and is synchronously controlled by the SCLK signal.
[0108]
VDO <23: 0> output from the shading circuit 104 is assigned to the lower 24 bits of the data VIN <27: 0>. Although not shown, a synchronization signal is assigned to the upper 4 bits.
[0109]
INTCLK is input to the differential buffer 905, and (TXCLK +, TXCLK-) is output.
[0110]
The EN signal is a signal for performing the enable control of the transmitter 120, and is input to the transmitter 902, the parallel-serial converter 904, and the differential buffer 905. The oscillator 902 stops oscillating, and the parallel-serial converter 904 and the differential buffer 905 operate to fix the output. The EN signal is supplied from the CPU 3101.
[0111]
In the above configuration, since the PLL circuit 901 controls the oscillator 902 so that the phase difference between DCLK and INTCLK is eliminated, the frequency of SCLK is the reciprocal multiple of 1/7 of the frequency division ratio of the frequency divider 903 with respect to INTCLK. That is, the frequency becomes seven times.
[0112]
The parallel-serial converter 904 performs a parallel-serial conversion of the input signal in synchronization with a clock SCLK having a frequency seven times INTCLK. Since there are four serial signals to be output, a 28-bit signal can be converted into four serial signals by a clock having a frequency seven times that of the clock.
[0113]
In this embodiment, when the frequency of DCLK is 25 MHz, the frequency of INTCLK is 25 MHz and the frequency of SCLK is 175 MHz. When the frequency of DCLK is 40 MHz, the frequency of INTCLK is 40 MHz and the frequency of SCLK is 280 MHz.
[0114]
The function of replacing the input DCLK with the INTCLK generated by the internal oscillator and outputting it is the clock recovery function of the transmitter 120.
[0115]
FIG. 11 is a diagram showing the timing of the high-speed differential signal output from the transmitter 120. FIG. 11 shows the timing after the synthesis of each differential signal, and the TXCLK signal shows a synthesized signal of TXCLK + and TXCLK-. The same applies to other signals. The TXCLK signals (TXCLK +, TXCLK−) are clocks reproduced by the transmitter 120. 7-bit data is distributed to each of the signals TX1 to TX4 during one cycle of the TXCLK signal, and the relationship with the input data is as shown in the figure.
[0116]
FIG. 13 shows the following operation of the signals DCLK, SCLK, and INTCLK.
[0117]
In FIG. 13, when the power is turned on, DCLK is stopped, a default voltage Va is output from the PLL circuit 901, and the oscillator 902 outputs a 420 MHz clock as SCLK for the voltage Va. In this case, INTCLK is frequency-divided by ７ in the frequency divider 903 to be 60 MHz.
[0118]
Next, DCLK is input at timing A, and the following operation is started. At timing B, the following operation is completed. At timing B, the frequency of INTCLK is 25 MHz, which is equal to DCLK, and the frequency of SCLK is 175 MHz, which is seven times INTCLK. The period from timings A to B is a follow-up period, and usually requires a time of about 10 to 50 ms.
[0119]
An image reading operation in the above configuration will be described.
[0120]
Image reading is performed according to an instruction from the controller 5000 as in the first embodiment. The reading flow is also the same as in the first embodiment.
[0121]
The feature of the present embodiment lies in the operation at the time of clock switching, and will be described in detail below.
[0122]
As in the first embodiment, the CPU 3101 performs switching from the low-speed clock to the high-speed clock in S7 in FIG. 6 and switching from the high-speed clock to the low-speed clock in S10 as in the first embodiment.
[0123]
In S7, an operation of switching the switch 114 to the clock set 2 selection side and the switch 118 to the SSCG 115 output selection side is performed. However, the stop flag remains at the low level, and the IPCLK stop control by the synchronization stop circuit 112 is not performed.
[0124]
FIG. 8 shows the clock tracking operation of the transmitter 120. Since stop control of IPCLK is not performed by the stop flag, a glitch occurs in DCLK at the clock switching point.
[0125]
However, the transmitter 120 has a clock recovery function as described above, and is not DCLK itself. The transmitter 120 generates a signal TXCLK that is generated in synchronization with DCLK, and that has a frequency that continuously changes and follows the change even if the frequency of DCLK changes discontinuously. Since the following time constant is several tens of ms, glitches generated by the switching operation are not transmitted to the output clock. Therefore, no malfunction of the image processing block of the controller 5000 occurs. Further, the clock follow-up period for the stop period control can be shortened.
[0126]
On the other hand, in the image reading apparatus 3000, data stored in the shading memory 152 may be destroyed by glitches generated on IPCLK. However, in S8 of FIG. 6, since the reshading operation is performed after the switching to the high-speed clock, the shading data is regenerated and has no effect on the read data.
[0127]
In S10 of FIG. 6, switching from the high-speed clock to the low-speed clock is performed. In this case, the switch 114 is set to the clock set 1 selection side and the switch 118 is set to the frequency divider 117 output side while the stop flag remains at low level. Can be switched to In this case as well, a glitch occurs in IPCLK, but no glitch is transmitted to the output clock of the transmitter 120 as described in S7, so that a malfunction does not occur in the image processing block of the controller 5000. Also in this case, there is no problem since the data in the shading memory 152 is regenerated in S11.
[0128]
As described above, glitches occurring in the output clock when the operation clock of the image reading apparatus is switched are prevented. Also, even if glitches occur in the internal clock, measures are taken against the effects and glitches can be prevented. Further, by not performing the stop operation, the period for following the high-speed clock to the low-speed clock can be shortened.
[0129]
In the present embodiment, the synchronization stop circuit 112 is not required for switching the clock, and the output signal of the switch 117 can be used as it is as the IPCLK. However, to stop the clock during standby, the synchronization stop circuit 112 is required.
[0130]
【The invention's effect】
As described above, the present invention has the following effects.
[0131]
Standby with a low-speed clock can reduce standby power and suppress a rise in device temperature.
[0132]
Further, by switching the clock frequency of the interface using the transmitter having the clock recovery function without controlling the clock stop, it is possible to improve the ability to follow the clock switching in the interface.
[0133]
Further, erroneous determinations caused by the signal SN can be reduced by performing the detection operation with a low-speed clock operation.
[Brief description of the drawings]
FIG. 1 is an image processing block diagram according to a first embodiment.
FIG. 2 is a diagram illustrating dust attached to a reference white plate 3002;
FIG. 3 is a diagram illustrating a dust detection algorithm.
FIG. 4 is an explanatory diagram of an operation of a synchronization stop circuit 112
FIG. 5 is an explanatory diagram of an output waveform of the CCD timing generation unit 107 at the time of startup and color reading.
FIG. 6 is an image reading flowchart.
FIG. 7 is an explanatory diagram of an output waveform of the CCD timing generation unit 107 when reading black and white.
FIG. 8 is an explanatory diagram of input / output clock waveforms of the transmitter 120 at the time of clock switching.
FIG. 9 is a detailed view of a transmitter 120.
FIG. 10 is a system configuration diagram including an image reading device 3000;
FIG. 11 is an output timing chart of the transmitter 120.
FIG. 12 is an image processing block diagram according to a second embodiment;
FIG. 13 is a diagram showing a clock tracking operation of the transmitter 120.
FIG. 14 is a configuration diagram of an image reading device 3000;
[Explanation of symbols]
101: AD converter, 102: FIFO, 103: Linear interpolation circuit, 104: Shading correction circuit, 105: Dust detection circuit, 106: Size detection circuit, 107: CCD timing generation unit, 108: IP timing generation unit, 109, 110: PLL circuit, 111, 116: crystal oscillator, 112: synchronization stop circuit, 112a: inversion buffer, 112b ... D-type flip-flop, 112c AND gate, 114, 118, 119 switch, 115 SSCG 117 divider, 120 transmitter, 121 inverting buffer 150 ... differential buffer group, 151 ... differential buffer,
901, PLL circuit, 902, oscillator, 903, frequency divider, 904, parallel-serial converter, 905, differential buffer
3000 image reading device 3001 original glass 3002 reference white plate 3003 original pressure plate 3004 illumination lamp 3005 first mirror 3006 second Mirror, 3007: third mirror, 3008: first mirror base, 3009: second mirror base, 3010: optical lens, 3011: CCD, 3012: optical motor, 3013, 3014 ・ ・ ・ Reflection shade
4000 image forming apparatus, 4001 power cable, 4002 signal cable
5000 ... controller
6000 ・ ・ ・ Operation unit

Claims (9)

An image reading device capable of reading a document image in synchronization with a plurality of clock frequencies,
Switching means for selectively switching the plurality of clock frequencies,
In the image reading standby state, the clock frequency is set to the lowest clock frequency, and at the time of starting reading, the document image is read by setting the clock frequency to any one of the plurality of clock frequencies, and after the reading is completed, the lowest clock frequency is set. An image reading device comprising: a reading control unit that resets a clock frequency. The image reading apparatus according to claim 1, further comprising a stop unit that stops a clock when switching is performed by the switching unit. An image reading device capable of reading a document image in synchronization with a plurality of clock frequencies,
Switching means for selectively switching the plurality of clock frequencies,
Image reading means for reproducing a clock having a frequency that continuously follows the clock frequency switched by the switching means, and outputting the reproduced clock as a synchronization signal for the original image; apparatus. The reading control means may set the highest clock frequency to read the document image and output the color image data if the monochrome mode is to output monochrome image data when reading the document image. The image reading apparatus according to claim 1, wherein an original image is read by setting the lowest clock frequency. 4. The image reading apparatus according to claim 1, wherein the reading control unit further performs shading correction, and sets the lowest clock frequency when performing the shading correction. 5. The image reading apparatus according to claim 1, wherein the reading control unit further performs document detection, and sets the lowest clock frequency when performing document detection. Means for reading a document image at a plurality of clock speeds and selectively switching the plurality of clock speeds;
First determining means for determining the state of the image reading apparatus from the read image,
The image reading apparatus according to claim 1, wherein the first determination unit performs the determination at a lowest clock speed among the plurality of clock speeds. The image reading apparatus according to claim 7, further comprising a second determination unit configured to determine a state of the document from the read image, instead of the first determination unit. An image processing apparatus, comprising: an output device capable of printing, facsimile, or outputting an image signal of a document image read by the image reading apparatus according to claim 1.

Images