JP2004120102A - Offset adjusting method for differential circuit and differential circuit with offset adjusting function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make exactly compensable the offset voltage of an operational amplifier, a comparator, etc. over a long time, without passing through other analog blocks. <P>SOLUTION: A switched capacitor SC411 is connected to a connection point (drain) of a transistor N411 and a transistor P411 at the input of a current mirror which form a differential pair in a differential amplifier circuit. Its switching frequency is suitably changed to change the resistance value of an equivalent resistance. This slightly changes the charge drawing quantity to reduce the voltage offset of the differential amplifier circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a differential circuit offset adjustment method and a differential circuit having an offset adjustment function.
[0002]
[Prior art]
In a circuit that outputs sound, it is important to prevent pop noise (sudden noise: sometimes described as “pop sound” in the following description) in order to ensure sound quality. is there.
[0003]
Various countermeasures have been taken for generation of pop noise due to power on / off, but there are various causes for generation of pop noise during audio output, and the countermeasure may be postponed. is there.
[0004]
The present invention mainly deals with pop noise caused by offset in a differentially configured circuit (differential amplifier or the like).
[0005]
As a technique for canceling the offset of the differential amplifier (op-amp), a technique employing a configuration for injecting a complementary current (see Patent Document 1 below) and a technique using a switched capacitor (see Patent Document 2 below) are known. is there.
[0006]
[Patent Document 1]
JP-A-9-130172 (FIG. 5 and the like)
[Patent Document 2]
JP-A-6-102294 (FIG. 1 etc.)
[0007]
[Problems to be solved by the invention]
In a circuit of an audio output system, for example, when a small voltage offset is present in a differential amplifier, if the volume is rapidly increased using a volume (that is, the gain of the circuit is increased), the volume is changed before the volume is changed. An unproblematic offset voltage is greatly amplified, the output level of the differential amplifier changes, ringing or the like may occur, and unpleasant pop noise may occur.
[0008]
For example, as shown in FIGS. 15A and 15B, a variable gain amplifier 700 (input resistor R211, feedback resistors R212 to R216, gain adjustment circuit GC) in the volume circuit after D / A conversion of the audio output system circuit. ) Is assumed, when there is no sound, the gain is suddenly increased for volume adjustment.
[0009]
That is, in FIG. 15A, in the gain adjustment circuit GC, only the switch S214 is closed (minimum gain), and from this state, as shown in FIG. 15B, all switches are opened (maximum). Gain).
[0010]
In this case, if there is no offset in the differential amplifier circuit 700, no step wave is generated at time T100 as shown in FIG. (See part X in FIG. 15 (c)).
[0011]
In contrast, when an offset exists in the differential amplifier circuit 700, the offset voltage of the differential amplifier circuit 700 is greatly amplified as shown in FIG. , A step wave (denoted as EV in the figure) corresponding to the product of the above is generated. Then, an unnecessary sound (pop noise) called “bottom” is generated by the ringing generated by the step wave.
[0012]
When talking normally, the power of this sound is considerably smaller than the power of the talking voice, so this is not a problem, but when there is no sound, this unnecessary sound becomes prominent.
[0013]
Therefore, in order to eliminate the unnecessary sound, it is necessary to surely cancel the offset generated in the volume circuit.
[0014]
Until now, there has been no effective countermeasure against the pop noise, that is, an effective countermeasure for surely canceling the offset of the volume circuit for a long time.
[0015]
Also, the CDMA transmitter D / A converts each of the QPSK-modulated I (positive phase) and Q (quadrature) signals, and sends out the signals to the antenna. It is ideal that the input value and the output voltage of the D / A converter match, but actually, input / output offset occurs due to various factors.
[0016]
If the D / A converters corresponding to the I signal and the Q signal have different offset amounts (that is, the input characteristics of the two D / A converters are different), each of the I and Q signals Are shifted in phase, resulting in a transmission error. Therefore, it is necessary to cancel the input / output offset of the D / A converter and make the characteristics of the D / A converter uniform.
[0017]
In the technique described in Patent Document 1 described above, an offset of the differential amplifier is canceled by injecting a complementary current. However, a countermeasure that can be taken by such a method is a considerably large offset. It is not suitable as a countermeasure for a minute offset of about several tens mV.
[0018]
Further, the technique described in Patent Document 2 is common to the present invention in that a switched capacitor is used. However, in the technique described in Patent Document 2, the switching frequency of the switched capacitor is constant, and the integration circuit And the voltage is adjusted by controlling the sample and hold, the configuration is complicated, and the technical idea of the present invention is fundamentally different.
[0019]
An object of the present invention is to appropriately adjust a very small offset of a circuit having a differential configuration with a simple configuration.
[0020]
[Means for Solving the Problems]
According to the present invention, a switched capacitor functioning as a variable resistor for trimming is connected to at least one of the left and right current paths of a circuit having a differential configuration, and the offset is adjusted by digital resistor trimming.
[0021]
In other words, in the present invention, the equivalent resistance value is minutely changed by changing the switching frequency of the switched capacitor, and the offset voltage is adjusted by finely adjusting the amount of charge withdrawn at a level where the small signal equivalent circuit of the transistor does not change. Shrink.
[0022]
Since the amount of charge extraction is finely adjusted by resistance trimming, adjustment to the opposite polarity cannot be performed. However, by intentionally giving an offset to the differential circuit from the beginning, the offset adjustment can be performed for any of the polarities (+,-) in accordance with the amount of charge to be extracted.
[0023]
According to the present invention, for example, digital trimming can be appropriately performed by using a high-speed clock available in an LSI.
[0024]
In one aspect of the differential circuit of the present invention, switching control is performed by dividing the switching frequency into several stages.
[0025]
Such a configuration can be easily realized by, for example, dividing a high-speed clock into several stages and dividing the high-speed clock, or individually generating clocks having different division ratios using the principle of a frequency synthesizer.
[0026]
In another aspect of the differential circuit of the present invention, switching is performed by driving a switched capacitor in a band sufficiently higher than a clock frequency required for normal signal processing (for example, processing of an audio signal). The accompanying weak noise can be made inaudible to human ears, or can be easily removed in distinction from a regular signal.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
As described above, in order to reduce the pop noise, that is, the offset of the operational amplifier circuit in the volume circuit, this offset amount is accurately measured without passing through another analog circuit, and the compensation corresponding to this amount is calculated by this operation. It must be applied to the amplifier circuit for a long time.
[0028]
The operational amplifier circuit is mainly configured with a differential amplifier. Although the differential amplifier is designed so that the current capabilities of the left and right are balanced, an offset is usually caused due to variations in the size of the transistors that actually constitute the differential amplifier.
[0029]
According to the study of the present inventors, it has been confirmed that the offset amount of the operational amplifier circuit varies considerably, sometimes deviates significantly from the allowable range of the specification, and the offset of about 10 mV remains in some cases.
[0030]
In order to eliminate such a problem, it is necessary to accurately measure the offset of the operational amplifier circuit used in the volume circuit itself (offset of the current capability on the left and right sides) and to cancel the offset reliably.
[0031]
However, in reality, providing a large-scale control system or a dedicated circuit only for the offset cancellation of the operational amplifier circuit and the comparator is necessary to prevent an increase in the occupied area of the semiconductor device (IC) or to reduce the power consumption. It is difficult in view of the demand for power.
[0032]
Therefore, in the present invention, the offset of the operational amplifier circuit is measured by a comparator, a clock corresponding to the offset is generated by digital signal processing from the measurement result, and the equivalent resistance is finely adjusted by a switched capacitor operated by the clock. To cancel the offset.
[0033]
That is, in the operational amplifier circuit of the present invention, the offset cancel function is activated at any time to cancel the offset voltage. For example, the offset voltage is canceled as follows.
[0034]
If the amount of current flowing through the transistors forming a differential pair (differential pair transistors) is unbalanced, the voltage of each terminal of the transistors forming the current mirror changes by the amount of the offset.
[0035]
The changed voltage is compared with a voltage at the time of design (reference voltage) by a comparator, and when the voltage is larger than the reference voltage, it is changed to a digital value of +1.
[0036]
A clock having a frequency reflecting this result is generated by a clock generator, and a clock having a cycle of ON / OFF of a switched capacitor circuit in the operational amplifier circuit is supplied. An equivalent resistance (trimming resistance) of several hundred kilohms or more is generated between the drain terminal and the ground in proportion to the clock frequency, and the offset is canceled by trimming this resistance.
[0037]
However, since the offset of a circuit having a transistor forming a differential pair usually has a random value, a desired bias cannot be applied no matter how the bias of the transistor connected to the switched capacitor circuit is adjusted. That situation occurs.
[0038]
To prevent this, it is effective to make the sizes of the transistors forming the differential pair different from each other in advance and intentionally give an offset to the left and right current capabilities in the initial state. Thus, it is possible to avoid a situation where the offset cannot be canceled.
[0039]
If the offset cancellation of the D / A converter is performed using the operational amplifier circuit with the offset cancellation function based on such digital processing, the offset can be accurately and reliably adjusted for a long time. .
[0040]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0041]
(Embodiment 1)
FIGS. 1 and 2 are circuit diagrams showing the principle configuration of a differential amplifier circuit having an offset adjusting function according to the present invention.
[0042]
FIG. 1 shows a circuit configuration in which the input stage transistors N411 and N412 forming a differential pair are N-type MOS transistors. FIG. 2 shows that the input stage transistors P421 and P422 forming a differential pair are P-type MOS transistors. 3 shows a circuit configuration in the case of a transistor.
[0043]
In the circuit of FIG. 1, P411 and 412 constitute a current mirror load, and N413 constitutes a constant current source. P413 and N414 constitute an output stage circuit of a push-pull configuration.
[0044]
Similarly, in the circuit of FIG. 2, N421 and N422 form a current mirror load, and P423 forms a constant current source. P421 and P422 constitute a push-pull output stage circuit. P424 and N423 constitute an output stage circuit of a push-pull configuration.
[0045]
VDD (power supply voltage) is 3V.
[0046]
In FIG. 1, a switched capacitor SC411 (consisting of a switch S411 and a capacitor C411) is connected to a connection point between the drain of the input-stage transistor N411 and the drain of the input-side transistor P411 of the current mirror serving as the load.
[0047]
The switch S411 is driven by the switching clock, and by changing the frequency of the switching clock, the equivalent resistance of the switched capacitor changes, the amount of charge extracted changes only by a very small amount, and the left and right offsets of the differential circuit change. Scaled down.
[0048]
Hereinafter, the operation of the switched capacitor circuit will be briefly described.
[0049]
By continuously turning on and off the switch at a certain cycle (this is realized by a clock having a square wave), the amount of change per unit time of the electric charge charged to the capacitor connected to this switch, that is, the current Is determined.
[0050]
The current I is represented by the following equation (1).
I = fsCrV (1)
R = V / I = 1 / (fsCr) (2)
Here, fs indicates the clock frequency (reciprocal of the ON / OFF cycle), CR indicates the capacity connected to the switch, and V indicates the voltage.
[0051]
From the equation (2), the switched capacitor circuit SC411 can be regarded as a resistance inversely proportional to the frequency. For example, when the clock frequency is 10 MHz and the capacitance is 1 pF, the resistance is equivalent to 100 kΩ.
[0052]
By connecting a resistor that is inversely proportional to this frequency between the point in the operational amplifier circuit where the bias is to be adjusted and the lowest potential (0 V), a path through which the current flows to the lowest potential can be provided at the above-described location, and this current is offset The switching frequency is adjusted to match the current.
[0053]
Similarly, in the circuit of FIG. 2, the offset can be reduced by changing the switching frequency of the switched capacitor SC421.
[0054]
Thus, the switched capacitor used in the present invention functions as a trimming resistor (digital variable resistor).
[0055]
Hereinafter, the operation of the differential amplifier circuit of FIG. 1 (or FIG. 2) at the time of offset adjustment will be described.
[0056]
Note that the channel conductance (W / L) of a transistor (differential transistor, input stage transistor) forming a differential pair is set to, for example, 1: 2 in order to enable bias adjustment with an equivalent resistance by a switched capacitor circuit. However, since the current mirror load is used, the amount of current on the left and right sides of the differential circuit is 1: 1 as a theoretical value regardless of the difference in channel conductance. Become.
[0057]
As described above, the current amounts on the left and right sides of the differential circuit are theoretically the same, but in reality, imbalance occurs due to various factors. According to the present invention, the adjustment is automatically made in a direction in which the imbalance is eliminated.
[0058]
FIG. 3 is a diagram showing a configuration for changing the switching frequency of the switched capacitor (SC) in the differential amplifier circuit 10 shown in FIG. 2 (the same applies to the differential amplifier circuit of FIG. 1) in a direction to reduce the offset. FIG. 3 is a diagram for explaining a circuit configuration.
[0059]
In FIG. 3, switches SW1 and SW2 and an SC control circuit 20 are provided.
[0060]
In a period in which the offset is adjusted (that is, a period in which the switching frequency of the switched capacitor (SC) is updated in a direction to reduce the offset of the differential amplifier circuit), both the switch 1 and the switch 2 are switched to the terminal a. As a result, the reference voltage generated from the reference voltage source V122 is applied to the two input terminals 12 and 14 of the differential amplifier circuit 10.
[0061]
If the differential amplifier circuit 10 is ideally adjusted, its output Vout should be a predetermined voltage (for example, half the power supply voltage VDD). , The voltage level of the output Vout slightly deviates from the ideal value.
[0062]
This shift is detected by the SC control circuit 20, and the switching frequency of the switched capacitor SC1 is changed in a direction to reduce the shift (offset).
[0063]
After the offset adjustment, the switches SW1 and SW2 are switched to the terminal b, and the normal input signal Vin is input to the terminal a of the switch SW1.
[0064]
FIG. 4 shows a specific configuration example of the SC control control 20.
[0065]
FIG. 4 shows the same contents as FIG. However, FIG. 4 does not show the switch SW2 in FIG.
[0066]
As shown in FIG. 4, the SC control circuit 20 includes a comparator 122 that compares the output level of the differential amplifier circuit 10 with a reference voltage V121, and a switched capacitor (SC1) built in the differential amplifier circuit 10. A control clock generator (including a determination circuit 123, a clock generator, and a latch 125) that generates a switching clock (control clock) is provided.
[0067]
The determination circuit 123 configuring the control clock generator 130 determines the amount of offset in the differential amplifier 10 based on the level of the output voltage of the comparator 122, and generates a control clock in a direction to reduce the offset. Instruct the clock generator 124.
[0068]
Information on the frequency of the control clock output from the clock generator 124 (including the past history) is stored in the latch 125. The frequency information of the control clock is appropriately referred to as needed.
[0069]
The switched capacitor SC1 built in the differential amplifier circuit 10 is driven by the control clock output from the clock generator 124, whereby the equivalent resistance is finely adjusted and the offset is reduced.
[0070]
FIG. 5 is a diagram showing a result of examining, by computer simulation, how the offset in the differential amplifier circuit having the configuration of FIG. 2 changes by changing the frequency of the switched capacitor.
[0071]
The vertical axis in FIG. 5 indicates the offset voltage of the differential amplifier circuit, and the horizontal axis indicates the time elapsed from time T1. Before time T2, the switched capacitor (SC) is off, and after time T2, the switched capacitor (SC) is on.
[0072]
Further, in the figure, a voltage {circle around (1)} (1.5254V) is an offset voltage when the switched capacitor (SC) is off.
[0073]
The voltage {circle around (2)} (1.000522V) is the offset voltage when the switching frequency of the switched capacitor (SC) is set to 13 MHz (as shown by the black band on the right side of the figure, the offset voltage is within a minute range). Because the voltage fluctuates, the center value of the voltage distribution is referred to as an offset voltage).
[0074]
The voltage {circle around (3)} (1.5136V) indicates an offset voltage when the switching frequency of the switched capacitor (SC) is set to 20 MHz.
[0075]
As shown, by changing the switching frequency, the offset voltage can be finely adjusted on the order of 10-5. The present invention adjusts a very small offset using this principle.
[0076]
Even if such fine adjustment is performed, the level of the adjustment is extremely small, so that the small signal equivalent circuit of the transistor forming the differential circuit does not change at all.
[0077]
FIG. 6 is a flowchart showing the procedure for adjusting the offset voltage of the circuit having the differential configuration described above.
[0078]
That is, an offset voltage (offset amount) is measured for a differential circuit using a switched capacitor (SC) and having a trimming resistor for fine adjustment of offset (step 40).
[0079]
Then, by changing the switching frequency of the switched capacitor (SC) (for example, by switching the frequency stepwise), the resistance value of the trimming resistor can be finely adjusted at a minute level that does not affect the small signal characteristics of the transistor. By performing adjustment (trimming), for example, the offset voltage of about several mV is reduced (step 50).
[0080]
(Embodiment 2)
FIG. 7 is a diagram showing a more specific circuit configuration for realizing the function of automatically controlling the switching frequency of the switched capacitor built in the differential amplifier circuit described in FIG.
[0081]
When adjusting the switching frequency of the switched capacitor (SC1) built in the differential amplifier circuit 10 using the configuration of FIG. 4, first, it is necessary to adjust the offset in the comparator 122 in the SC control circuit 20. is there. This is because accurate determination cannot be performed if the comparator 122 itself that should determine the offset amount of the differential amplifier circuit 10 has an offset exceeding the allowable value.
[0082]
Therefore, in the configuration of FIG. 7, a switched capacitor (SC2) for resistance trimming and a plurality of switches (SW4 to SW7) are also provided in the comparator 62 in the SC control circuit 20, so that the switched capacitor SC1, A switching clock can be selectively supplied to one of the SC2s.
[0083]
Then, first, the offset of the comparator 62 in the SC control circuit 20 is adjusted using SC2, and then the offset of the differential amplifier circuit 10 is adjusted using SC1.
[0084]
Further, in the configuration of FIG. 7, the frequency of the clock supplied to the switched capacitor can be switched in three stages. That is, the clock output from the oscillation circuit 52 is frequency-divided by each of the frequency-dividing circuits 54, 56, and 58, and one of the output clocks of each frequency-dividing circuit is selected by the switch SW7. Supply to SC1 or SC2.
[0085]
The specific operation of the offset adjustment in the circuit of FIG. 7 will be described with reference to FIGS.
[0086]
FIG. 8 is a diagram for explaining the operation of adjusting the offset of the comparator 62. For easy understanding, signal paths related to this operation are indicated by thick lines in the figure.
[0087]
As shown, the switches SW4, SW5, SW6, and SW8 are all switched to the terminal a. Then, a voltage of the same level as the reference voltage V121 applied to the non-inverting terminal of the comparator 62 (indicated as Vin in FIG. 8) is input, and this input voltage is supplied via the switches SW4, SW5, and SW8. , And an inverting terminal of the comparator 62.
[0088]
Then, the determination circuit 123 determines how much the output level of the comparator 62 deviates from the ideal value.
[0089]
Here, if the deviation is equal to or less than the allowable value, there is no need to adjust the offset of the comparator 62, so the determination circuit 123 instructs the clock control circuit 127 to that effect, and the clock control circuit 127 Switch to terminal c. Thus, the supply of the clock to the switched capacitor SC2 built in the comparator 62 is stopped. The configuration may be such that the switched capacitor SC2 (SC1) is always operated. In this case, the switching frequency is maintained at a standard value (neutral value) when adjustment is not required.
[0090]
On the other hand, when the deviation amount of the output level of the comparator 62 exceeds the allowable value, the clock control circuit 127 receives the detection result of the determination circuit 123 and sets the switch SW7 so that the deviation amount falls within the allowable range. Is switched to one of the terminals d to f.
[0091]
The switching control clock output from the switch SW7 is supplied to the switched capacitor SC2 in the comparator 62 via the switch SW6, and the offset of the comparator is reduced by trimming the resistance.
[0092]
FIG. 9 is a diagram for explaining an operation of adjusting the offset of the differential amplifier circuit 10. As in FIG. 8, signal paths related to this operation are indicated by thick lines in the m diagram.
[0093]
As shown, all of the switches SW4, SW5, SW6, and SW8 are switched to the terminal b.
[0094]
The reference voltage V is applied to the inverting terminal 12 of the differential amplifier circuit 10 via the switches SW4 and SW5, similarly to the non-inverting terminal 14. _ref1 Is given.
[0095]
The output level of the differential amplifier circuit 10 is compared with the reference voltage V121 by the comparator 62, the output of the comparator is watched by the determination circuit 123, and the clock control circuit 127 switches the switch SW7.
[0096]
A switching clock of a desired frequency is supplied to the switch 31 of the switched capacitor SC1 incorporated in the differential amplifier circuit 10 via the switch SW7, and the resistance is trimmed, thereby reducing the offset of the differential amplifier circuit. Is done.
[0097]
As described above, in the present embodiment, it is only necessary to switch the switch to select the path or the frequency of the switching clock, so that the configuration is simple and realization is easy.
[0098]
Further, for example, by dividing the high-speed clock into several stages and dividing the frequency, a switching clock having a desired frequency can be obtained, and also in this respect, the configuration is simplified.
[0099]
(Embodiment 3)
FIG. 10 is a diagram showing a main configuration of an audio output system circuit (PCM codec LSI) in which the differential amplifier circuit with an offset adjustment function 10 of the present invention is mounted.
[0100]
As shown, the digital audio signal is converted to an analog signal by a D / A converter 311, a high-frequency component is removed by a low-pass filter 312, and is input to a volume circuit 313.
[0101]
As illustrated, in the present embodiment, the operation clock f0 of the D / A converter 311 is generated by a frequency synthesizer using the PLL 320 based on the system clock of the PCM codec LSI. The frequency of the operation clock f0 of the D / A converter 311 is, for example, several MHz.
[0102]
The volume circuit 313 includes the differential amplifier circuit 10 (inverting amplifier circuit incorporating the switched capacitor SC1) of the present invention described above and a switch circuit GC (switches S211 to S214) for volume (gain) adjustment. ). Each switch of the switch circuit GC is controlled by an externally applied volume adjustment signal.
[0103]
When the switches S211 to S214 are all in the open state, the gain of the differential amplifier circuit 10 is-(R212 + R213 + R214 + R215) / R211 and is the maximum gain.
[0104]
When only the switch S214 is closed, the gain of the differential amplifier circuit 10 is-(R216 / R211), which is the minimum gain.
[0105]
For example, the gain when all the switches are turned off is 11 times, the gain when the switch S211 is turned on is -0.8 times, and the gain when the switch S213 is turned on is -0.4 times. Become.
[0106]
The output signal of the volume circuit 313 is subjected to impedance conversion by the voltage follower 314, and the speaker 315 is driven by the output signal of the voltage follower 314.
[0107]
The switched capacitor SC1 built in the differential amplifier circuit 10 is controlled by the SC control circuit 324. The SC control circuit 324 measures the deviation of the output of the differential amplifier circuit 10 from the ideal value, and selects the optimal clock from among the clocks f1, f2, and f3 based on the measurement result. Is supplied to the switched capacitor SC1 in the differential amplifier circuit 10.
[0108]
The clocks f1, f2, and f3 are obtained by dividing the LSI system clock by two frequency dividers 321 to 323. The frequencies of the clocks f1, f2, f3 are, for example, 1 MHz to several tens MHz.
[0109]
A point to be noted in the present embodiment is that all necessary clocks can be easily generated based on a system clock of the LSI (that is, a clock used in a normal operation of the LSI). Since the frequency of the switching clock of the switched capacitor SC1 is sufficiently higher than the operation clock of the D / A converter 311 for processing the above, even if the noise accompanying the driving of the switched capacitor SC1 leaks to the outside, It is inaudible to human ears and does not cause any problems.
[0110]
Hereinafter, the pop noise and the cancellation of the pop noise will be described.
[0111]
First, a signal at the time of silence (a signal whose amplitude is almost 0 and a signal almost close to DC) is input to a volume circuit having no offset in the operational amplifier circuit in the volume circuit, and in this state, the volume (gain) is changed at time T. In this case, the offset voltage is also amplified, and a step wave (a waveform in which the DC level rapidly changes to a different DC level in a certain time) occurs before and after the volume is changed.
[0112]
At the same time as the generation of such a step wave, ringing appears immediately after the change, and this ringing is generated as an unnecessary sound.
[0113]
Even when a signal at the time of silence (a signal having almost zero amplitude and almost DC) is inputted to a volume circuit having no offset in the operational amplifier circuit in the volume circuit, the volume (gain) is changed after time T in this state. The signal does not change before and after the volume is changed, and no unnecessary sound is generated.
[0114]
The offset of the volume circuit, that is, the unnecessary sound (pop noise) is offset to a block monitored by a comparator as described in Japanese Patent Application Laid-Open No. H11-234130, for example, by canceling the offset of the entire system. In a configuration in which only the sum of is canceled, reduction (cancellation) cannot be performed.
[0115]
In order to cancel such an offset, the system must be such that the offset cancellation is completed in one block in the middle, and the technique of the present invention can do so.
[0116]
(Embodiment 4)
FIG. 11 is a block diagram illustrating a configuration of a wireless receiver to which the present invention has been applied.
[0117]
A feature of this embodiment is that a volume circuit 342 having the same configuration as the volume circuit 313 shown in FIG. 10 is provided in the D / A converter 340 built in the wireless receiver, and the switching frequency of the switched capacitor SC3 is reduced. , And the SC control circuit 344 performs feedback control.
[0118]
As illustrated, the wireless receiver includes a receiving circuit 329, a demodulator 330, a D / A converter 340 including a volume circuit 342, a power amplifier 350 in an output stage, and a speaker 360.
[0119]
By changing the frequency of the switched capacitor SC3 and finely adjusting the equivalent resistance, the offset of the volume circuit 342 is reduced to within an allowable range, so that even when the volume is suddenly increased, unpleasant pop noise is generated. This does not occur, and it is possible to prevent the quality of the output sound from lowering.
[0120]
(Embodiment 5)
FIG. 12 is a diagram showing a configuration of a CDMA wireless transmitter (mobile phone) to which the present invention is applied.
[0121]
In a CDMA transmitter, if the offset amount is different between the D / A converters corresponding to each of the one signal and the Q signal (that is, the input characteristics of the two D / A converters are different), 1 , Q out of phase, resulting in a transmission error. Therefore, it is necessary to cancel the input / output offset of the D / A converter and make the characteristics of the D / A converter uniform.
[0122]
In order to cancel the input / output offset of the D / A converter, first, it is necessary to measure the offset amount, and a comparator (voltage comparator) is used for this purpose. Based on the comparison result by the comparator, a control signal for compensating the offset is obtained, and the offset of the D / A converter is canceled.
[0123]
In the CDMA transmitter shown in FIG. 12, transmission data is QPSK-modulated by a digital modulator 521, I and Q signals are converted into analog signals by D / A converters 522a and 522b, and variable gain amplifiers 530a and 530b The signal is amplified by a built-in switched capacitor SC, quadrature-modulated by a quadrature modulator 523, and transmitted from an antenna 525 via a transmission circuit 524.
[0124]
If there is an offset outside the allowable range in the variable gain amplifiers 530a and 530b, if the gain increases rapidly, the offset may be amplified and unnecessary noise may be transmitted.
[0125]
Therefore, in the present invention, SC control circuits 540a and 540b are provided in each of the variable gain amplifiers 530a and 530b, and the switched capacitors SC incorporated in the variable gain amplifiers 530a and 530b are controlled so that the offset is within an allowable range. Reduce.
[0126]
The offset adjusting method using the switched capacitor according to the present invention can be directly applied to a circuit in which offset is a problem, so that the method is easy to implement and can be widely used in various devices.
[0127]
(Embodiment 6)
In the circuit shown in FIG. 13, the offset fine adjustment using a switched capacitor is performed on a comparator and an amplifier included in a circuit that cancels the offset of the D / A converter by correcting the input digital value. .
[0128]
The negative feedback loop for adjusting the offset of the D / A converter 517 includes a low-pass filter (LPF) 518, switches SW10 and SW11, a variable gain amplifier 519, switches SW13 and SW14, a comparator 511, and a determination circuit. 512, a latch 513, and an adder 516.
[0129]
That is, digital data (for example, VDD / 2) corresponding to the center voltage of the circuit is input to the adder 516, and correction for canceling the offset of the D / A converter 517 is performed using the above-described negative feedback loop. The digital value is calculated by the determination circuit 512, and the correction value is added to the adder 516 via the latch 1 (reference numeral 513) to correct the input digital value itself.
[0130]
In order to accurately perform such feedback control, the offset of the variable gain amplifier (amplifier with a volume function) 519 and the comparator 511 must be within an allowable range.
[0131]
In addition, even when the feedback system operates and the offset of the D / A converter 517 is canceled, a correction digital value is calculated based on the output of the variable gain amplifier 519, and is fed back to the adder 516. Therefore, no offset is compensated for in the amplifier 519. Therefore, when the gain of the variable gain amplifier 519 is rapidly increased, uncomfortable pop noise may be output.
[0132]
Therefore, in the circuit of FIG. 13, before performing the above-described negative feedback control, offset adjustment of the variable gain amplifier 519 (with the built-in switched capacitor SC) and the comparator 511 is performed.
[0133]
In this case, first, the switch SW511 is switched to the terminal b, and the switch SW12 is switched to the terminal a. Further, the switches SW12 and SW13 are switched to the terminal a, and the reference voltage V is applied to two input terminals of the comparator 511. _REf2 give.
[0134]
Then, the switched capacitor in the comparator 511 is controlled to reduce the offset.
[0135]
Next, the switch SW12 is switched to the terminal b, the switches SW10 and SW11 are switched to the terminal a, and the reference voltage V is applied to two input terminals of the comparator 511. _ref3 give. The switches SW13 and SW14 are switched to the terminal b.
[0136]
Then, the offset of the variable gain amplifier 519 is reduced by finely adjusting the switched capacitor SC incorporated in the variable gain amplifier 519.
[0137]
Thereafter, the switches SW10 and SW11 are returned to the terminal b, the switch SW511 is switched to the terminal a, and negative feedback control is performed to add a correction value to the adder 516 as described above.
[0138]
FIG. 14 summarizes the main procedure of the offset cancellation process for preventing pop noise described above.
[0139]
A trimming resistor using a switched capacitor (SC) is connected to a circuit in which there is a risk of causing an offset which causes pop noise (step 600).
[0140]
Next, the offset amount is measured (Step 602). The switching frequency of the switched capacitor (SC) is adjusted in a frequency band (frequency band higher than the frequency band for audio signal processing) sufficiently higher than the operation clock of each part of the audio output system (audio codec). Is finely adjusted (trimmed) to reduce the offset (step 604).
[0141]
According to the present invention, a volume circuit and a comparator having a simple configuration and having an offset adjustment function can be realized. In addition, by performing processing for canceling the offset of the D / A converter using the comparator, adjustment with less error can be performed. In addition, the time required for offset adjustment can be reduced, and the ease of LSI design (design flexibility) can be improved.
[0142]
【The invention's effect】
As described above, according to the present invention, the offset of a differential circuit (differential amplifier circuit or operational amplifier circuit) that generates an offset in a volume circuit can be reliably performed without being affected by an offset in another analog block. , Can be canceled for a long time.
[0143]
By applying the present invention to a volume circuit (including the one obtained by adjusting the gain of a variable gain amplifier) or a D / A converter incorporating this volume circuit, the offset of the circuit can be reduced, and for example, The output of the pop sound from the speaker can be reliably reduced for a long time.
[0144]
In addition, the time required for offset adjustment can be reduced, and the ease of LSI design (design flexibility) can be improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example of a differential amplifier circuit including a switched capacitor (SC) for resistance trimming.
FIG. 2 is a circuit diagram showing another example of a differential amplifier circuit including a switched capacitor (SC) for resistance trimming.
FIG. 3 is a circuit diagram showing a configuration of a differential amplifier circuit having a function of reducing offset using a switched capacitor.
4 is a circuit diagram showing an example of a configuration of an SC control circuit described in FIG.
FIG. 5 is a diagram showing an example of a change in an offset voltage by changing the frequency of a switched capacitor (an example by computer simulation);
FIG. 6 is a flowchart for explaining main steps of an offset adjustment method according to the present invention.
FIG. 7 is a circuit diagram showing a configuration of an example of a differential amplifier circuit to which the present invention is applied.
8 is a circuit diagram for explaining an operation for reducing the offset of the comparator in the differential amplifier circuit of FIG. 7;
9 is a circuit diagram for explaining an operation of reducing the offset of the differential amplifier circuit of FIG.
FIG. 10 is a block diagram showing a configuration of an audio output system circuit (a circuit including a PCM codec LSI);
FIG. 11 is a block diagram showing an example of a configuration of a wireless receiver incorporating a volume circuit to which the present invention is applied.
FIG. 12 is a block diagram showing a configuration of a CDMA wireless transmitter to which the present invention is applied;
FIG. 13 is a circuit diagram showing a configuration of a circuit for canceling an offset of a D / A converter to which the present invention is applied.
FIG. 14 is a flowchart showing a main procedure of an offset canceling process for preventing pop noise.
FIG. 15 (a) is a circuit diagram showing a configuration of a volume circuit (variable gain amplifier) in which a gain can be adjusted by a volume adjustment signal in a low gain state, for explaining a problem of the related art.
(B) A circuit diagram showing a configuration of a volume circuit (variable gain amplifier) in which a gain can be adjusted by a volume adjustment signal in a high gain state, for explaining a problem of the related art.
(C) A diagram showing an output signal (no change even if the gain of the volume circuit is sharply increased) when the offset of the volume circuit is within an allowable range.
(D) A diagram showing a situation in which ringing (pop noise) occurs due to a sudden increase in volume because the offset of the volume circuit is outside the allowable range.
[Explanation of symbols]
10 Differential amplifier circuit with built-in switched capacitor for trimming
20 SC control circuit
SC411, SC421 Switched capacitor
S411, S421 switch
C411, C421 capacity

Claims (11)

A trimming resistor including a switched capacitor is connected to at least one of the left and right current paths of the differential circuit, and an offset amount is detected by comparing an output signal level of the differential circuit with a target level. And changing the switching frequency of the switched capacitor in a direction to reduce the offset to finely adjust the resistance value of the trimming resistor. In claim 1,
The switching frequency of the switched capacitor is changed by switching the frequency stepwise, and the degree of adjustment of the resistance value of the trimming resistor by the switching is determined before and after the switching frequency is changed. Wherein the small signal equivalent circuit of the transistors constituting the differential circuit does not substantially change. In claim 1 or claim 2,
An offset adjustment method for a differential circuit, characterized in that the switched capacitor is switched in a frequency band higher than a frequency band necessary for digitally processing a signal input to the differential circuit. A differential circuit comprising a transistor forming a differential pair and a load element of each transistor forming the differential pair, and having a function of adjusting an offset between a current path on the left side and a current path on the right side. So,
A switched capacitor functioning as a trimming resistor, connected to at least one of the connection points between each of the transistors forming the differential pair and each of the load elements;
The output signal level of the differential circuit is compared with a target level, and based on the comparison result, the switching frequency of the switched capacitor is changed in a direction to reduce the offset of the differential circuit, and A switched capacitor control circuit for fine-tuning the resistance of the resistor;
A differential circuit having an offset adjustment function, comprising: In claim 4,
The change of the switching frequency of the switched capacitor by the switched capacitor control circuit is performed by switching the frequency stepwise, and the degree of adjustment of the resistance value of the trimming resistor by the switching is determined by the switching frequency. And a small-signal equivalent circuit of the transistors constituting the differential circuit is not substantially changed before and after the change. In claim 4 or claim 5,
The switched capacitor control circuit switches the switched capacitor in a frequency band higher than a frequency band required for digitally processing a signal input to the differential circuit. . The differential circuit according to any one of claims 4 to 6, wherein the differential circuit is used in a circuit for audio output having a volume control function. A comparator comprising the differential circuit according to claim 4. A volume circuit including the differential circuit according to claim 4. A D / A converter including the differential circuit according to claim 4. A switched capacitor as a trimming resistor is connected to a portion of at least one of the circuit blocks constituting the signal processing circuit that needs to be adjusted to reduce the offset, and the switching frequency of the switched capacitor is adjusted by the signal processing. An offset adjustment method comprising: performing fine adjustment within a band higher than a clock for signal processing in a circuit and performing offset adjustment by digital resistance trimming.

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