JP2004119455A - Position detecting method, position detecting device, exposure method, and aligner - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a position detecting method and an aligner which are capable of carrying out very robust alignment even when there are wafer processing errors (Wafer Induced Shift) and errors induced by a device (Tool Induced Shift). <P>SOLUTION: The position detecting method and a position detecting device are equipped with an acquisition means acquiring alignment actual waveforms from the aligner, and a generating means which generates simulation waveforms by the use of the surface information of a resist or a wafer underlying layer obtained from a three-dimensional form measuring device. After TIS and WIS are determined so as to make the alignment actual waveforms identical with the simulation waveforms, a plurality of waveforms are generated by applying TIS and WIS on the basis of the determined simulation waveforms, signal processing or signal processing parameters are optimized on the basis of the waveforms, and the result is fed back to the aligner. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, a relative positioning (alignment) of a fine electronic circuit pattern such as an IC, LSI, or VLSI formed on a reticle surface of a first object and a wafer of a second object in an exposure apparatus for manufacturing a semiconductor. And a position detecting method for performing the above. The present invention particularly relates to a position detection method and an exposure apparatus that require high-precision alignment even in a situation where a WIS (Wafer Induced shift), which is a wafer process error, can occur.
[0002]
[Prior art]
2. Description of the Related Art In a projection exposure apparatus for manufacturing a semiconductor device, it is required that a circuit pattern on a reticle surface can be projected and exposed on a wafer surface with a higher resolution as a circuit becomes finer and higher in density. Since the projection resolution of the circuit pattern depends on the numerical aperture (NA) of the projection optical system and the exposure wavelength, methods for increasing the resolution include increasing the NA of the projection optical system and shortening the exposure wavelength. Has been adopted. Regarding the latter method, the exposure light source is shifting from g-line to i-line, and further from i-line to excimer laser. Excimer lasers having exposure wavelengths of 248 nm and 193 nm have already been put to practical use and used.
[0003]
At present, a VUV exposure method with a wavelength of 157 nm and a EUV exposure method with a wavelength of 13 nm in which the oscillation wavelength is further shortened are being studied as candidates for a next-generation exposure method.
[0004]
Also, semiconductor device manufacturing processes are diversifying, and technologies such as a W-CMP (Tungsten Chemical Mechanical Polishing) process are attracting attention as a planarization technology for solving the problem of insufficient depth of an exposure apparatus.
[0005]
Also, the structure and material of the semiconductor device are various, for example, P-HEMT (Pseudomorphic High Electron Mobility Transistor), M-HEMT (Metamorphe-HEMT), SiGe, An HBT (Heterojunction Bipolar Transistor) using SiGeC or the like has been proposed.
[0006]
On the other hand, with the miniaturization of circuit patterns, it is also required to align a reticle on which a circuit pattern is formed and a wafer onto which the reticle is projected with high precision, and the required precision is １ ／ of the circuit line width. For example, the required accuracy in the current 180 nm design is 1/3 of 60 nm.
[0007]
At present, most of the alignment methods actually used in an exposure apparatus perform image processing of an electric signal obtained by forming an optical image of an alignment mark formed on a wafer on an image sensor such as a CCD camera, The position of the mark on the wafer is detected.
[0008]
Generally, when performing alignment between a reticle and a wafer, a major factor that deteriorates the alignment accuracy is as follows.
(1) Non-uniformity of the film thickness in the vicinity of the alignment mark of the resist (2) Asymmetry of the shape of the alignment mark under the wafer. WIS (Wafer Induced Shift) is a cause of the alignment error caused by these wafers.
I'm calling In this specification, in the following description, (1) the alignment error caused by the resist is referred to as “resist WIS”, and (2) the alignment error caused by the wafer base is referred to as “base WIS”. I do.
[0009]
On the other hand, the alignment error factor caused by the exposure apparatus is called TIS (Tool Induced Shift), and specifically includes coma aberration and spherical aberration of an illumination system, telecentricity of illumination light, and the like.
[0010]
It is also pointed out that a factor causing an actual alignment error is that the WIS and the TIS mutually affect each other.
[0011]
[Problems to be solved by the invention]
Improving the overlay accuracy on an actual device wafer, one of the three major performances of an exposure apparatus, can be said to be an essential issue for improving the performance of semiconductor devices and the production yield. However, with the introduction of a special semiconductor manufacturing technique such as a CMP (Chemical Mechanical Polishing) process, a problem that a defect occurs in a position detection mark has occurred, although the structure of the circuit pattern is good. This is because, with the miniaturization of the circuit pattern, the difference between the line width of the circuit pattern and the alignment mark increases, and the process conditions such as film formation, etching, and CMP are fine. .15 .mu.m), but often occurs because alignment marks with large line widths (line widths of 0.6 to 4.0 .mu.m) are not optimized.
[0012]
If an attempt is made to match the line width of the alignment mark with the line width of the circuit pattern, the resolution of the microscope used for alignment is insufficient, so that the signal strength or contrast is reduced, and the stability of the alignment signal is degraded. A microscope that can detect alignment marks with the same line width as the circuit pattern requires an alignment light source with a large NA and a short wavelength, making it a microscope similar to a projection optical system, and raising the cost of equipment. Will occur.
[0013]
At present, in such a situation, the conditions of the process are changed to determine the conditions by trial and error so that the appropriate conditions are obtained for both the alignment mark and the circuit pattern. After manufacturing and evaluating the exposure, an alignment mark having the best line width is used.
[0014]
Therefore, it took an enormous amount of time to determine the optimal conditions (parameters). Also, even after the parameters are once determined, if, for example, a wafer process error WIS occurs, it may be necessary to change the parameters of the manufacturing apparatus again in accordance with the change of the manufacturing process in accordance therewith. In this case, too, much time is required. In the future, as circuit patterns become finer, it will become increasingly difficult to manufacture both circuit patterns and alignment marks over the entire surface of the wafer without defects due to the introduction of new semiconductor processes and the 300 mm wafer diameter. is expected.
[0015]
[Means for Solving the Problems]
The present invention has been made in view of the above-described background, and its object is to reduce the error TIS caused by the apparatus even when there is a wafer process error WIS such as a defect of an alignment mark or uneven resist coating. It is an object of the present invention to provide a position detection method and an exposure apparatus which can execute an alignment accurately and quickly even in the case where there is.
[0016]
In order to achieve this object, a position detection method and an exposure apparatus according to the present invention include an acquisition unit for acquiring a first waveform and a generation for generating a second waveform, which are necessary for mark position detection in the exposure apparatus. Means for determining an input condition of the second generating means so that the first acquired waveform and the second generated waveform coincide with each other, assigning an input condition to the second generated waveform, Is generated, the signal processing is optimized for a plurality of waveforms, and the result is fed back to the exposure apparatus.
[0017]
Further, an optimization technique is characterized in that a signal processing with a minimum sensitivity to an input condition is determined while evaluating a shift amount (offset) from a true value due to a plurality of signal processings.
[0018]
Another optimization technique is characterized in that a signal processing parameter having the minimum sensitivity to an input condition is determined while evaluating a deviation amount (offset) from a true value due to a plurality of signal processing parameters. .
[0019]
Further, the second waveform generating means is characterized in that the second waveform generating means generates the second waveform based on the measurement information obtained by the measuring means outside the exposure apparatus. Further, the measurement information is characterized in that it is information on the surface of the base of the wafer and the surface of the resist.
[0020]
In addition, the range in which the input condition of the generation unit that generates the second waveform is changed is a range in which a plurality of pieces of the measurement information acquired by the measurement unit are accumulated, and the range is determined based on the accumulated measurement information. It is characterized by: Further, preferably, the input condition of the generating means for generating the second waveform is a resist WIS or a base WIS.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[0022]
FIG. 2 is a schematic view of the semiconductor exposure apparatus of the present invention. It should be noted that parts other than the points of the present invention are not shown. The exposure apparatus 1 includes a reduction projection optical system 11 for reducing and projecting a reticle 10 on which a certain circuit pattern is drawn, a wafer chuck 13 for holding a wafer 12 on which a base pattern and an alignment mark are formed in a previous process, and a predetermined wafer. It comprises a wafer stage 14 for positioning at a position, an alignment detection optical system 15 for measuring the position of an alignment mark on the wafer, and the like.
[0023]
Next, the principle of alignment detection will be described. FIG. 3 shows main components of the alignment detection optical system 15. Illumination light from the light source 18 is reflected by the beam splitter 19, passes through the lens 20, and illuminates the alignment mark 30 on the wafer 12. The diffracted light from the alignment mark 30 passes through the lens 20, the beam splitter 19, and the lens 21, and is received by the CCD sensor 22. Here, the alignment mark 30 is enlarged by the lenses 20 and 21 at an imaging magnification of about 100 times, and is formed on the CCD sensor 22.
[0024]
FIG. 1 is a schematic block diagram illustrating an embodiment of the present invention.
[0025]
First, data (waveform data) necessary for alignment is obtained from the exposure apparatus by an obtaining unit. Hereinafter, this is referred to as ADUL. Note that ADUL is an abbreviation for Alignment Data Up Load, and indicates that data necessary for alignment is obtained from the exposure apparatus.
[0026]
On the other hand, measurement information from a three-dimensional shape measurement device (hereinafter, profiler), which is a measurement means, that is, surface information of a resist near an alignment mark and a base of a wafer is acquired. Here, the detection of the three-dimensional shape of the alignment mark can of course be performed by an optical method. However, a scanning tunneling microscope as disclosed in Japanese Patent Publication No. 2735632 and a method disclosed in Japanese Patent Application Laid-Open No. Hei 5-217861 can be used. A high-resolution system such as an atomic force microscope (AFM) as described above can also be used.
[0027]
Next, based on the surface information of the resist and the wafer base obtained by the measurement unit and certain input conditions set by the input condition processing unit, an alignment signal is pseudo-generated using an optical simulator as a generation unit. . As the optical simulator, commercially available products include EMFlex, EM series, Metropole, CODEV (all of which are trade names), and the like. In the optical simulator, for example, the Maxwell's equation relating to the propagation of light is vector-wise solved using the finite element method, and it is possible to obtain what kind of signal the light from the alignment mark has in an actual configuration. Further, it is possible to simulate the detection signal of the alignment mark by the alignment scope in the actual configuration including the aberration of the optical system. Next, the actual waveform obtained by ADUL is compared with the pseudo waveform generated by simulation to evaluate the degree of coincidence. If they do not match, the input condition processing unit changes the input conditions to generate a simulation waveform. , Repeat until match.
[0028]
In the present embodiment, the input condition processing unit assigns a plurality of input conditions using the matched waveform as a new reference, and the optimization processing unit optimizes signal processing or processing parameters for the obtained plurality of generated waveforms. The parameters are fed back to the exposure apparatus.
[0029]
The present embodiment will be described with reference to the processing flowchart of FIG.
First, in step S1010, an actual ADUL waveform is acquired from the exposure apparatus.
[0030]
On the other hand, in step S1020, a three-dimensional shape (surface information) of the resist and the base is acquired using a profiler.
[0031]
In S1030, a waveform is generated using an optical simulator based on the surface information acquired in S1020.
[0032]
It is evaluated whether the waveform acquired in S1010 matches the waveform generated in S1030 (S1040). If they do not match, the input condition (TIS, WIS) is changed (S1050), and the two waveforms are changed. Are generated repeatedly so that the values match.
[0033]
Here, as a method of evaluating the degree of coincidence in S1040, the degree of coincidence from a certain template may be compared to evaluate whether or not the degree of coincidence falls within a certain allowable range. A method may be used in which a correlation with the other is obtained as a template and whether the degree of correlation exceeds a certain set threshold is evaluated.
[0034]
Next, in S1060, TIS or WIS is applied near the generation condition of the simulation waveform that matches the ADUL waveform, and a plurality of waveforms near the ADUL waveform are generated.
[0035]
In S1070, signal processing is performed on the plurality of waveforms, and signal processing or optimization of processing parameters is performed. Finally, in S1080, the optimal signal processing or processing parameters are fed back to the exposure apparatus.
[0036]
FIG. 5 is a diagram showing an example of occurrence of a resist WIS among the input conditions in S1050 or S1060.
[0037]
In FIG. 5, after the resist surface information acquired from the profiler is set to a location (A in the figure) that most matches the ADUL waveform, the resist is shaken in a range from α1 to α2 in the left-right direction on the paper based on the position. Thereby, a plurality of simulation waveforms are generated.
[0038]
FIG. 6 is a diagram illustrating an example of occurrence of the background WIS in the input conditions in S1050 or S1060.
[0039]
The underlayer WIS in FIG. 6 is a WIS related to a step of an alignment mark, and is set at a position where the surface information of the underlayer of the wafer obtained from the profiler most coincides with the ADUL waveform (B in FIG. 6). , Β1 to β2 to generate a plurality of simulation waveforms.
[0040]
FIG. 7 is an example of the occurrence of the background WIS different from FIG.
[0041]
The underlayer WIS in FIG. 7 is a WIS relating to the side wall angle of the alignment mark. After setting a place where the surface information of the underlayer of the wafer obtained from the profiler best matches the ADUL waveform, the position of the underlayer WIS is used as a reference. A plurality of simulation waveforms are generated by varying the side wall angles (left and right, respectively, γ1 and γ2).
[0042]
Next, FIG. 8 is a diagram for explaining a deviation from a true value in the signal processing of the present embodiment. As shown in FIG. 8, assuming that surface information of the wafer base and the resist has been obtained, the alignment mark side wall shape is substantially symmetrical, and if the alignment mark is vertical, the center between the side walls (A in the figure) is the mark position. Can be defined as the true value of For example, assuming that the mark position as a result of signal processing is shown in FIG. A ′, the difference between A and A ′ in the figure can be defined as a deviation from the true value. In the following description of the embodiments of the present invention, a deviation is defined as a deviation from the true value, and various deviations are performed using the deviation as an evaluation criterion, and the deviation is applied to signal processing or optimization of signal processing parameters. It is characterized by.
[0043]
In the present embodiment, the true value is not always necessary. For example, when the surface information of the wafer base is not ideal as shown in FIG. 8, the true value is calculated from the simulation waveform that matches the actual waveform from ADUL. Assuming that the mark position is temporarily set as a true value, evaluation may be performed based on a deviation from the provisional true value while shaking the WIS. Even in this case, it is possible to determine a signal processing robust to WIS in the vicinity of the actual ADUL waveform.
[0044]
FIG. 9 is a diagram illustrating the concept of signal processing optimization for explaining the first embodiment of the present invention.
[0045]
For a plurality of signal processings (P1 to P4), the amount of deviation in the range of the resist WIS from α1 to α2 set in FIG. 5 is obtained, and the processing with the smallest sensitivity of the amount of deviation to the resist WIS is determined as the optimal signal processing. (P4 in the figure)
FIG. 10 is a diagram illustrating the concept of optimizing signal processing parameters for explaining the second embodiment of the present invention.
[0046]
With respect to the plurality of signal processing parameters, the amount of deviation from the background WIS range β1 to β2 set in FIG. 6 is obtained, and the parameter having the smallest sensitivity of the deviation amount to the background WIS is determined as the optimal signal processing parameter.
[0047]
Here, a specific method of determining the WIS, β1, and β2 regarding the step of the alignment mark is to store a plurality of step information of the alignment mark obtained from the profiler, perform a statistical process, and then perform the range (for example, 3σ). The above range is set from β1 to β2 and shaken.
[0048]
FIG. 11 and FIG. 12 are diagrams illustrating the concept of signal processing optimization when there are two WISs, illustrating the third embodiment of the present invention. FIG. 11 is a diagram in which the signal processing P1 is performed on a simulation waveform generated while swaying γ1 and γ2 by taking the two WISs (γ1 and γ2) of FIG. 7 as an example, and a shift amount in the signal processing P1 is plotted. . In FIG. 10, the shift amount is small when both γ1 and γ2 are near zero, but the shift amount increases nonlinearly as γ1 and γ2 increase. In addition, when γ1 ≒ γ2, the shift amount tends to be small, which suggests that the left and right side wall angles γ are largely asymmetrical.
[0049]
FIG. 11 is a diagram in which the same processing as that of FIG. 10 is performed on a plurality of signal processes, and the shift amounts are plotted.
[0050]
In the present embodiment, the signal processing (in this case, P4) with the smallest sensitivity of the shift amount is determined as the optimal signal processing in the range of γ1 and γ2.
[0051]
FIG. 13 is a diagram illustrating the optimization of a plurality of signal processing parameters for explaining the fourth embodiment of the present invention.
[0052]
In FIG. 13, specifically, there are two signal processing parameters C and W, and as input conditions, for example, four types of WIS within a set range (WIS1, WIS2, WIS3, WIS4) are assumed. In the present embodiment, for each of WIS1 to WIS4, a region where the sensitivity of the shift amount falls below a certain threshold is determined, and the region A1 to region A4 is ANDed to determine the region AA as the optimal signal processing parameter. I do.
[0053]
In the first to fourth embodiments of the present invention, the processing parameter optimization is applied to the WIS. However, the present embodiment is not limited to this, and the present embodiment can be applied to the TIS. It is.
[0054]
Next, an embodiment of a device manufacturing method using the method of the embodiment will be described.
[0055]
FIG. 14 shows a flow of manufacturing micro devices (semiconductor chips such as ICs and LSIs, liquid crystal panels, CCDs, thin-film magnetic heads, micromachines, etc.).
[0056]
In step 1 (circuit design), the circuit of the semiconductor device is designed. Step 2 is a process for making a mask on the basis of the circuit pattern design. On the other hand, in step 3 (wafer manufacturing), a wafer is manufactured using a material such as silicon. In step 4 (wafer process), which is called a pre-process, an actual circuit is formed on the wafer by lithography using the prepared mask and wafer. Next, step 5 (assembly) is called a post-process, and is a process of forming a semiconductor chip using the wafer prepared in step 4, and includes processes such as an assembly process (dicing and bonding) and a packaging process (chip encapsulation). including. In step 6 (inspection), inspections such as an operation confirmation test and a durability test of the semiconductor device manufactured in step 5 are performed. Through these steps, a semiconductor device is completed and shipped (step 7).
[0057]
FIG. 15 shows a detailed flow of the wafer process. Step 11 (oxidation) oxidizes the wafer's surface. Step 12 (CVD) forms an insulating film on the wafer surface. Step 13 (electrode formation) forms electrodes on the wafer by vapor deposition. Step 14 (ion implantation) implants ions into the wafer. In step 15 (resist processing), a photosensitive agent is applied to the wafer. Step 16 (exposure) uses the exposure apparatus described above to expose the circuit pattern of the mask onto the wafer by printing. Step 17 (development) develops the exposed wafer. In step 18 (etching), portions other than the developed resist image are removed. Step 19 (resist stripping) removes unnecessary resist after etching. By repeating these steps, multiple circuit patterns are formed on the wafer. By using the manufacturing method of this embodiment, it is possible to manufacture a highly integrated semiconductor device which has been conventionally difficult to manufacture.
[0058]
【The invention's effect】
According to the present invention, in detecting a mark position from a position detection mark signal, there are a wafer process error WIS (Wafer Induced Shift) such as a mark defect and resist coating unevenness, and an error TIS (Tool Induced Shift) of a device factor. In this case, the position of the mark can be detected with high accuracy. In particular, when the present invention is applied to the alignment of a semiconductor exposure apparatus, it is hardly affected by WIS or TIS, the alignment accuracy can be improved, and the yield can be improved in the semiconductor element manufacturing process.
[0059]
The present applicant has already proposed a method of performing signal processing only on an ADUL waveform and performing optimization.
[0060]
However, in the present specification, signal processing is optimized for a plurality of waveforms generated by shaking the WIS or TIS from the simulation waveform matched with the ADUL waveform.
[0061]
That is, in the present specification, the signal processing is optimized also in the vicinity of the waveform acquired by ADUL, so that it can be said that the robustness is more excellent.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram illustrating an embodiment of the present invention.
FIG. 2 is a view schematically showing a semiconductor exposure apparatus according to the present invention.
FIG. 3 is a diagram showing a position detection optical system according to the present invention.
FIG. 4 is a diagram showing a flowchart of a process in the present invention.
FIG. 5 is a view showing an example of occurrence of a resist WIS in the present invention. FIG. 6 is a view showing an example of occurrence of a base WIS in the present invention.
FIG. 7 is a diagram showing another example of occurrence of a base WIS in the present invention.
FIG. 8 is a diagram illustrating a deviation from a true value in the signal processing of the present invention.
FIG. 9 is a view showing the concept of signal processing optimization for explaining the first embodiment of the present invention.
FIG. 10 is a diagram showing a concept of signal processing parameter optimization for explaining a second embodiment of the present invention.
FIG. 11 is a diagram showing signal processing optimization for explaining a third embodiment of the present invention.
FIG. 12 is a diagram showing signal processing optimization for explaining a third embodiment of the present invention.
FIG. 13 is a diagram illustrating optimization of a plurality of signal processing parameters for explaining a fourth embodiment of the present invention.
FIG. 14 is a view showing a manufacturing flow of the semiconductor device.
FIG. 15 is a diagram showing a detailed flow of a wafer process.
[Explanation of symbols]
Reference Signs List 1 semiconductor exposure apparatus 10 reticle 11 reduction projection optical system 12 wafer 13 wafer chuck 14 wafer stage 15 alignment scope 16 alignment signal processing unit 17 central processing unit 18 alignment light source 19 beam splitters 20, 21 lens 22 CCD sensor 30 alignment mark

Claims (10)

An acquisition unit for acquiring first data and a generation unit for generating second data, which are required for processing in the manufacturing apparatus; and a second unit for generating the second data so that the first data and the second data match. Determining the input conditions of the generating means, assigning the input conditions to the determined second data, generating a plurality of data, optimizing the processing based on the plurality of generated data, and A method characterized by feeding back to a manufacturing apparatus and a manufacturing apparatus having the method. An acquiring unit for acquiring a first waveform and a generating unit for generating a second waveform, which are necessary for detecting a mark position in the exposure apparatus, wherein the first acquired waveform matches the second generated waveform The input condition of the second generation means is determined, the input condition is assigned to the determined second generated waveform, a plurality of waveforms are generated, and a signal is generated for the plurality of generated waveforms. A position detection method and apparatus, wherein processing is optimized and a result is fed back to an exposure apparatus, and an exposure method and an exposure apparatus having the position detection method. The position detection method and apparatus, wherein the optimization method determines a signal processing with a minimum sensitivity to the input condition while evaluating a deviation amount (offset) from a true value due to a plurality of signal processings. And an exposure method and an exposure apparatus having the position detection method. The above-described optimization method determines a signal processing parameter having a minimum sensitivity to the input condition while evaluating a deviation amount (offset) from a true value due to a plurality of signal processing parameters. Apparatus, and exposure method and exposure apparatus having the position detection method. A position detection method and apparatus, wherein the generation unit generates the position information based on measurement information obtained by a measurement unit outside the exposure apparatus, and an exposure method and an exposure apparatus having the position detection method. A position detection method and apparatus, wherein the measurement information is surface information of a wafer base and a resist, and an exposure method and an exposure apparatus having the position detection method. A position detection method and apparatus, wherein the input condition stores a plurality of pieces of the measurement information acquired by the measurement means, and shakes the input information within a range determined based on the stored measurement information; Exposure method and exposure apparatus having the method. A position detection method and apparatus, wherein the input condition is a resist WIS, and an exposure method and an exposure apparatus having the position detection method. A position detection method and apparatus, wherein the input condition is a base WIS, and an exposure method and an exposure apparatus having the position detection method. In a tool for analyzing signal processing of waveform data, the tool includes an acquisition unit for acquiring a first real waveform and a generation unit for generating a second pseudo waveform, wherein the first acquisition waveform and the second pseudo waveform are acquired. The input conditions of the second generation unit are assigned so that the waveforms match, the input conditions are assigned to the determined second generated waveform, a plurality of pseudo waveforms are generated, and the plurality of pseudo waveforms are generated. A tool for optimizing signal processing for a data warehouse.

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