JP2004119011A - Synchronous large-scale integrated circuit storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a storage device which can respond to a high-speed CPU system, without making the system complicated by operating a CPU having a high clock rate and a memory with a speed lower than that of the CPU by making it operate at single clock. <P>SOLUTION: This device comprises a cell array means having a plurality of storage cells, a data register means to fetch external input data synchronizing with a clock signal, a register means for input connected to a first terminal of the data register, and a register means controlled so that input data is input into the register means for input in the order, when data are input to the cell array means, and in which a plurality of alternate bits are in a data input state, when the order of data input is not switched. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a synchronous large-scale integrated circuit storage device, and more particularly to a synchronous large-scale integrated circuit storage device suitable for making a memory configured as a large-scale integrated circuit compatible with a high-speed CPU.

Generally, a DRAM used as a main storage device of a computer or the like requires various control signals such as a RAS signal and a CAS signal. Conventionally, these control signals have been created by processing a clock signal supplied as a signal necessary for the operation of the CPU.

On the other hand, in recent years, the improvement of the operation speed of the CPU has been faster than the improvement of the operation speed of the DRAM. For this reason, minicomputers and workstations composed of a CPU and a DRAM take measures such as using a plurality of banks of a main memory composed of a DRAM and performing an interleave operation in order to bridge the speed difference between the two. However, such memory operation complicates memory control and increases system cost.

構成 Further, in order to correspond to the speed of the CPU, a configuration in which the inside of the memory is operated in a pipeline is also conceivable. However, the mere operation of the pipeline causes the memory operation speed to be limited by the data read speed from the core unit, and does not contribute to the improvement of the operation speed. For this reason, it is necessary to take special measures in the memory control system in order to make the memory speed correspond to the CPU speed.

Since the conventional synchronous large-scale integrated circuit storage device is configured as described above, when a memory operation method such as memory interleaving or bank switching is applied to a relatively small system such as a minicomputer or a workstation. However, there is a problem that the system cost is increased or the downsizing is hindered. Also, as the operating speed of the CPU increases to 50 MHz or 100 MHz, it is necessary to construct the memory hierarchical structure more skillfully to make full use of the CPU, which further complicates the memory system. For these reasons, there has been a strong demand for a memory structure and a memory control system to ensure consistency between the operating speed of the CPU and the operating speed of the memory.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the related art, and has as its object to provide a synchronous large-scale integrated circuit storage device that can support a high-speed CPU system without complicating the system. It is in.

The present invention relates to a cell array having a plurality of storage cells, a data register for taking in external input data in synchronization with a clock signal, an input register connected to a first terminal of the data register, and the cell array. Register means for controlling input data to be sequentially input to the input register means when data is input to the means, and register means in which every other bit is placed in a data input state when the order of data input is not switched; Prepare.

As described above, in the synchronous large-scale integrated circuit storage device of the present invention, a memory having an access speed lower than that of the CPU can be operated by a single high-speed clock suitable for the CPU. Is simple, and it is possible to relatively easily cope with an increase in the speed of the CPU.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a synchronous large-scale integrated circuit storage device according to one embodiment of the present invention, and particularly exemplifies a configuration of a 2MX8 synchronous DRAM. As shown in the figure, the cell array is divided into a bank (I) BK1 and a bank (II) BK2, and is connected to a DQ buffer DQBF via a register RG. Signals such as / CS, / RAS, / CAS, / WE, DQM, CKE, and CLK are input to the timing generator TG. For address control, a refresh counter RC, a row buffer RBF, a column counter CC, a precharge logic PLG, and the like are arranged. The banks BK1 and BK2 are selected by the BS signal. Each bank BK1, BK2 is precharged by a bank 1 precharge PR1 and a bank 2 precharge PR2.

FIG. 88 shows the configuration of the DQ write control unit in the configuration of FIG. FIG. 88 shows a coexistence portion of the address A9c and its inverted signal / A9c.

Next, the basic operation of the configuration of FIG. 88 will be described based on the timing charts of FIGS. 89, 90, 91, and 92. Incidentally, FIG. 89 shows a state of interleave bank read in 4-lap mode, FIG. 90 shows a state of interleave bank read in 8-lap mode, and FIG. 91 shows a state of interleave bank write in 8-lap mode. FIG. 92 shows a state of active page random read in the 4-wrap mode.

Now, in the synchronous large-scale integrated circuit storage device, the cell array starts to be activated under the bank active condition of the truth table shown in Table 1.

Next, the column active condition such as read or write is established, and the column system is operated.

(4) In the read mode, a series of data is output after a cycle corresponding to a separately designated latency from the cycle in which the column active condition is set. At this time, a series of data lengths are separately designated as module lengths.

On the other hand, in the write mode, a series of data is input from the cycle in which the column active condition is reached. Here, the latencies “1”, “2”, “3”, and “4” are for the read mode, and the module lengths are “1”, “2”, “4”, “8”, and the page length. . In addition, in the case of a write, there is a case where a series of data starts to be written, and the write latency is “1”, which is the cycle next to the cycle in which the column active condition is reached.

Further, a series of data has different scrambles such as a wrap mode and an interleave mode. Tables 2 to 6 show the order as a column-based activation order. Incidentally, Table 2 shows the page wrap mode, Table 3 shows the 8 wrap mode, Table 4 shows the 8 interleave mode, Table 5 shows the 4 wrap mode, and Table 6 shows the 4 interleave mode.

By the way, the column active condition can enter every even cycle from the cycle in which the column active condition is specified during a series of data access. Also, a part or all of a series of data can be masked. When masking is performed, in the case of reading, DQM is set to “H” level at the rise of the cycle clock immediately before the cycle to be masked. On the other hand, in the case of writing, DQM is set to the “H” level at the rising edge of the clock in the cycle for taking in the data to be masked.

There is also a function that masks the input CLK signal and makes it appear as if the CLK signal is not being input. This is realized by setting the CKE signal to the “L” level at the rising edge of the CLK signal immediately before the CLK signal to be masked. When the access for the designated module length is completed, a column active cycle can be inserted into an arbitrary cycle thereafter.

Here, the operation of the column system and the serial system will be described with reference to the block diagram of FIG. FIG. 2 shows a configuration of a synchronous large-scale integrated circuit storage device according to an embodiment of the present invention, and particularly illustrates the structure of a data line of a 16M synchronous DRAM. As is clear from the figure, a 4-bit write register and a read register are provided for each DQ pin, and these are connected to the DQ buffer via the RWD line. This DQ buffer is a circuit that exchanges data with the cell array unit via the DQ line.

FIG. 84 is a circuit diagram showing an example of a circuit for exchanging data between the DQ buffer and the cell array.

76 and 77 are diagrams for explaining the structure of the DQ buffer. FIG. 76 shows the structure of an 8-bit DRAM having a 2-M bank structure of 1M words. FIG. 77 shows a 4-bit structure of a 2-M bank structure having a 2-M word structure. This is a structure in the case of a DRAM. As shown in FIGS. 76 and 77, there are four DQ buffers at both ends of each cell array, and DQs corresponding to both ends of the activated cell array can be operated among them. The signal for activating the DQ buffer is QACT, which is supplied from a DQ buffer activation signal generation circuit as shown in the circuit diagram of FIG.

The column data is selectively output to the DQ line from the column selected by the column select line. In the column select line, the outputs of the column decoders CSLA to CSLH as shown in the circuit diagram of FIG. Two of them are selected and activated. The column select line selected at this time is selected by scrambling, and the selected column sect line is a CSL selector shown in the circuit diagram of FIG. 58, a CSL selector drive shown in the circuit diagram of FIG. It is controlled through a CSL-related logic circuit shown in the circuit configuration diagram of FIG. 60, a CLS selector tap selection signal generation circuit shown in the circuit configuration diagram of FIG. 61, and the like. Incidentally, the CSL selector tap set is as shown in Table 7, and the CSL selector operation combination is as shown in Table 8.

(5) Regarding the operation of the serial system, the circuits shown in FIGS. 5 and 6 show a column activation detection circuit, FIG. 7 shows a serial basic pulse generation circuit, FIG. 8 shows a serial reset circuit, and FIG. 9 shows a column inactivation detection circuit.

Further, in order to realize a word mask, there are a DQM read register and a DQM write register.

The DQM read register sequentially inputs the DQM state to each register as "1"-"2"-"3"-"4"-"1", latches the data, and outputs the data to the DQMR line at the same time. This DQMR line is input to the output buffer, and when the DQM corresponds to the "H" level, the output buffer is brought into a high impedance state.

The DQM write register operates in the same manner as the write register, and outputs the captured DQM state by scrambling the DQMW line by two bits at a time. Before the data from the DQM write register is output, the DQMW line is once precharged to a write disabled state, the DQMW state is output to the DQMW line, and writing is possible only when the value is at "L" level. It becomes a state.

動作 The above operation is controlled through the configuration shown in the circuit configuration diagrams of FIGS. Incidentally, FIG. 33 is a read operation permission circuit, FIG. 34 is a DQMR gate circuit, FIG. 35 is a high impedance control circuit, FIG. 36 is a DQMR register, FIG. 37 is an RPRM generation circuit, FIG. 38 is a GDM generation circuit, and FIG. FIG. 40 shows a DQM option circuit for write latency.

The structure of the read / write register is as shown in FIGS. Incidentally, FIG. 19 shows a read register gate, FIG. 20 shows an XR register selection signal generation circuit, FIG. 21 shows a used register group detection circuit, FIG. 22 shows a data transfer gating circuit, FIG. 23 shows a read data transfer circuit, and FIG. 25 shows a write register gate, FIG. 26 shows a data transfer selection signal generation circuit, FIG. 27 shows a write data transfer signal generation circuit, and FIG. 28 shows a configuration of a write data register.

Next, the architecture, serial operation, word mask, clock mask, module length-related operation, burst stop, column system, column system address, and column system data access of this embodiment will be described in order.

First, as shown in the explanatory diagram of the serial operation in FIG. 103, the functions necessary for the serial system of the SDRAM can correspond to a clock mask, a column address is inserted at least every two cycles, a word mask is applied, and 100 MHz is applied. Need to work with.

In order to cope with the above operation, it is necessary to be able to access the core unit during a time corresponding to two cycles. However, due to the latency, it is necessary to temporarily store data read from the core unit. Registers are required. This register must be at least 4 bits long to handle the case where the latency is "4". This prevents the new data read from the core during data output from interfering with the data in the register currently being output.

(4) Since the column address can be changed every two cycles, only two bits of the 4-bit data can be serial data from the same column address. For this reason, it is necessary to treat a 4-bit register as a set of two registers each consisting of two bits. That is, a data register having a 2-bit + 2-bit configuration is required.

On the other hand, as shown in the explanatory diagram of the read mode and the write mode in FIG. 104, in the read mode, high-speed operation is performed by pipeline-operating two systems of the system from the CLK signal to the RWD line and the system from the RWD line to the data register. It corresponds to the operation. Therefore, the data register for the read mode needs to interleave a register group of two bits and transfer data to the register from the RWD line every two cycles. Output is performed in order from the first data register.

In the write mode, on the other hand, it is necessary to interleave a register group of two bits and transfer the register data to the RWD line every two cycles. In order to perform a write operation at high speed, a DQM line is used. Before the write data is output to the RWD line, the DQM is set in a write-disabled state, and a write enable signal by the DQM is output simultaneously with the output of the write data. By doing so, the write operation is sped up without delaying the write operation.

The configuration shown in the circuit diagram of FIG. 2 is applied to realize the above operation at high speed.

Next, the configuration of the serial system in the case where the above configuration is adopted will be described with reference to FIG.

(4) A basic signal CP for operating the serial system is prepared, and this CP is stopped in response to the serial system reset and the write latency. Further, the CP is used to select a shift register that operates the data register.

(4) The signal K for controlling the main path of access to the core unit by the output of the shift register is operated such as the signals REG1 and REG2 for selecting the register group in units of 2 bits, and the GDM for selecting the DQM register.

ＣＰ Furthermore, the CP needs to deal with one of the functions, the clock mask. For this reason, the CP is formed from the CLK synchronization signal CPOR with the clock mask applied.

Considering the above, as a serial system architecture, a method shown in the configuration diagrams of FIGS. 3 and 4 can be considered. FIGS. 3 and 4 show the configuration of the serial control lines. That is, in FIG. 3, the basic signals CP are classified by use, such as read, write, and K. On the other hand, in FIG. 4, the CP is not classified according to the application, but only the shift register is classified according to the application. 3 and 4, the required number of shift registers is different, but the number of simultaneously operating shift registers is the same.

Next, basic operations required for each unit will be described with reference to the architecture explanatory diagram of FIG.

各 Each part shown in FIGS. 3 and 4 needs the following operation.

(4) The main path activation signal K moves every two cycles in synchronization with the CP. When the serial system is stopped, K must be stopped. When the serial system is reset, it is initialized to operate from the first CLK signal. The read data register gate GR advances in synchronization with the CP, and when the serial system is reset, the read data register gate GR operates from GRi according to the read latency. This corresponds to keeping the first access from GR1. Also, it is set to be inactive during the write mode. The write register gate GW advances in synchronization with the CP, and is reset so that when the serial system is reset, the next time it starts operating, it starts operating from GW1. Note that, in modes other than the write mode, the GW1 and GW3 are set to the “H” level, and the GW2 and GW4 are set to the “L” level in response to the capture of the first data.

(4) The register group selection signal REG operates every two cycles in synchronization with the CP, and when the serial system is reset, the first register group is set to be in the selected state at the next operation. Some DQM read register gates GDM advance in synchronization with the CP and are fixed at the “H” level or the “L” level depending on the read latency except in the read mode. On the other hand, during the read mode, the operation is the same as that of the data register gate GR.

Next, the basic operation of the read corresponding unit will be described with reference to the architecture explanatory diagram of FIG.

(4) When data is read from the core unit, the data must be transferred to the read data register in response to the read data being read from the core unit. After the normal data has been transferred to the read data register, the read register gate must be opened. Therefore, the data transfer signal XR is activated after data is read out by K, and GR1 and GR3 become operable after XR is activated.

In consideration of the above, the configuration of the serial control unit as shown in FIG. 4 is applied.

Next, the basic operation of the read / write mode and the address fetch will be described with reference to FIGS. Incidentally, FIG. 105 describes the read / write mode capture, address capture, and counter relationship, FIG. 106 describes the address signals used in each circuit at the time of tap setting, and FIG. 107 illustrates the use of each part. / WE.

Both the mode and the address are taken in by the first CLK signal of the column access cycle, so that K can be switched inactive, that is, switched between "L" levels. This is because the mode and address must be switched only while the column system is in the inactive state.

(4) The head address is set in the output preparation unit of the address counter when the / R signal becomes "H" level except when the module length is the page length. Incidentally, the / R signal is a signal which becomes "H" level in the first cycle of the column access cycle and becomes "L" level when K transitions to "H" level. On the other hand, when the module length is the page length, the leading address is set in the output section of the counter at the falling edge of K.

{Circle around (2)} When the module length is other than the page length, the output section of the counter is opened only during the first K “L” level following the column access cycle, and is closed otherwise. On the other hand, when the module length is the page length, the output unit of the counter counts up by the count-up signal.

Here, the basic operation for resetting or stopping the serial system will be described with reference to FIG. FIG. 108 explains the serial system enable.

(4) In the read mode, when the column access cycle does not enter after the cycle corresponding to the latency after the last data output cycle, the serial system is reset, and when the next column access cycle enters, the serial operation becomes possible.

In the write mode, stop the serial system after the last data input cycle, and enable the serial system when the next column access cycle starts.

動作 The above operation is performed through the configuration as shown in FIGS. 42 shows the configuration of the register group detection circuit, FIGS. 43 and 44 show the configuration of the module length detection procedure selection circuit, FIG. 45 shows the configuration of the module length detection circuit, and FIG. 46 shows the configuration of the read module reset circuit. 47 shows the configuration of the write module stop circuit, FIG. 48 shows the configuration of the module length detection circuit, and FIG. 49 shows the configuration of the module number counter circuit.

(4) If the write latency is "1", the serial system is stopped for one cycle of the first cycle only when entering the write mode from a mode other than the write mode. Such an operation is performed through a write latency detection circuit as shown in the circuit diagram of FIG.

Next, the mode detection required for the above operation will be described with reference to the explanatory diagram of FIG.

(4) The reason why the read mode or the write mode is detected is to operate only the circuits required in each mode. For this purpose, a read detection READ and a write detection WRITE are used. These signals are generated through the read mode detection circuit of FIG. 10 and the write mode detection circuit of FIG.

カ ラ ム Column cycle detection and address mode fetch in the case of write latency “1” will be described with reference to the explanatory diagrams of FIGS.

(4) When the column access cycle is entered when the write latency is “1”, detecting this is different from the case where the write latency is “0”. This is because the cycle for inputting the address and the mode and the actually used cycle are shifted by one cycle because the control as described above is performed. For this reason, it is necessary to perform the detection in different cases, such as when the mode changes. By the way, when the latency is “0”, the above-described case division is unnecessary.

{That is, when the write latency is “0”, it is controlled by the tap address mode capture control circuit of FIG. On the other hand, when the write latency is “1”, the control is performed under the cycle detection in the column cycle detection circuit of FIG.

The first shift register involved in the serial operation has the configuration as shown in the circuit diagram of FIG. 15, and the second shift register has the configuration as shown in the circuit diagram of FIG. A configuration as shown in FIG. 17 is applied to register group selection, and a column basic signal is generated through a configuration as shown in FIG.

Also, regarding the serial operation, an initial stage circuit as shown in FIG. 29, an address buffer circuit as shown in FIG. 30, a / WE buffer circuit as shown in FIG. 31, and an address mode fetch signal generation circuit as shown in FIG. Is used.

Next, the word mask operation will be described with reference to the explanatory diagrams of FIGS. FIG. 112 explains a word mask for the case where the latency is "4" or "3" in the case of the DQM read, and FIG. 113 shows the DQM high impedance in the case where the latency is "2". 9 illustrates a word mask for a corresponding case.

{First, in the read mode, the latency of the word mask is “1” and does not depend on the read latency. Also, it is considered optimal to perform masking by outputting high impedance data to an output buffer associated with the read data register. Incidentally, as the read data register, a configuration as shown in the circuit diagram of FIG. 24 is applicable.

Therefore, each output DQMRi of the DQM read register shown in FIGS. 35 and 36 may be input to each read register as shown in FIG.

Since the output of the DQM read register is a signal for controlling the high impedance and low impedance states of the output, the control of the DQM read register must be changed according to the read latency. This is because the output must be high impedance until the first access. These controls are performed through the configurations shown in FIGS.

Next, based on the explanatory diagram of FIG. 114, a description will be given of the high impedance support after the module.

場合 If the next column cycle does not enter for more than the module length from the column activation cycle, a high impedance will always occur in the output. However, the serial circuits must continue to work and have to create a high impedance state regardless of the value of DQM. For this reason, it is necessary to make the impedance high with the CLK signal of the module length + latency corresponding to each read latency. The release of the high impedance is also performed depending on the latency. This is performed by the circuits shown in FIGS.

{DQM write study will be described based on the explanatory diagram of FIG.

ワ ー ド The word mask in the write mode is implemented by the method described above. This is performed through the circuits shown in FIGS. On the other hand, when the write latency is “1”, the processing is performed through the circuit of FIG.

Next, the clock mask will be described based on the explanatory diagram of FIG.

This is to stop the operation in the cycle next to the cycle in which the CKE signal is at the “L” level. In order to realize this, it is controlled whether or not to generate a CPOR according to the state of the CKE signal captured one cycle before. In addition, the state of the CKE signal captured one cycle before is input to each function detector other than the CP, and when the mask is applied, the function detector is not set. Incidentally, the CPOR is generated through a short-period basic signal generation circuit as shown in the circuit diagram of FIG.

Next, the operation related to the module length will be described based on the explanatory diagrams of FIGS. Incidentally, FIG. 117 is a module length detection operation, FIG. 118 is a module operation, a module reset release operation, FIG. 119 is a module length detection reset operation, FIG. 120 is a summary of each module operation at the time of read and write operations, and FIG. FIG. 122 illustrates a state reset operation, and FIG. 122 illustrates a column active cycle detection operation and an operation corresponding to a module length of “1”.

サ イ ク ル In the read mode, a cycle in which data corresponding to the module length is output, and in the write mode, a cycle in which data corresponding to the module length is input can be regarded as the end of the module length.

Based on the above premise, in the read mode, the final data access is from GR2 or GR4 due to the configuration of the register. Further, as described above, the register group for outputting the final data controls the read register, and therefore is determined only by the module length regardless of the read latency.

This is also true in the light mode.

{That is, if it is known whether REG1 or REG2 is at the "L" level in the column access cycle, the register in which the final data access is performed can be determined. Since the module length starts to be counted every column access cycle, a reset is applied in the column access cycle. Also, the page length can be handled in the same way as when the module length is "8" by operating a counter described later. In order to deal with these, the circuits of FIGS. 42 to 49 are applied.

Next, the burst stop will be described based on the explanatory diagram of FIG.

The burst stop operation is performed by disabling the serial system in the cycle following the input of the burst stop command during the burst cycle. Since such a burst stop operation terminates a burst in an arbitrary cycle of a burst cycle, a burst stop command detection circuit as shown in the circuit diagram of FIG. 50 is applied.

Here, the operation of the column system will be described with reference to the explanatory diagram of FIG.

に は A column bank switching circuit as shown in the circuit diagram of FIG. 51 is applied to the column system. The whole is controlled by K, and the K corresponding to the bank which is activated in the column access cycle is activated.

However, K that is not decoded by the bank designation signal is used for a circuit that is not unique to each bank.

The column system has a configuration for supporting scrambling, which is one of the features of the SDRAM, that is, addressing mode. In response to the scrambling, how the lower address changes, the column select line, Tables 2 to 6 show how to activate the DQ buffer and the data register.

部分 In each table, the sections demarcated by arrows correspond to 2 CLK signals in one lower K cycle. The register scramble indicates which transfer signal is selected when data is transferred to or from the data register shown in FIG. 23 or FIG. In each table, lower addresses A0, A1, and A2 are described. Addresses A3 and higher are decoded by a column decoder shown in the circuit diagram of FIG. This column decoder is decoded by the column partial decoder shown in the circuit diagram of FIG. Further, in order to realize the movement of the column select line shown in Tables 2 to 6, a configuration as shown in the circuit diagrams of FIGS. 56 to 61 is applied. Incidentally, FIG. 56 shows a spare CSL, and FIG. 57 shows a CSL driver.

Next, the column address will be described with reference to the explanatory diagram of FIG.

For column addresses, address generation and spare circuit operation are performed through the configurations shown in FIGS. 62 is an address change basic pulse generation circuit, FIG. 63 is a counter driver circuit, FIG. 64 is a spare selection signal generation circuit, FIG. 65 is a partial decode S / N discrimination result capture signal generation circuit, and FIG. 66 is an address counter circuit. 67 to 72 are address counter circuits, FIG. 73 is a spare circuit, FIG. 74 is an S / N discriminating circuit for A1c = "1" side, and FIG. 75 is an S / N discriminating circuit for A1c = "0" side. .

First, the counter generates a column address that generates a partial decode signal that changes every eight cycles in the page mode, and the counter does not need to count up except in the page mode, so that it is not necessary to transmit the carry. For this reason, in the page mode, the head address is output and set to the counter using CLSETP in the column access cycle, and the operation starts at the eighth cycle from the fifth cycle from the column access cycle during the burst cycle.

The count-up cycle in the page mode burst cycle is detected by the circuit of FIG. 62, and the counter is directly operated by the circuit of FIG. The counters are connected as shown in FIG. 66, and the respective counters are configured by connections as shown in FIGS. 67 to 72, and perform the intended address counting operation.

The column spare performs the operation of the address counter described above in the page mode in order to perform a spare-normal determination without causing a delay due to the spare, and compares the spare address with the next output address. The address is determined before the address is actually used. By the way, in the circuit of FIG. 64, in the page mode, the column decoder corresponding to the head address and the next column decoder are activated, so that the determination result corresponding to which decoder is used is determined. Things.

Next, switching of the partial decode signal and taking in of the S / N determination result at the column address will be described with reference to the explanatory diagram of FIG.

The spare / normal discrimination signal and the column partial decode signal are changed every eight cycles from the column access cycle. The spare / normal discriminating circuit is connected to other circuits as shown in FIG. 73, and has a circuit configuration as shown in FIGS. Since the column decoder is not changed during the burst cycle except in the page mode, the switching signal shown in FIG. 65 remains at a constant value.

Next, the switching operation of the 4-bit / 8-bit configuration for column data access will be described with reference to FIGS. 127, 128, and 129. Incidentally, FIG. 127 shows the change of X4 and X8 and the decoding of A9c at X4, FIG. 128 shows the correspondence for X4 page, and FIG. 129 shows the QACT control and A9c control.

The configuration of FIG. 76 is for 8-bit data, and the configuration of FIG. 77 is for 4-bit addresses and output numbers corresponding to each cell array. In order to switch between X8 and X4, as shown in Table 9, the connection between the RWD line and the DQ buffer may be changed.

First, when changing from X8 to X4, the signal QACT for activating the DQ buffer is decoded and performed. As shown in Table 10, when the page length is X4, the cell array to be accessed may extend over two. . However, at this time, QACT0 and QACT3 are always activated.

$ ACT0 always exists in the cell array to be accessed from now on, and QACT3 always exists in the cell array to which access has been made so far. Therefore, this can be dealt with only by latching A9c of the old access array and the new access array and detecting the timing of performing access across the two cell arrays. These operations are executed through the circuits shown in FIGS. Incidentally, FIGS. 79, 80, and 81 show a QACT selection circuit, FIG. 82 shows a counter circuit for A9, and FIG. 83 shows a counter drive circuit for A9, respectively.

84 shows a specific circuit of the DQ buffer, FIG. 85 shows a DQ line read control circuit, FIG. 86 shows a DQ line write control circuit, FIG. 87 shows a DQ line read control circuit in an A9c // A9c coexistence section. Reference numeral 88 denotes a DQ write control circuit in the A9c // A9c coexisting unit.

Incidentally, the bank switching of the column system is executed by the circuit of FIG. 51, and the column system is selected through the circuit of FIG. When KI / KII is used as the reverse phase signal, the circuit shown in FIG. 53 is applied.

The detailed operation of the embodiment of the present invention is as shown in the timing charts of FIGS. Incidentally, FIG. 93 shows the case of the latency “2” and the module length “4”, FIG. 94 shows the case of the latency “3” and the module length “4”, and FIG. 95 shows the case of the latency “4” and the module length “4”. CLK, / CAS, DQM, CLKIN, CPOR, CP, / SF11, / SF12, / DF13, / SF14, / SF21, / SF22, / SF23, / SF24, REG1, REG2, K, CFP, RLL, WMR1, WMR2, HiZ, / RPRMij, GDM1, GDM2, GDM3, GDM4, DQMR1, DQMR2, DQMR3, DQMR4, GR1, GR2, GR3, GR4, R, CLSET, and DQ, respectively. FIG. 96 shows a case where the latency is “2”, module length “4”, and write latency “0”. FIG. 97 shows a case where the latency is “3”, module length “4”, and write latency “0”. When the latency is “4”, the module length is “4”, and the write latency is “0”, the latency CLK, / CAS, / WE, COLACT, / NONCLA, CLKIN, CPOR, CP, READ, WRITE, / R, CLSET, / SF11, / SF12, / DF13, / SF14, / SF21, / SF22, / SF23, / SF24, REG1, REG2, K, / PERM, GR1, GR2, GR3, GR4, GW1, GW2, GW3, GW4, REG110, REG110, REG101, REG210, REG201, XR110, XR101, XR 10, XR201, / XW, RWDin, illustrates DQn, CFP, RiL, WMRi, / RMR, MRRST, SRST, HiZ, respectively. FIG. 99 shows CLK, K, KR, PLS1, PLS2, PLS3, PLS4, CNTF, / CNTB, CNTP, / PX, / PY, X, Y, / in the case of page mode (X4) and tap = 9. YCHAN, ACi, SA-SD, SE-SH, Kp, Kp ', SAB, SBC, SCD, SDE, SEF, SFG, SGH, SHA, Y A / B / C, / CDRVA, / CDRVB, / CDRVC, / It shows CDRVD, / CDRVE, / CDRVF, / CDRVG, / CDRVH, CNT9, ACL9, / QA9C, A1Gi, QACT00, QACT01, QACT02, QACT03, QACT10, QACT11, QACT12, and QACT13.

Through the above embodiments, in the present invention,
(1) It has a basic signal synchronized with the CKE signal related to the mask according to the state of the CKE signal, operates in synchronization with this basic signal, and after a predetermined number of accesses have been made, or the stop signal is A synchronous large-scale integrated circuit storage device accessed by a second signal that stops when input is provided.

(2) Further, in the configuration of (1), a configuration in which an initial operation is achieved by a shift register accessed by a second signal is proposed.

(3) Further, a configuration is proposed in which the shift register having the configuration of (2) is a 4-bit shift register, and the column meter is activated by an output of a specific shift register.

(4) Further, a configuration in which two sets are provided as the shift register having the configuration of (2) is proposed.

(5) Then, in the configuration of (2), a configuration in which the initial state changes according to the read latency is proposed.

(6) A synchronous large-scale integrated circuit storage device having a shift register which takes in external input data in synchronization with a CLK signal, wherein a 4-bit input register is provided for each DQ pin, and input data is sequentially stored. In order to be input to the input register, a configuration is proposed in which the register is controlled at the time of data input and a register of a total of two bits is provided in a data input state when the data input is not sequentially switched.

(7) The state of DQM is sequentially taken into a 4-bit register, and the taken-in data is sequentially output. The outputted data is inputted to a specific 4-bit register, respectively, and when the data from DQM to be inputted is in the first state. The four-bit register proposes a configuration in which a signal for setting the output circuit to a high impedance state is output in synchronization with the second signal having the configuration (1).

(8) A data register which takes in the DQM sequentially into the 4-bit register in synchronization with the second signal only in the write mode, and outputs the data of the data register by scrambling the DQMW line every two cycles every two bits. Then, a configuration in which the DQMW line is precharged at a predetermined cycle interval is proposed.

(9) Propose a configuration in which when the predetermined access length is "1", the second and fourth registers of the 4-bit DQM write register are fixed to the same state as when the mask data is fetched. I do.

(10) There is a data register for sequentially taking in the DQM into the 4-bit register in synchronization with the second signal in the read mode, and the data of this data register is sequentially output to the DQMW line. Is proposed to fix to a state where is in a high impedance state.

(11) A configuration is proposed in which when the predetermined access length is "1", the second and fourth outputs of the 4-bit DQM read register are fixed to the mask data output state.

(12) In the configuration of (1), a configuration is proposed in which a stop signal is output after performing a predetermined number of accesses after both banks are precharged.

(13) Further, the present invention proposes a configuration in which the stop signal is output during the first cycle from the non-write state to the write mode when the write latency is "1".

(14) A configuration is proposed in which a predetermined number of cycles is counted by using a signal for selecting a 2-bit unit by interleaving a total of 4-bit registers of 2 bits + 2 bits.

(15) The present invention proposes a configuration in which, when performing serial access between a plurality of cell arrays, when accessing a serially accessed cell array, a plurality of cell arrays may be accessed simultaneously.

(16) Also, in the configuration of (15), a configuration is proposed in which, when accessing a plurality of cell arrays simultaneously, half the number of DQ buffers when accessing a single cell array is activated in each cell array. I do.

(17) Then, in the configuration of (1), a configuration is proposed in which the second signal is divided for each of a plurality of applications, and is controlled separately, for example, in CPK, CPW, CPR, and the like in FIG.

As described above, the synchronous large-scale integrated circuit storage device of the present invention includes a timing generator that divides a cell array into two banks and generates an access signal synchronized with a masked CLK signal, and includes a DQ buffer and a register. , The column system of the cell array of the two banks is pipeline-operated, thereby allowing access to the core unit once every two clocks. Then, in the read mode, the data read from the core unit is interleaved and transferred to the 4-bit serial register by two bits at a time, and the data transferred to the serial register is serially output. In the write mode, data is sequentially taken into the serial register, and the taken data is interleaved every two bits and written into the core unit.

As a result, a CPU having a high clock speed and a memory having a lower speed than the CPU can be operated by a single clock, and a synchronous large-scale integrated circuit storage device capable of supporting a high-speed CPU system without complicating the system. Can be realized.

FIG. 2 is a block diagram of a storage device according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating the structure of a data line of a 16M synchronous DRAM. FIG. 3 is a circuit diagram illustrating an example of a configuration of a serial control line. FIG. 9 is a circuit diagram of another example of a configuration of a serial control line. FIG. 3 is a partial circuit configuration diagram of a column activation detection circuit. FIG. 10 is another partial circuit configuration diagram of the column activation detection circuit. FIG. 3 is a circuit diagram of a serial basic pulse generation circuit. It is a circuit diagram of a serial system reset circuit. FIG. 3 is a circuit diagram of a column inactivation detection circuit. FIG. 3 is a circuit diagram of a read mode detection circuit. FIG. 3 is a circuit diagram of a write mode detection circuit. FIG. 3 is a circuit diagram of a write latency detection circuit. It is a circuit diagram of a tap address mode capture control circuit. FIG. 3 is a circuit diagram of a column cycle detection circuit. FIG. 3 is a circuit diagram of a first shift register. FIG. 9 is a circuit diagram of a second shift register. It is a circuit diagram of register group selection. FIG. 3 is a circuit diagram of a column-based basic signal generation circuit. FIG. 3 is a circuit diagram of a read register gate. FIG. 3 is a circuit diagram of an XR register selection signal generation circuit. It is a circuit diagram of a used register group detection circuit. FIG. 3 is a circuit diagram of a data transfer gating circuit. FIG. 3 is a circuit diagram of a read data transfer circuit. FIG. 3 is a circuit diagram of a read data register. FIG. 3 is a circuit diagram of a write register gate. FIG. 3 is a circuit diagram of a data transfer selection signal generation circuit. FIG. 3 is a circuit diagram of a write data transfer signal generation circuit. FIG. 3 is a circuit diagram of a write data register. FIG. 3 is a circuit diagram of a serial first stage circuit. FIG. 3 is a circuit diagram of an address buffer circuit. FIG. 3 is a circuit diagram of a / WE buffer circuit. FIG. 3 is a circuit diagram of an address mode capture signal generation circuit. FIG. 3 is a circuit diagram of a read operation permission circuit. FIG. 3 is a circuit diagram of a DQMR gate circuit. It is a circuit diagram of a high impedance control circuit. FIG. 3 is a circuit diagram of a DQMR register. It is a circuit diagram of a RPRM generation circuit. FIG. 3 is a circuit diagram of a GDM generation circuit. FIG. 3 is a circuit diagram of a DQM write register. It is a circuit diagram of a DQM option circuit corresponding to write latency. It is a circuit diagram of a short cycle basic signal generation circuit. It is a circuit diagram of a register group detection circuit. It is a circuit diagram of a partial configuration of a module length detection procedure selection circuit. FIG. 14 is a circuit diagram of another partial configuration of the module length detection procedure selection circuit. It is a circuit diagram of a module length detection circuit. It is a circuit diagram of a read module reset circuit. It is a circuit diagram of a light module stop circuit. It is a circuit diagram of a module length detection circuit. It is a circuit diagram of a module number counter circuit. It is a circuit diagram of a burst stop command detection circuit. FIG. 9 is a circuit diagram of column-based bank switching. It is a circuit diagram of selection of a column system. It is a circuit diagram in case KI / KII is used as a reverse phase signal. FIG. 3 is a circuit configuration diagram of a column decoder. FIG. 3 is a circuit diagram of a column partial decoder. It is a circuit diagram of a spare CSL. FIG. 3 is a circuit diagram of a CSL driver. FIG. 3 is a circuit configuration diagram of a CSL selector. FIG. 3 is a circuit configuration diagram of a CSL selector drive. FIG. 3 is a circuit configuration diagram of a CSL-related logic circuit. FIG. 3 is a circuit configuration diagram of a CLS selector tap selection signal generation circuit. FIG. 3 is a circuit diagram of an address change basic pulse generation circuit. FIG. 3 is a circuit diagram of a counter driver circuit. FIG. 3 is a circuit diagram of a spare selection signal generation circuit. FIG. 9 is a circuit diagram of a partial decode S / N determination result capturing signal generation circuit. FIG. 3 is a circuit diagram of a first portion of the address counter circuit. FIG. 4 is a circuit diagram of a second part of the address counter circuit. FIG. 9 is a circuit diagram of a third part of the address counter circuit. FIG. 9 is a circuit diagram of a fourth part of the address counter circuit. FIG. 14 is a circuit diagram of a fifth part of the address counter circuit. FIG. 14 is a circuit diagram of a sixth part of the address counter circuit. FIG. 14 is a circuit diagram of a seventh part of the address counter circuit. It is a circuit diagram of a spare circuit. FIG. 3 is a circuit diagram of an S / N determination circuit on the A1c = “1” side. FIG. 4 is a circuit diagram of an S / N determination circuit on the A1c = “0” side. FIG. 4 is an explanatory diagram of the structure of a DQ buffer in the case of an 8-bit DRAM with a 2-bank configuration of 1M words. FIG. 3 is an explanatory diagram of the structure of a DQ buffer in the case of a 4-bit DRAM having a 2-bank configuration of 2M words. FIG. 3 is a circuit configuration diagram of a DQ buffer activation signal generation circuit. QACT selection circuit. QACT selection circuit. QACT selection circuit. A9 counter circuit. Counter drive circuit for A9. FIG. 3 is a circuit configuration diagram illustrating an example of a circuit that exchanges data between a DQ buffer and a cell array. DQ line read control circuit. DQ line write control circuit. DQ line read control circuit in the A9c, / A9c coexistence section. FIG. 2 is a circuit diagram showing a configuration of a DQ write control unit in the configuration of FIG. It is a timing chart which shows the state of the interleave bank read of 4-lap mode. It is a timing chart which shows the state of the interleave bank read of 8-lap mode. It is a timing chart which shows the state of the interleave bank write of 8-lap mode. 5 is a timing chart showing a state of active page random read in 4-lap mode. 5 is a timing chart for explaining a detailed operation of the embodiment of the present invention. 5 is a timing chart for explaining a detailed operation of the embodiment of the present invention. 5 is a timing chart for explaining a detailed operation of the embodiment of the present invention. 5 is a timing chart for explaining a detailed operation of the embodiment of the present invention. 5 is a timing chart for explaining a detailed operation of the embodiment of the present invention. 5 is a timing chart for explaining a detailed operation of the embodiment of the present invention. 5 is a timing chart for explaining a detailed operation of the embodiment of the present invention. FIG. 2 is an explanatory diagram of an architecture for studying a serial system configuration. It is an explanatory view of an architecture. FIG. 5 is an explanatory diagram of the architecture of the basic operation of the read corresponding unit. FIG. 4 is an explanatory diagram of a serial operation. FIG. 4 is an explanatory diagram of a read mode and a write mode. FIG. 4 is an explanatory diagram of a read / write mode, an address fetch, and a counter relationship in a basic operation of a read / write mode and an address fetch. FIG. 9 is an explanatory diagram of an address signal used in each circuit at the time of tap setting in a basic operation of read / write mode and address fetch. FIG. 5 is an explanatory diagram of / WE used in each part in a basic operation of read / write mode and address fetch. FIG. 9 is an explanatory diagram of serial system enable in a basic operation when resetting or stopping a serial system. It is explanatory drawing of mode detection. FIG. 4 is an explanatory diagram of column cycle detection. FIG. 4 is an explanatory diagram of address mode capture. FIG. 4 is an explanatory diagram of a word mask operation corresponding to DQM read. FIG. 11 is an explanatory diagram of a word mask operation in a case of supporting DQM high impedance. It is explanatory drawing about the high impedance correspondence after a module. It is explanatory drawing about DQM write study. FIG. 4 is an explanatory diagram of a clock mask. It is explanatory drawing of a module length detection operation. It is explanatory drawing of a module operation | movement and a module reset release operation | movement. It is explanatory drawing of a module length detection reset operation. FIG. 7 is an explanatory diagram of a summary of respective module operations at the time of read and write operations. It is explanatory drawing of a module state reset operation. FIG. 11 is an explanatory diagram of a column active cycle detection operation and an operation corresponding to a module length of “1”. FIG. 4 is an explanatory diagram of a burst stop. FIG. 4 is an explanatory diagram of an operation of a column system. FIG. 4 is an explanatory diagram of a column address. FIG. 9 is an explanatory diagram of switching of a partial decode signal and capturing of an S / N determination result at a column address. FIG. 10 is an explanatory diagram of a change of X4 and X8 and decoding of A9c at X4 in a switching operation of a 4-bit / 8-bit configuration of column data access. FIG. 10 is an explanatory diagram of the switching operation of the 4-bit / 8-bit configuration of the column data access, corresponding to the X4 page. FIG. 9 is an explanatory diagram of a QACT control and an A9c control in a switching operation of a 4-bit / 8-bit configuration for column data access.

100 is a timing chart for explaining the detailed operation of FIG. 93.

Explanation of reference numerals

BK1 Bank I
BK2 Bank II
RG register TG Timing generator DQBF DQ buffer

Claims (1)

Cell array means having a plurality of storage cells;
Data register means for capturing external input data in synchronization with a clock signal;
Input register means connected to a first terminal of the data register;
When data is input to the cell array means, input data is controlled so as to be sequentially input to the input register means. When the order of data input is not switched, a register means in which every other bit is placed in a data input state. ,
A synchronous large-scale integrated circuit storage device comprising:

Images