JP2004117707A - Active matrix substrate, its manufacturing method, and liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a constitution by which simple measures can be taken against static electricity in an active matrix substrate having two wiring systems. <P>SOLUTION: A plurality of scanning signal lines, a plurality of first auxiliary capacitance wiring patterns and a plurality of second auxiliary capacitance wiring patterns are extended in a first direction. A plurality of display signal lines, a first auxiliary capacitance main line and a second auxiliary capacitance main line are extended in a second direction. The plurality of scanning lines are individually extended to the outside of a terminal region, and at least one of the first and the second auxiliary capacitance main lines is extended to the outside of the terminal region. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an active matrix substrate, a method of manufacturing the same, and a liquid crystal display device, and more particularly to an active matrix substrate suitably used in a liquid crystal display device used as a monitor for a personal computer, a television system, a display panel of a portable device, and the like. And its manufacturing method.
[0002]
[Prior art]
Liquid crystal display devices are flat display devices having excellent features such as high definition, thinness, light weight, and low power consumption. In recent years, the display performance, the production capacity, and the price competitiveness with other display devices have been improved. As a result, the market scale is rapidly expanding.
[0003]
A liquid crystal display device has, for example, a structure in which a liquid crystal layer as a display medium layer is sandwiched between a pair of substrates provided to face each other. One substrate (called an “active matrix substrate”) of a so-called active matrix type liquid crystal display device having a switching element for each pixel includes a display signal line (data line or source line), a scanning line (gate line), and a display. A storage capacitor line for forming a storage capacitor (CS) provided for holding a signal voltage (drain voltage) is formed. On this substrate, switching elements driven by gate signals supplied from the scanning line gate lines and pixel electrodes connected to the switching elements are arranged in a matrix. In addition, a common electrode and the like are provided on the other substrate (counter substrate). In a liquid crystal display device, the light modulation state of the liquid crystal layer is controlled by applying a predetermined voltage to the liquid crystal layer using the pixel electrode and the common electrode. As described above, it is possible to display an image by controlling the light modulation state of the liquid crystal layer.
[0004]
As a liquid crystal display device, an active matrix type liquid crystal display device employing a dot inversion driving method is known. The dot inversion driving method is a driving method in which the polarity of an image signal applied to adjacent pixels is inverted.
[0005]
For example, in a liquid crystal display device of a dot inversion driving method described in Patent Document 1, a common electrode provided to face a pixel electrode is divided into two groups. , Different signals having opposite polarities (common voltage) are supplied. In addition, auxiliary capacitance wirings (hereinafter, referred to as “CS wirings”) that form auxiliary capacitances provided for the respective pixels are also divided into two groups similarly to the common electrode. Different signals (a storage capacitor opposite voltage) are input. More specifically, the CS wirings are divided into an odd-numbered CS wiring group and an even-numbered CS wiring group, and the CS wirings of each group have opposite polarities whose polarity is inverted every predetermined period. A phase signal is input.
[0006]
In a manufacturing process of an active matrix type liquid crystal display device, an active matrix capable of taking a countermeasure against static electricity in order to prevent a switching element (typically, a thin film transistor, hereinafter referred to as a “TFT”) from being broken or disconnected due to static electricity. It is important to design the substrate.
[0007]
A typical example of conventional static electricity countermeasures uses a conductive layer (also referred to as “gate metal”) for forming a scanning line (and a gate electrode of the TFT) on an active matrix substrate having a bottom gate type TFT. By forming a short ring around the panel and connecting as many of the circuit elements (including TFTs and wirings) formed in the subsequent process as possible to the short ring, these circuit elements are brought to the same potential. Is to keep. It is preferable that all of the scanning lines and the CS wiring existing in the display area (also referred to as “active area”) be connected to the short ring.
[0008]
A terminal for supplying a scanning signal to the scanning line is formed in a terminal region outside the display region, and a short ring is formed near the outside of the terminal region, so that each scanning line extends to outside the terminal region. Thus, each scanning line can be directly connected to the short ring.
[0009]
On the other hand, the same signal (typically, the same as the voltage applied to the common electrode) is conventionally supplied to a plurality of CS wirings provided in parallel with the scanning lines. On the side (gate signal non-input side) opposite to the gate signal input side (the side on which the terminal region is provided), all CS wirings were connected to the CS trunk, and this CS trunk was connected to the short ring. .
[0010]
[Patent Document 1]
JP-A-11-119193
[0011]
[Problems to be solved by the invention]
However, as described in Patent Document 1, when the CS wiring is divided into two groups and different signals are supplied to each group (that is, when the CS wiring is driven by two systems), Since the two groups of CS wirings are alternately arranged, it is not possible to connect two groups of CS wirings formed of the same conductive layer to one CS main line for each system on the gate signal non-input side. It is possible.
[0012]
Therefore, since the number of locations where the CS wiring is connected to the short ring increases, there arise problems such as an increase in the wiring density of the terminal region and an increase in the number of wirings exposed by cutting the short ring. Patent Document 1 does not mention measures against static electricity in CS wiring.
[0013]
The present invention has been made in view of the above points, and a main object of the present invention is to provide a simple countermeasure against static electricity in an active matrix substrate having two lines of wiring, such as the active matrix substrate having two lines of CS wiring. It is to provide a configuration which can be taken.
[0014]
[Means for Solving the Problems]
An active matrix substrate according to the present invention includes: a substrate; a display region defined by a plurality of pixel regions arranged on the substrate along a first direction and a second direction intersecting the first direction; A plurality of first terminals for supplying a predetermined signal to the plurality of pixel regions; a plurality of terminal regions arranged around the region and defined by a plurality of terminals to which signals for driving the plurality of pixel regions are input; A wiring, a plurality of second wirings, a plurality of third wirings, and a plurality of fourth wirings; a fifth wiring electrically connected to the plurality of second wirings; and an electrical connection to the plurality of third wirings An active matrix substrate having a plurality of sixth wirings, wherein the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings extend in the first direction; Wiring, the fifth wiring and the The sixth wiring extends in parallel with the second direction, and each of the plurality of first wirings extends to the outside of the terminal region, and at least one of the fifth wiring and the sixth wiring is provided. One is extended to the outside of the terminal area.
[0015]
In one embodiment, each of the plurality of pixel regions includes at least one switching element, a pixel electrode to which a display signal is supplied via the at least one switching element, at least one auxiliary capacitance electrode, and A plurality of scanning lines connected to the at least one switching element, each of the plurality of first wirings having an auxiliary capacitance counter electrode which is opposed to one of the auxiliary capacitance electrodes via an insulating layer to constitute an auxiliary capacitance; Wherein the plurality of fourth wirings are a plurality of display signal lines each connected to the at least one switching element, and the plurality of second wirings and the plurality of third wirings are each This is an auxiliary capacitance line connected to the auxiliary capacitance counter electrode.
[0016]
The method for manufacturing an active matrix substrate according to the present invention is a method for manufacturing an active matrix substrate having the above configuration, wherein (a) a step of preparing a mother substrate; and (b) a display area on the mother substrate. A short ring disposed outside the display region and the terminal region, wherein each of the plurality of first wirings and at least one of the fifth wiring and the sixth wiring are Forming a connected short ring; and (c) between the short ring and the terminal region, each of the plurality of first wires, and the fifth wire and the fifth wire connected to the short ring. Cutting at least one of the sixth wirings.
[0017]
In a preferred embodiment, the short ring is formed in the same step as the plurality of first wires, the plurality of second wires, the plurality of third wires, and the sixth wire.
[0018]
An active matrix substrate according to a preferred embodiment of the present invention is a display region defined by a substrate and a plurality of pixel regions arranged on the substrate along a first direction and a second direction intersecting the first direction. And a terminal area defined by a plurality of terminals arranged around the display area and to which signals for driving the plurality of pixel areas are input. Each of the plurality of pixel areas has at least one One switching element, a pixel electrode to which a display signal is supplied via the at least one switching element, a first storage capacitor electrode, and a second storage capacitor electrode, facing the first storage capacitor electrode via an insulating layer. A first auxiliary capacitance opposing electrode forming a first auxiliary capacitance, and a second auxiliary capacitance opposing electrode opposing the second auxiliary capacitance electrode via an insulating layer to form a second auxiliary capacitance. An active matrix substrate having a plurality of scanning signal lines each connected to the at least one switching element; a plurality of display signal lines each connected to the at least one switching element; A plurality of first auxiliary capacitance lines for supplying a first auxiliary capacitance opposing voltage to one auxiliary capacitance opposing electrode; and a plurality of second auxiliary capacitance lines each supplying a second auxiliary capacitance opposing voltage to the second auxiliary capacitance opposing electrode. And a first auxiliary capacitance main line electrically connected to the plurality of first auxiliary capacitance lines; and a second auxiliary capacitance line electrically connected to the plurality of second auxiliary capacitance lines, The plurality of scanning signal lines, the plurality of first auxiliary capacitance lines, and the plurality of second auxiliary capacitance lines extend in the first direction, and the plurality of display signal lines, the first auxiliary capacitance line And the second storage capacitor main line extends in the second direction, and each of the plurality of scanning lines extends to the outside of the terminal region, and the first storage capacitor main line and the second storage capacitor main line extend in the second direction. At least one of the auxiliary capacitance trunk lines extends to the outside of the terminal region.
[0019]
In a preferred embodiment, the terminal region is provided between the first end of one of two first ends intersecting the first direction of the substrate and the display region, and in the second direction of the substrate. Are formed only between one of the two second end sides intersecting with the display area and the display area.
[0020]
In a preferred embodiment, at least one of the plurality of auxiliary capacitance lines extends outside the terminal region, and the second auxiliary capacitance main line extends outside the terminal region.
[0021]
In a preferred embodiment, the plurality of scanning lines, the plurality of first auxiliary capacitance lines, the plurality of second auxiliary capacitance lines, and the second auxiliary capacitance main line are formed from the same conductive layer.
[0022]
A method for manufacturing an active matrix substrate according to a preferred embodiment of the present invention is a method for manufacturing an active matrix substrate having the above configuration, wherein (a) a step of preparing a mother substrate; and (b) a step of: A short ring disposed outside the display region, the terminal region, and the display region and the terminal region, wherein each of the plurality of scanning lines, the first auxiliary capacitance main line, and the second auxiliary capacitance Forming a short ring connected to at least one of the main lines; and (c) connecting the plurality of scanning lines and the short ring between the short ring and the terminal region. Cutting the at least one of the first auxiliary capacitance trunk line and the second auxiliary capacitance trunk line.
[0023]
In a preferred embodiment, the short ring is formed in the same step as the plurality of scanning lines, the plurality of first auxiliary capacitance lines, the plurality of second auxiliary capacitance lines, and the second auxiliary capacitance main line.
[0024]
In a preferred embodiment, the step (c) includes a step of cutting the mother substrate between the short ring and the terminal region. Or conversely, for example, only the wiring may be cut using a laser beam or the like, and the wiring may be cut electrically from the short ring. That is, the completed active matrix substrate may include a short ring.
[0025]
A liquid crystal display device according to the present invention includes: the active matrix substrate according to any one of the above, a liquid crystal layer, and a counter substrate disposed to face the active matrix substrate with the liquid crystal layer interposed therebetween. Features.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an active matrix substrate and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings. Hereinafter, an active matrix type liquid crystal display device including a TFT as a switching element will be exemplified.
[0027]
FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal panel 100 having an active matrix substrate 100A according to the first embodiment. A liquid crystal display device can be obtained by providing a power supply circuit and a backlight or the like as necessary in the liquid crystal panel 100.
[0028]
The liquid crystal panel 100 includes a display area 1 corresponding to a displayable area of the liquid crystal display device, and a frame area R0 provided therearound. In the display area 1, a plurality of pixels 21 (see FIG. 8) are arranged in a matrix (array).
[0029]
Note that in this specification, also for the active matrix substrate 100A, a region corresponding to each of the display panels 100 is referred to as a display region 1 and a frame region RO, and a region corresponding to the pixels 21 is referred to as a pixel region.
[0030]
In the frame region R0 of the active matrix substrate 100A, a scanning line terminal portion 2a in which terminals for inputting scanning signals (gate signals) to scanning lines (gate lines, GL, 12) are arranged, and a scanning line terminal portion 2a is displayed. A scanning line portion 3a for connecting to a scanning line in the region 1, a signal line terminal portion 2b in which terminals for inputting a display signal (source signal) are arranged on a signal line (source line), and a signal line terminal portion 2a and a signal line portion 3b for connecting the signal line (SL, 14) in the display area 1. The scanning line terminal portion 2a and the signal line terminal portion 2b are collectively referred to as a terminal region 2.
[0031]
FIG. 8 shows an equalization circuit in the display area 1 of the liquid crystal panel 100. On the active matrix substrate 100A, pixel electrodes 18a and 18b, TFTs 16a and 16b as switching elements provided corresponding to the respective pixels 21, a gate line GL for controlling ON / OFF of the TFTs 16a and 16b, and a pixel A source line SL for supplying a predetermined voltage to the electrodes 18a and 18b, an auxiliary capacitance line CSO (odd-numbered auxiliary capacitance line), a CSE (even-numbered auxiliary capacitance line), and the like are provided. The auxiliary capacitance line CSO and the auxiliary capacitance line CSE are connected to the auxiliary capacitance counter electrodes 22a and 22b for forming the auxiliary capacitances CcsO and CcsE, respectively, to apply a predetermined voltage to these electrodes 22a and 22b. Used for The pixel region of the active matrix substrate 100A includes TFTs 16a and 16b, pixel electrodes 18a and 18b, and auxiliary capacitors CcsO and CcsE.
[0032]
Further, a common electrode 17 is formed on a counter substrate (not shown) provided to face the active matrix substrate 100A. Liquid crystal capacitors ClcO and ClcE are formed between the common electrode 17 and the pixel electrodes 18a and 18b. The opposing substrate may be provided with a color filter or the like as necessary. The operation of the liquid crystal panel having such a circuit configuration will be described later.
[0033]
Before describing the configuration of an active matrix substrate in an embodiment of the present invention, an example (reference example) of a configuration based on a conventional design method will be described with reference to FIGS. 2, 3, and 4. FIG.
[0034]
The active matrix substrate 100B shown in FIG. 2 includes an odd-numbered CS wiring CSO (hereinafter, also referred to as CSO wiring, 24O) and an even-numbered CS wiring CSE (hereinafter, referred to as CSE wiring) extending in the display region 1. 24E) and the gate line GL (12).
[0035]
In FIG. 2, reference numeral 102 'indicates a motherboard, and reference numeral 102 indicates the outer edge of the final active matrix substrate 100A. That is, after various circuit elements and the like are formed on the mother substrate 102 ', the mother substrate 102' is cut along the line indicated by 102, and the active matrix substrate 100A is obtained. For simplification of the drawing, the CSO wiring and the CSE wiring are shown outside the substrate 102, but are naturally provided inside the short ring 30.
[0036]
In FIG. 2, the wiring shown by a solid line is formed of a gate metal, and the wiring shown by a broken line is formed of a source metal.
[0037]
As can be seen from FIG. 2, in the display area 1, a plurality of substantially parallel CSO wirings 24O and a plurality of substantially parallel even-numbered CSE wirings 24E are formed in the lateral direction (X direction) of the panel. Extends along. The CSO wiring 24O and the CSE wiring 24E are alternately arranged in the vertical direction (Y direction) of the panel, and a gate line is provided between a pair of adjacent CS wirings (that is, between the CSO wiring 24O and the CSE wiring 24E). GL is provided.
[0038]
Further, the plurality of odd-numbered CS lines CSO are electrically connected to a common trunk line 26b (hereinafter, also referred to as a CSO trunk line) in the scanning line region 3a. Are electrically connected to a common trunk line 26a (hereinafter, also referred to as a CSE trunk line) in the scanning line region 3a. The CSO trunks 26b and 26d and the CSE trunks 26a and 26c extend in the vertical direction (Y direction) of the panel and intersect with the direction in which the plurality of CSE wirings 24E and the CSO wiring 24O extend in the display area 1 (X direction). Direction (here, a direction orthogonal to the direction). These trunk lines 26b and 26a or 26d and 26c are insulated and spaced apart from each other, and provided so as to be adjacent to each other, and signals are separately supplied. 26b and 26d or 26a and 26c are supplied with a common signal.
[0039]
A short ring 30 is arranged outside the display area 1 and the terminal area 2 around the panel, and a scanning line GL is connected to the short ring 30 on the gate signal input side via the terminal 2a.
[0040]
On the gate signal input side, it is necessary to input a gate signal through the terminal 2a, so that the terminal pitch needs to be smaller than the pixel pitch in the display area 1 so that ACF or TAB can be connected to the terminal 2a. Therefore, it is necessary to narrow the gate line pitch. However, since the TAB is not arranged on the gate signal non-input side, it is not necessary to reduce the pitch between the CSO wiring 240 and the CSE wiring 24E. When the wiring density of the gate line is 1, the wiring density in the configuration of FIG. 2 is 1.
[0041]
However, when cutting the substrate 102 from the mother substrate 102 ', the CSO wiring 240 and the CSE wiring 24E extending to the short ring 30 are cut, so that these wirings are exposed. Need to be performed. This region is a region in which the terminal region 2 for the scanning line and the signal line is not formed, and is a region where it is not necessary to take a countermeasure against corrosion.
[0042]
Next, in the active matrix substrate 100C shown in FIG. 3, the scanning line GL, the CSO wiring 240 and the CSE wiring 24E are connected to the short ring 30 on the gate signal input side via the terminal portion 2a. Therefore, as shown in FIG. 2, the extended portions of the CSO wiring 240 and the CSE wiring 24E are not cut in a region where the terminal region 2 is not provided. However, as compared with the case of FIG. 2, the wiring density on the gate signal input side is doubled, so that there is a disadvantage that the defective rate increases.
[0043]
Next, the active matrix substrate 100D shown in FIG. 4 has a configuration in which the CSE wiring 24E is connected to the gate signal input side and the CSO wiring 24O is connected to the short ring from the gate signal non-input side. In this case, the wiring density on the gate signal input side is 3/2 as compared with the case of FIG. However, also in this case, similarly to the case of FIG. 2, it is necessary to take a countermeasure against corrosion in a region where the countermeasure against corrosion was not originally required, and there is a problem that the number of steps is increased.
[0044]
FIG. 5 schematically shows a configuration of an active matrix substrate 100A according to the embodiment of the present invention.
[0045]
In the active matrix substrate 100A, the connection between the CSE wiring 24E and the short ring 30 is made on the gate signal input side (left side). Here, each of the CSE wirings 24E is connected to the short ring 30 via the terminal portion 2a, but at least one of the CSE wirings 24E may be connected to the short ring 30.
[0046]
On the other hand, all the CSO wirings 24O are connected to the trunk line 26d on the gate signal non-input side (right side), and are connected to the short ring 30 via the trunk line 26d. The trunk line 26d is provided in a direction crossing the CSO wiring 24O, and is connected to the short ring 30 outside the terminal portion 2b (see FIG. 1) provided with the source terminal portion 3a.
[0047]
In the active matrix substrate 100A, since only the CSE wiring 24E is connected to the short ring 30 on the gate signal input side, the wiring density on the gate signal input side is 3/2 as in the active matrix substrate 100D of FIG. is there. Further, since the CSO wiring 240 is connected to the main line 26d and connected to the short ring via the terminal 2b on the source signal input side, there is no need to take extra measures against corrosion.
[0048]
According to the active matrix substrate 100A of the present embodiment, the wiring density on the gate signal input side is reduced to 3/2 of that in the case of one CS wiring, and the CS wiring 24 (240 and 24E) is connected to the short ring 30. Since the connection portion can be provided only on the side where the terminal region 2 is provided, the cut portion of the CS wiring 24 can be protected by countermeasures against the terminal region 2 (for example, formation of a resin layer).
[0049]
Further, the configuration shown in FIG. 5 has an advantage that the gate wiring GL, the CS wiring 24 (240, 24E), and the CS main line 26d can be formed of gate metal.
[0050]
When a bottom gate type TFT is adopted, the short ring 30 formed on the mother substrate 102 ′ includes a gate metal, a gate insulating film GI, a semiconductor layer (i layer, n + layer), as schematically shown in FIG. It has a cross-sectional structure in which a source metal layer and an upper layer ITO (layer forming a pixel electrode) are stacked. When the gate metal formed at the bottom is used, the gate wiring GL, the CS wiring 24 (240, 24E) and the CS main line 26d can be formed in the same step as shown in FIG. Further, by forming another CS trunk using the source metal formed thereon, the active matrix substrate 100A shown in FIG. 5 can be easily manufactured.
[0051]
Hereinafter, an example of a liquid crystal display device using the liquid crystal panel 100 having the above-described active matrix substrate 100 will be described with reference to FIGS.
[0052]
FIG. 8 is a diagram schematically showing an equivalent circuit of the liquid crystal panel in a display area of the liquid crystal panel. This liquid crystal panel is an active matrix type liquid crystal panel having pixels (sometimes called dots) arranged in a matrix having rows and columns. The pixel 21 illustrated in FIG. 8 corresponds to a pixel in n rows and m columns.
[0053]
The pixel 21 has a first sub-pixel and a second sub-pixel. In FIG. 8, the liquid crystal capacitance corresponding to the first sub-pixel is denoted as ClcO, and the liquid crystal capacitance corresponding to the second sub-pixel is denoted as ClcE. The liquid crystal capacitance ClcO of the first sub-pixel includes the first sub-pixel electrode 18a, the common electrode 17, and a liquid crystal layer therebetween. The liquid crystal capacitance ClcE of the second sub-pixel is constituted by the second sub-pixel electrode 18b, the common electrode 17, and the liquid crystal layer between them. The first sub-pixel electrode 18a is connected to the signal line 14 (source line SL) via the TFT 16a, and the second sub-pixel electrode 18b is connected to the same signal line 14 via the TFT 16b. Gate electrodes of the TFTs 16a and 16b are connected to a common scanning line 12 (gate line GL).
[0054]
The first storage capacitor and the second storage capacitor provided corresponding to the first sub-pixel and the second sub-pixel are denoted by CcsO and CcsE, respectively, in FIG. The storage capacitor electrode 23a of the first storage capacitor CcsO is connected to the drain of the TFT 16a, and the storage capacitor electrode 23b of the second storage capacitor CcsE is connected to the drain of the TFT 16b. Note that the connection form of the auxiliary capacitance electrode is not limited to the illustrated example, and it is sufficient that the auxiliary capacitance electrode is electrically connected so that the same voltage as that of the corresponding subpixel electrode is applied. In other words, the sub-pixel electrode and the corresponding storage capacitor electrode may be electrically connected directly or indirectly, and for example, each sub-pixel electrode may be connected to the corresponding storage capacitor electrode.
[0055]
The storage capacitor counter electrode 22a of the first storage capacitor CcsO is connected to a CSO wiring (storage capacitor wiring 240 (or 24E)), and the storage capacitor counter electrode 22b of the second storage capacitor CcsE is connected to a CSE wiring (storage capacitor wiring). 24E (or 24O)). With this configuration, it is possible to supply different auxiliary capacitance voltages to the respective auxiliary capacitance counter electrodes 22a and 22b of the first and second auxiliary capacitances. The connection relationship between the auxiliary capacitance counter electrode and the auxiliary capacitance wiring is appropriately selected according to the driving method (dot inversion driving or the like). Note that, for example, a gate insulating film can be commonly used as an insulating layer included in the storage capacitor.
[0056]
Next, the principle that different voltages can be applied to the first sub-pixel (ClcO) and the second sub-pixel (ClcE) by the above configuration will be described with reference to FIG.
[0057]
FIG. 9 shows voltage waveforms and timings of various signals input to the pixel (n, m) in FIG. (A) shows a horizontal scanning period (H) over two frames, and (b) shows a waveform (broken line) of a display signal voltage Vs (m ± 1) supplied to the m ± 1st signal line 14. , (C) shows the waveform (solid line) of the display signal voltage (gradation signal voltage) Vs (m) supplied to the m-th signal line 14. (D) shows the waveform of the scanning signal voltage (Vg (n)) supplied to the n-th scanning line 12, and (e) and (f) show the auxiliary signal supplied to the auxiliary capacitance lines 24O and 24E, respectively. 2 shows waveforms of capacitance opposing voltages (VcsO, VcsE). (G) and (h) show the waveforms of the voltages (VlcO, VlcE) applied to the liquid crystal capacitance ClcO of the first sub-pixel and the liquid crystal capacitance ClcE of the second sub-pixel, respectively.
[0058]
The driving method shown in FIG. 9 shows an embodiment in which the present invention is applied to a 2H dot inversion + frame inversion type liquid crystal display device.
[0059]
The display signal voltage Vs applied to the signal line 14 is inverted in polarity each time two scanning lines are selected (every 2H), and is changed to adjacent signal lines (for example, Vm and V (m ± 1)). The polarity of the applied display signal voltage is reversed (2H dot inversion), and the polarity of the display signal voltage Vs for all signal lines 14 is inverted for each frame (frame inversion).
[0060]
Here, the cycle in which the polarities of the auxiliary capacitance opposite voltages VcsO and VcsE are inverted is the same as the cycle (2H) in which the polarity of the display signal voltage is inverted, and the phase is shifted by 周期 cycle (1H). The auxiliary capacitance opposed voltages VcsO and VcsE have waveforms having the same amplitude and different phases by 180 °.
[0061]
The reason why the voltages (VlcO, VlcE) applied to the liquid crystal capacitance ClcO and the liquid crystal capacitance ClcE become as shown in FIG. 9 will be described with reference to FIG.
[0062]
When the scanning signal voltage Vg is at the high level (VgH), the TFTs 16a and 16bn become conductive, and the display signal voltage Vs of the signal line 14 is applied to the sub-pixel electrodes 18a and 18b. The voltage applied to both ends of the liquid crystal capacitors ClcO and ClcE is the difference between the voltage of the sub-pixel electrodes 18a and 18b and the voltage (Vcom) of the common electrode 17, respectively. That is, VlcO = Vs-Vcom (VlcE = Vs-Vcom).
[0063]
After (n × h−Δt) seconds, when the scanning line signal voltage Vg switches from the high voltage VgH in the ON state to the low voltage VgL (<Vs) in the OFF state, the sub-pixel electrode 18a and the The voltage at 18b drops by Vd. The voltage Vcom of the common electrode 17 is adjusted to a voltage lower than the center potential of the display signal voltage Vs by this Vd reduction. This decrease is ΔV.
[0064]
After (n × h) seconds, the voltage VlcO of the liquid crystal capacitance ClcO is affected by the voltage VcsO of the auxiliary capacitance counter electrode of the auxiliary capacitance CcsO which is electrically connected to the sub-pixel electrode 18a constituting the liquid crystal capacitance ClcO. Change. The voltage VlcE of the liquid crystal capacitance ClcE changes under the influence of the voltage VcsE of the auxiliary capacitance counter electrode of the auxiliary capacitance CcsE electrically connected to the sub-pixel electrode 18b constituting the liquid crystal capacitance ClcE. Here, it is assumed that, at (n × h) seconds, the auxiliary capacitance opposite voltage VcsO increases by VcsOp> 0, and the auxiliary capacitance opposite voltage VcsE decreases by VcsEp> 0. That is, the full amplitude (Vp-p) of the auxiliary capacitance opposing voltage VcsO is VcsOp, and the full amplitude of the auxiliary capacitance opposing voltage VcsE is VcsEp.
[0065]
When the total capacitance of the liquid crystal capacitance ClcO and the auxiliary capacitance CcsO connected to the drain of the TFT 16a is CpixO,
VlcO = Vs−ΔV + VcsOp (CcsO / CpixO) −Vcom
Becomes
Assuming that the total capacitance of the liquid crystal capacitance ClcE and the auxiliary capacitance CcsE connected to the drain of the TFT 16b is CpixE,
VlcE = Vs−ΔV−VcsEp (CcsE / CpixE) −Vcom
It becomes.
[0066]
Next, after (n + 2) × h seconds (at the time of (n + 3) H), VlcO and VlcE are similarly affected by the voltage VcsO (or VcsE) of the auxiliary capacitance counter electrode, and the voltages at the time of nH are respectively obtained. Return to value.
[0067]
VlcO = Vs−ΔV−Vcom
VlcE = Vs−ΔV−Vcom
This change in voltage is repeated until Vg (n) becomes VgH in the next frame. As a result, the respective effective values of VlcO and VlcE become different values.
[0068]
That is, assuming that the effective value of VlcO is VlcOrms and the effective value of VlcE is VlcErms,
VlcOrms = Vs−ΔV + (１ ／) VcsOp (CcsO / CpixO) −Vcom
VlcErms = Vs-ΔV- (1/2) VcsEp (CcsE / CpixE) -Vcom
It becomes. Therefore, if the difference between these effective values is ΔVlc = VlcOrms−VlcErms,
ΔVlc = (１ ／) {VcsOp (CcsO / CpixO) + VcsEp (CcsE / CpixE)}
It becomes.
[0069]
If the liquid crystal capacitance and the auxiliary capacitance of the two sub-pixels are equal (ClcO = ClcE = Clc, CcsO = CcsE = Ccs, CpixO = CpixE = Cpix),
ΔVlc = (１ ／) (VcsOp + VcsEp) (Ccs / Cpix)
It becomes. As shown in FIG. 9, when VcsOp = VcsEp and the phases are different by 180 °, if VcsOp = VcsEp = Vcsp, then
ΔVlc = Vcsp (Ccs / Cpix)
The effective value of VlcO is large, and the effective value of VlcE is small.
[0070]
If the voltages of VcsO and VcsE are exchanged, on the contrary, the effective value of VlcO can be set to be small and the effective value of VlcE can be set to be large.
[0071]
Here, since the frame inversion drive is performed, the polarity of Vs is inverted in the next frame, and Vlc <0. However, if the polarities of VcsO and VcsE are also inverted in synchronization with this, the same applies. The result is obtained.
[0072]
In this case, the polarity of the display signal voltage supplied to the adjacent signal line 14 is reversed to perform the dot inversion driving. Therefore, the driving state of the pixel (n, m) in the next frame is the pixel (n). The driving state is the same as the driving state of the pixels (n, m ± 1) on both sides of the signal line 14 (m) of (n, m).
[0073]
Next, referring to FIG. 10, the distribution (a) of the polarity of the voltage applied to each pixel (liquid crystal capacitor) in a certain frame and the storage capacitor counter voltage (storage capacitor) obtained by the driving method shown in FIG. The combination (b) of the wiring and the distribution (c) of the effective voltage applied to the sub-pixel for each pixel will be described.
[0074]
As shown in FIG. 10A, when the driving method of FIG. 9 is adopted, 2H dot inversion in which the polarity is inverted every two rows and the polarity is inverted every adjacent column is realized. In the next frame shown in FIG. 10A, all polarities are inverted (frame inversion).
[0075]
Here, as shown in FIG. 10B, when the auxiliary capacitance lines connecting the auxiliary capacitance counter electrodes of the auxiliary capacitances connected to the respective sub-pixel electrodes are combined, the effective voltage as shown in FIG. Can be formed. Note that the upper row of each cell in FIG. 10B shows an auxiliary capacitance line (240 or 24E) to which an auxiliary capacitance counter electrode used in combination with the sub-pixel electrode 18a is connected, and the lower row shows the sub-pixel electrode 18b A storage capacitance line (240 or 24E) to which a storage capacitance counter electrode used in combination is connected is shown. The upper part of each cell in FIG. 10C corresponds to the sub-pixel (liquid crystal capacitance) constituted by the sub-pixel electrode 18a, and the lower part corresponds to the sub-pixel (liquid crystal capacitance) constituted by the sub-pixel electrode 18b. . In FIG. 10C, the effective voltage of the sub-pixel denoted by “O” is high, and the effective voltage of the sub-pixel denoted by “E” is low.
[0076]
As can be seen from FIG. 10C, when the driving method of FIG. 9 is adopted, 2H dot inversion driving (FIG. 10A) is realized, and the magnitude relationship of the effective values applied to the sub-pixels is In each of the row and column directions, the direction is reversed for each sub-pixel. As described above, when the spatial frequency of the distribution of the effective value of the voltage applied to the sub-pixel is high, high-quality display can be performed.
[0077]
In the above liquid crystal panel, the display signal voltage is supplied to the sub-pixel electrodes 18a and 18b from the common signal line 14 via the corresponding TFTs 16a and 16b. The gate electrodes of the TFTs 16a and 16b are formed integrally with the common scanning line 12, and are provided between the sub-pixel electrodes 18a and 18b. The sub-pixel electrodes 18a and 18b are located symmetrically with respect to the scanning line 12, and have the same area in this example. The auxiliary capacitance counter electrode is formed integrally with the auxiliary capacitance lines 24O and 24E, and each of the auxiliary capacitance lines 24O and 24E is shared by two pixels adjacent in the Y direction.
[0078]
Although a TFT type liquid crystal display device has been illustrated above, another switching element (for example, an MIM element) may be used.
[0079]
In the liquid crystal panel described above, since the active matrix substrate 100A is used, the amplitude as shown in FIGS. 9E and 9F is applied to each of the CSO wiring (24O) and the CSE wiring (24E). And the storage capacitor opposite voltages VcsO and VcsE having waveforms that are the same and 180 ° out of phase with each other and have inverted waveforms can be appropriately supplied. Therefore, it is possible to appropriately control the voltage applied to the liquid crystal layer, which changes depending on the amplitude of the storage capacitor counter voltage in the pixel division driving method. As described above, in the display device of the present embodiment, the effective voltage applied to the liquid crystal layer is appropriately changed in the dot inversion driving method in which voltages having different polarities are applied to each of the CS wiring groups driven by two systems. Thus, high-quality display can be performed.
[0080]
Note that the active matrix substrate shown in FIG. 11 can be used instead of the active matrix substrate 100A shown in FIG. In the configuration shown in FIG. 11, the CS wiring (24) is connected to the CS trunks 26a and 26b also on the gate terminal region side, and connected to the short ring on the source terminal region side via these CS trunks 26a and 26b. It has the following configuration. When this configuration is employed, there is an advantage that the wiring density can be set to 1 in the gate terminal region. However, since the CS trunk lines 26a and 26b cannot be formed of gate metal, it is necessary to form a contact hole or the like in order to connect with the short ring 30.
[0081]
In addition, the present invention is not limited to the above embodiment, and can be suitably applied to a CS2-system liquid crystal display device as described in Patent Document 1.
[0082]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the structure which can take a countermeasure against static electricity easily in the active matrix board which has two wirings is provided.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a configuration of a liquid crystal panel 100 having an active matrix substrate 100A according to an embodiment of the present invention.
FIG. 2 is a diagram schematically showing a configuration of an active matrix substrate 100B of a reference example.
FIG. 3 is a diagram schematically showing a configuration of an active matrix substrate 100C of a reference example.
FIG. 4 is a diagram schematically showing a configuration of an active matrix substrate 100D of a reference example.
FIG. 5 is a diagram schematically showing a configuration of an active matrix substrate 100A according to an embodiment of the present invention.
6A and 6B are diagrams schematically showing a configuration of a short ring 30 in an active matrix substrate 100A according to an embodiment of the present invention, wherein FIG. 6A is a cross-sectional view taken along line 6A-6A ′ in FIG. (b) is a sectional view taken along line 6A-6A 'in (c), and (c) is a plan view.
FIG. 7 is a diagram schematically showing a wiring pattern formed of a gate metal in the active matrix substrate 100A according to the embodiment of the present invention.
FIG. 8 is a diagram showing an equalizing circuit in a display area 1 of the liquid crystal panel 100 according to the embodiment of the present invention.
9 is a diagram illustrating voltage waveforms and timings of various signals input to the pixel (n, m) in FIG.
10A shows the distribution of the polarity of the voltage applied to each pixel (liquid crystal capacitor) in a certain frame obtained by the driving method shown in FIG. 9, and FIG. (C) shows a distribution of effective voltages applied to sub-pixels of each pixel.
FIG. 11 is a view showing another active matrix substrate according to the embodiment of the present invention.
[Explanation of symbols]
ClcO liquid crystal capacitance (first sub-pixel)
ClcE liquid crystal capacitance (second sub-pixel)
CcsO 1st auxiliary capacity
CcsE 1st auxiliary capacity
12 scanning lines
14 signal line
17 Common electrode
18a First sub-pixel electrode
18b second sub-pixel electrode
16a, 16b TFT
16O, 16E Drain electrode extension
24O First auxiliary capacitance wiring
24E Second auxiliary capacitance wiring

Claims (13)

A substrate, a display region on the substrate defined by a plurality of pixel regions arranged along a first direction and a second direction intersecting the first direction, and the plurality of pixels arranged around the display region. A plurality of first wirings, a plurality of second wirings for supplying a predetermined signal to the plurality of pixel regions, and a terminal region defined by a plurality of terminals to which signals for driving the pixel regions are input; A plurality of third wirings and a plurality of fourth wirings; a fifth wiring electrically connected to the plurality of second wirings; and a sixth wiring electrically connected to the plurality of third wirings. An active matrix substrate,
The plurality of first wires, the plurality of second wires, and the plurality of third wires extend in the first direction, and the plurality of fourth wires, the fifth wire, and the sixth wire are Extending parallel to two directions, and
An active matrix substrate, wherein each of the plurality of first wirings extends to the outside of the terminal area, and at least one of the fifth wiring and the sixth wiring extends to the outside of the terminal area; . Each of the plurality of pixel regions includes at least one switching element, a pixel electrode to which a display signal is supplied via the at least one switching element, at least one auxiliary capacitance electrode, and at least one auxiliary capacitance electrode. An auxiliary capacitance opposing electrode that opposes via an insulating layer to form an auxiliary capacitance,
The plurality of first wirings are a plurality of scanning lines each connected to the at least one switching element, and the plurality of fourth wirings are a plurality of display lines each connected to the at least one switching element. 2. The active matrix substrate according to claim 1, wherein the plurality of second wirings and the plurality of third wirings are signal lines, and each of the plurality of third lines is an auxiliary capacitance line connected to the auxiliary capacitance counter electrode. 3. It is a manufacturing method of the active matrix substrate of Claim 1 or 2, Comprising:
(A) a step of preparing a mother substrate;
(B) On the motherboard, the display region, the terminal region, and a short ring disposed outside the display region and the terminal region, wherein each of the plurality of first wirings includes: Forming a short ring connected to at least one of the fifth wiring and the sixth wiring;
(C) cutting each of the plurality of first wirings and at least one of the fifth wiring and the sixth wiring connected to the short ring between the short ring and the terminal region; When,
A method for manufacturing an active matrix substrate, comprising: 4. The active matrix substrate according to claim 3, wherein the short ring is formed in the same step as the plurality of first wirings, the plurality of second wirings, the plurality of third wirings, and the sixth wiring. Method. A substrate, a display region on the substrate defined by a plurality of pixel regions arranged along a first direction and a second direction intersecting the first direction; and the plurality of pixels arranged around the display region. A terminal area defined by a plurality of terminals to which a signal for driving the pixel area is input,
Each of the plurality of pixel regions includes at least one switching element, a pixel electrode to which a display signal is supplied via the at least one switching element, a first auxiliary capacitance electrode, and a second auxiliary capacitance electrode; A first auxiliary capacitance opposing electrode opposing the first auxiliary capacitance electrode via an insulating layer, and a second auxiliary capacitance opposing the second auxiliary capacitance electrode via an insulating layer to form a second auxiliary capacitance; An active matrix substrate having an auxiliary capacitance counter electrode,
A plurality of scanning signal lines each connected to the at least one switching element; a plurality of display signal lines each connected to the at least one switching element; A plurality of first auxiliary capacitance lines for supplying an auxiliary capacitance opposing voltage; a plurality of second auxiliary capacitance lines each for supplying a second auxiliary capacitance opposing voltage to the second auxiliary capacitance opposing electrode; A first auxiliary capacitance main line electrically connected to the capacitance line, and a second auxiliary capacitance line electrically connected to the plurality of second auxiliary capacitance lines;
The plurality of scanning signal lines, the plurality of first auxiliary capacitance lines, and the plurality of second auxiliary capacitance lines extend in the first direction, and include the plurality of display signal lines, the first auxiliary capacitance trunk line, and the second auxiliary capacitance line. The second auxiliary capacitance trunk extends in the second direction, and
Each of the plurality of scanning lines extends to the outside of the terminal region, and at least one of the first auxiliary capacitance main line and the second auxiliary capacitance main line extends to the outside of the terminal region. Matrix substrate. The terminal region is provided between the display region and one of two first edges of the substrate that intersect with the first direction, and two second edges that intersect with the second direction of the substrate. 6. The active matrix substrate according to claim 5, wherein the active matrix substrate is formed only between one of the two end sides and the display area. 7. The device according to claim 5, wherein at least one of the plurality of auxiliary capacitance lines extends outside the terminal region, and wherein the second auxiliary capacitance main line extends outside the terminal region. 8. Active matrix substrate. 8. The device according to claim 5, wherein the plurality of scanning lines, the plurality of first auxiliary capacitance lines, the plurality of second auxiliary capacitance lines, and the second auxiliary capacitance main line are formed from the same conductive layer. The active matrix substrate according to the above. It is a manufacturing method of the active matrix substrate in any one of Claims 5 to 8, Comprising:
(A) a step of preparing a mother substrate;
(B) a short ring disposed on the mother substrate outside the display region, the terminal region, and the display region and the terminal region, wherein each of the plurality of scan lines is Forming a short ring connected to at least one of the auxiliary capacitance trunk and the second auxiliary capacitance trunk;
(C) between the short ring and the terminal region, each of the plurality of scanning lines and at least one of the first auxiliary capacitance trunk line and the second auxiliary capacitance trunk line connected to the short ring. Cutting,
A method for manufacturing an active matrix substrate, comprising: 10. The short ring according to claim 9, wherein the plurality of scanning lines, the plurality of first auxiliary capacitance lines, the plurality of second auxiliary capacitance lines, and the second auxiliary capacitance main line are formed in the same step. A method for manufacturing an active matrix substrate. The method of manufacturing an active matrix substrate according to claim 9, wherein the step (c) includes a step of cutting the mother substrate between the short ring and the terminal region. An active matrix substrate manufactured by the method for manufacturing an active matrix substrate according to claim 9. 13. A liquid crystal display device comprising: the active matrix substrate according to claim 5; a liquid crystal layer; and a counter substrate disposed to face the active matrix substrate via the liquid crystal layer.

Images