JP2004117485A - Video display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inhibit deterioration of an image due to interference between an FRC pattern period and a motion compensation period of MPEG. <P>SOLUTION: The interference is inhibited by providing the video display device with a motion compensation period detection means 1 for detecting the motion compensation of a MPEG compression video signal, an FRC pattern generation means 2 for generating a pattern for switching on-off the display according to the gradations of an input video signal in frame units, and a period control means 3 for controlling the period of the pattern generated by the FRC pattern generation means according to an output of the motion compensation period detection means, and synchronizing the FRC pattern period with the MPEG motion compensation period. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a video display device, and more particularly to a multi-gradation display circuit in a simple matrix type display device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as an image display device, for example, an image display device described in Patent Document 1 is known.
[0003]
Hereinafter, a description will be given based on FIG. 5 showing a configuration of a conventional video display device. As a configuration of a conventional video display device, reference numeral 111 denotes an FRC pattern generation circuit that determines and outputs a FRC (Frame Rate Control) pattern FD based on lower three bits of display data to be displayed as a gradation, and 112 denotes a luminance level of 0%. Poff, 50% luminance level Pg, and 100% luminance level Pon are generated by a gradation pulse generating means 113. The upper one bit 113 of the display data to be displayed as a gradation and the FRC A display pulse selection circuit that selectively outputs three types of gradation pulses Poff, Pg, and Pon according to the pattern FD. Reference numeral 114 denotes a liquid crystal panel driven by the output of the display pulse selection circuit 113.
[0004]
A display example of the conventional video display device configured as described above will be described with reference to FIG. FIG. 6 is a display example when the lower three bits of the display data are (1, 0, 1). The FRC pattern FD selected by the FRC pattern generation circuit according to the 3-bit display data is 4/5, and 4 out of 5 frames are "1" and the remaining 1 frame is "0".
[0005]
Here, when the upper 1 bit of the display data is 0, the gradation pulse selecting circuit 113 outputs Pg of a luminance level of 50% when the FD is “1”, and outputs the luminance level of 50% when the FD is “0”. Selectively output 0% Poff. As a result, the luminance is 50% four times out of five frames, and is 0% once, and the luminance display of 40% is obtained by averaging the five frames.
[0006]
When the upper 1 bit of the display data is 1, the grayscale pulse selection circuit 113 outputs a Pon with a luminance level of 100% when the FD is “1”, and outputs a Pon with a luminance level of “0” when the FD is “0”. Selectively output 50% of Pg. As a result, four times out of five frames have a luminance of 100%, and one time has a luminance of 50%. When the five frames are averaged, a luminance display of 90% is performed.
[0007]
As described above, an FRC (Frame Rate Control) for performing display on / off for each frame according to the bits of the display data (gradation display on average by turning on / off n times in the five frames described above). ) Method, and further multi-gradation display is performed by using PWM that changes the pulse width in one horizontal scanning period (in the above-described example, gradation display with three-step pulse widths of Pon, Pg, and Poff). Things.
[0008]
In general, the FRC has a drawback of a display flow in which a dot arrangement pattern flows in a diagonal direction of a screen and a method called flicker. When the number of gradations increases, the number of frames required to express the gradations is reduced. Since the frequency increases, the visibility is improved by lowering the FRC frequency, and this problem becomes particularly noticeable.
[0009]
To solve this problem, in the conventional video display device, by reducing the number of gradations expressed by FRC and supplementing this with PWM, it is possible to set the FRC frequency higher, thereby suppressing display flow and flicker. Things.
[0010]
On the other hand, with the spread of DVDs (Digital Video Discs), video signals compressed by the MPEG method employed in DVDs and the like are often used as images to be displayed on these display devices.
[0011]
One feature of the video signal compressed by the MPEG method will be described with reference to FIG. Although the compression of the MPEG system is configured by the motion compensation prediction and the DCT system, the motion compensation which is largely related to the present invention will be described. FIG. 7 shows a configuration of motion compensation prediction between frames, which is composed of three types of picture coding: an I (intra coded) picture, a P (predictive coded) picture, and a B (bidirectionally predicated coded) picture.
[0012]
The I picture is coded independently of the other screen, and all information (macroblock) in the screen is coded. For this reason, the I-picture has a low compression ratio and is effective at the time of screen switching. Next, the P picture is coded by a change prediction from the I picture or the P picture in the forward prediction coding screen. The B picture performs predictive coding from the previous, subsequent, or previous and subsequent screens using I or P pictures located before and after in time, and the prediction is performed in units of macroblocks. realizable.
[0013]
The above three types of coding, I, B, and P, are switched according to the characteristics of the video and the like to configure the motion compensation. A picture is periodically arranged, and a video is mainly composed of a B picture and a P picture having a high compression ratio and having difference (prediction) information of a video change based on the picture. As shown in the lower part of FIG. 7, as a feature of the video compressed in this way, the error rate increases as the picture is located farther away from the I picture with a low compression rate (= the error rate is also low at the same time). Since the error is improved at the time of periodically arranged I pictures, a periodic variation occurs in the error rate. This error rate fluctuation is characterized in that it tends to appear as noise that fluctuates in the frame direction on the actual video display.
[0014]
[Patent Document 1]
JP-A-3-125188
[Problems to be solved by the invention]
This video display device is characterized by using both the FRC and the PWM method. The number of gradations expressed in the FRC portion is reduced, and the reduced gradations are supplemented by the PWM in the horizontal direction, thereby increasing the number of gradations. Therefore, it is possible to set the FRC frequency to be high while suppressing deterioration in image quality such as display flow, flicker, and crosstalk due to the FRC pattern. However, since the FRC method is used, the frequency of the FRC is increased to make the deterioration of the image quality difficult to visually recognize, but the problems of display flow and flicker in the method have not been completely eliminated. For this reason, when receiving and displaying a video signal compressed by the MPEG method, interference between the periodic noise fluctuating in the frame direction and the FRC frequency occurs as a feature of the MPEG method, and the beat components of both appear as low frequencies and are suppressed. However, there is a problem that the image quality noise appears, and it is required that a good image quality display can be obtained even in the case of an MPEG video input.
[0016]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a video display device capable of obtaining a good image quality display even with an MPEG video input.
[0017]
[Means for Solving the Problems]
In order to solve this problem, the present invention detects a motion compensation prediction cycle that fluctuates in a frame direction, which is a characteristic of an MPEG video signal, when an MPEG video is input, and detects the FRC cycle. It is characterized in that it is synchronized or linked with the motion compensation prediction cycle.
[0018]
As a result, it is possible to remove interference between the FRC frequency and the periodic noise due to the MPEG motion compensation, and it is possible to obtain an effect that it is possible to suppress image quality deterioration such as display flow and flicker.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the first aspect of the present invention, a motion compensation prediction cycle at the time of compressing a video signal compressed by the MPEG system is detected, and multi-gradation display is performed using an FRC pattern synchronized or linked to the detection cycle. When an MPEG video is input, a motion compensation prediction cycle that changes in the frame direction, which is a feature of the MPEG video signal, is detected, and the FRC cycle is detected. This has the effect of synchronizing or interlocking with the compensation prediction cycle.
[0020]
According to a second aspect of the present invention, there is provided a motion compensation cycle detecting means for detecting a motion compensation cycle of an MPEG compressed video signal, and an FRC pattern for creating a pattern for turning on and off a display in accordance with the gradation of an input video signal in frame units. Generating means, and a cycle control means for controlling a cycle of a pattern generated by the FRC pattern generating means in accordance with an output of the motion compensation cycle detecting means, wherein when an MPEG video is input, , A motion compensation prediction cycle that varies in the frame direction, which is a feature of an MPEG video signal, is detected, and the FRC cycle is synchronized or linked with the detected motion compensation prediction cycle.
[0021]
According to a third aspect of the present invention, there is provided a storage unit for storing an input video signal for one frame, a subtractor for obtaining a difference between an output of the storage unit and the input video signal, and an output of the subtracter for each frame. And a determination circuit for determining whether the value of the output of the cumulative sum circuit is within a specific range. In this case, an operation of detecting a motion compensation prediction cycle that varies in the frame direction, which is a characteristic of an MPEG video signal, is provided.
[0022]
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
[0023]
(Embodiment 1)
FIG. 1 shows the configuration of a video display apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a motion compensation period detecting means. It has the function of detecting the compensation period. Reference numeral 2 denotes an FRC pattern generation unit, which has an operation of creating a pattern for turning on and off the display in accordance with the gradation of the input video signal in frame units in order to realize multi-gradation display. Reference numeral 3 denotes a period control unit, which has an operation of controlling the period of the pattern generated by the FRC pattern generation unit 2 according to the output of the motion compensation period detection unit 1.
[0024]
Hereinafter, the operation of the video display device configured as described above will be described with reference to FIG. Here, as an example, it is assumed that the motion compensation cycle of the input video signal is an m-frame cycle, and the FRC pattern generating means forms the FRC pattern in n-frame units in order to perform multi-tone display. When an MPEG-compressed video is input, the motion compensation cycle detecting means 1 detects a motion compensation cycle m during MPEG compression as shown in FIG. Next, the cycle control means 3 generates a pulse of the FRC pattern cycle n based on the motion compensation cycle m detected as shown in FIG. Here, even if the FRC cycle n is not completed, an output that coincides with the motion compensation cycle m is generated, as at point T in FIG. As a result, the FRC pattern generating means 2 generates and outputs an FRC pattern in which the input timing of FIG. 2B and the start timing of the first frame pattern of the FRC pattern generated in n-frame units are output. Supplied.
[0025]
The FRC pattern created in this way is synchronized with and linked to the motion compensation cycle of the input video at the time of MPEG compression, and interference between the motion compensation cycle and the FRC cycle can be eliminated.
[0026]
In the above description, the interference between the MPEG motion compensation cycle and the FRC cycle has been described as an example. However, the same applies to the interference between the MPEG motion compensation cycle and the cycle when error diffusion is performed in the frame direction for bit reduction. It is feasible.
[0027]
(Embodiment 2)
FIG. 3 shows a configuration of a video display device according to a second embodiment of the present invention. In FIG. 3, reference numeral 4 denotes storage means for storing one frame of the input video signal. Reference numeral 5 denotes a subtractor that calculates the difference between the output of the storage unit 4 and the input video signal. Reference numeral 6 denotes a cumulative sum circuit that calculates the cumulative sum of the output of the subtracter 5 on a frame basis. Numeral 7 denotes a judgment circuit for judging whether the value of the output of the accumulative sum circuit 6 is within a specific range, and 4 to 7 constitute the motion compensation period detecting means 1. Further, the FRC pattern generation means 2 and the cycle control means 3 perform the same configuration and operation as in the first embodiment.
[0028]
Hereinafter, the operation of the video display device configured as described above will be described. Since the storage unit 4 outputs the video signal input one frame before, the subtracter 5 obtains the difference between the video signal of one frame before and the current frame. This difference is calculated by a cumulative sum circuit 6 for a pixel of one frame. FIG. 4 shows the output of the accumulation circuit 6. As described above, the I picture that is periodically arranged as a relationship between the motion compensation and the compression rate that has been MPEG-compressed has a lower compression rate than other B and P pictures. Therefore, as shown in FIG. 4, before and after the I picture, a tendency is obtained that the cumulative sum of the difference between the video signals between the frames is larger than the difference in the compression ratio. Therefore, the cycle determination circuit 7 determines whether the output of the accumulative sum circuit 6 is greater than or less than the threshold value L in FIG. 4 to determine and detect the timing of an I picture that is periodically present and has a low compression ratio. As a result, it is possible to detect the motion compensation period when the input video is compressed by MPEG.
[0029]
Here, the operations of the FRC pattern generation means 2 and the cycle control means 3 are the same as in the first embodiment, and a description thereof will be omitted. However, the above operation makes it possible to detect the motion compensation cycle during the MPEG compression of the input video. , An FRC pattern synchronized with and linked to this is created. The FRC pattern created in this way is synchronized with and linked to the motion compensation cycle of the input video at the time of MPEG compression, and interference between the motion compensation cycle and the FRC cycle can be eliminated.
[0030]
【The invention's effect】
As described above, according to the present invention, it is possible to remove the interference between the FRC frequency and the periodic noise due to the MPEG motion compensation, and to suppress the deterioration of the image quality such as display flow and flicker. The effect is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a video display device according to a first embodiment of the present invention. FIG. 2 is a timing chart of an FRC cycle and a motion compensation cycle in the first embodiment of the present invention. FIG. 4 is a block diagram illustrating a configuration of a video display device according to a second embodiment of the present invention. FIG. 4 is a timing chart illustrating an operation of a motion compensation period detecting unit according to the second embodiment of the present invention. FIG. 6 is a block diagram showing the configuration of a video display device. FIG. 6 is a diagram showing a transition table showing the operation of a conventional video display device. FIG. 7 is a correlation diagram showing an example of a motion compensation prediction structure in the MPEG system.
REFERENCE SIGNS LIST 1 motion compensation cycle detecting means 2 FRC pattern generating means 3 cycle controlling means 4 one frame video storage means 5 subtractor 6 accumulative sum circuit 7 cycle determining circuit 111 FRC pattern generating means 112 gradation pulse generating means 113 display pulse selecting circuit 114 liquid crystal panel

Claims (3)

A video display device comprising: detecting a motion compensation prediction cycle at the time of compression of a video signal compressed by the MPEG system; and performing multi-tone display by using an FRC pattern synchronized with or linked to the detection cycle. Motion compensation cycle detection means for detecting a motion compensation cycle of an MPEG compressed video signal; FRC pattern generation means for creating a pattern for turning on and off a display in units of frames in accordance with a gradation of an input video signal; 2. The video display device according to claim 1, further comprising: a period control unit for controlling a period of a pattern generated by said FRC pattern generation unit in accordance with an output of said unit. The motion compensation period detection means includes a storage means for storing the input video signal for one frame, a subtractor for obtaining a difference between an output of the storage means and the input video signal, and an accumulator for accumulating the subtractor output for each frame. 3. The video display device according to claim 2, comprising a cumulative sum circuit for calculating a sum, and a determining circuit for determining whether a value of the cumulative sum circuit output is within a specific range.

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