JP2004112376A - Electronic circuit and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the transitional continuation of the oscillation of a TCXO (temperature compensated crystal oscillator) caused by the feedback of a residual voltage of a buffer circuit inputted to a power line of the TCXO that occurs when turning off the power of the TCXO when not used to suppress constant power consumption, to reduce power consumption. <P>SOLUTION: While the power of a buffer circuit 6 is kept turned on irrespective of the on or off of the power of the TCXO 1, a control unit 8 controls a switch 2 to cut off the power to the TCXO 1, and simultaneously controls a switch 7 to pull up an input to the buffer circuit 6. As a result, an output from the buffer circuit 6 is forcibly fixed at a voltage level corresponding to a logic value of zero which prevents the feedback of the residual voltage at the input terminal of the buffer circuit 6 to the power line of the TCXO 1 and minimizes the power consumption of the buffer circuit 6 in terms of series connection. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electronic circuit and an electronic device, and more particularly to an electronic circuit that controls the output level of a subsequent stage to a constant value when a power source of a preceding stage is turned off to achieve stable operation and power saving, and to use the electronic circuit. Related to electronic equipment.
[0002]
[Prior art]
Power saving is required for any electronic device, but especially for portable electronic devices represented by portable wireless communication devices, one of the most important technical issues that affect continuous operation time and battery life It is. To solve this problem, it is essential to reduce the power consumption of individual components and circuits. Above all, a temperature-compensated crystal oscillator (hereafter, commonly used as a reference signal source) often used as a reference signal source for such electronic equipment TCXO) and a buffer circuit provided in the subsequent stage have a large specific gravity in terms of power consumption, and thus various ideas have been devised.
[0003]
The problem is that the power consumption of the TCXO itself has a relatively large steady value during operation. Therefore, countermeasures such as turning off the power of the TCXO except for the reception operation are generally taken. However, if the power supply of the buffer circuit that drives the capacitive load is also turned on / off when the power supply of the TCXO is turned on / off, another problem occurs in that the transient current increases.
[0004]
In the case of a circuit configuration in which the TCXO and the buffer circuit and the load circuit share a power supply line, there is the following problem. That is, when the power is turned off, the time constant of the non-zero DC voltage drop remaining at the input terminal of the buffer circuit is larger than the time constant of the drop of the power supply voltage supplied to the TCXO or the like. The residual voltage may be fed back from the load circuit to the power supply line of the TCXO via the common power supply line, and a phenomenon may occur in which the oscillation of the TCXO, which should be immediately stopped, continues for a certain period of time. An example of such a phenomenon will be described later with reference to FIG.
[0005]
The invention disclosed in Patent Document 1 has been made to avoid an increase in transient current due to driving of a capacitive load at the time of power on / off, among the problems described above, and is a non-feedback type buffer circuit. The input / output of the buffer circuit is turned on / off by a switch circuit provided at the input terminal of (1), thereby switching the operation / non-operation state of the buffer circuit without turning on / off the power supply.
[0006]
[Patent Document 1]
JP-A-9-294065 (pages 2-3, FIG. 3)
[0007]
[Problems to be solved by the invention]
According to the above-described conventional technique, when the power supply of a circuit (TCXO or the like) at the preceding stage is turned off, only the input to the buffer circuit is turned off by a switch circuit provided at the input end of the buffer circuit. This is not a countermeasure against the problem that the non-zero DC voltage remaining at the input end is fed back to the power supply line of the TCXO via the load circuit.
[0008]
Therefore, the present invention provides an electronic circuit capable of reducing a transient power consumption caused by a residual voltage at a subsequent circuit input being fed back to a power supply line of a preceding circuit when a power supply of a preceding circuit is turned off. And an electronic device using the same.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, an electronic circuit according to the present invention includes a first partial circuit that generates and / or outputs an electric signal when a power is turned on, and a first partial circuit connected to a stage subsequent to the first partial circuit. A second partial circuit that amplifies the electric signal when it is input and outputs it as a buffer, and a second partial circuit when the power of the first partial circuit is turned off. Control means for controlling the second partial circuit so that the output voltage of the second partial circuit is made equal to a certain DC voltage level. According to the present invention, when the power supply of the preceding circuit is turned off, the output of the buffer circuit is forced to take a certain level, and the power consumption due to the transient feedback phenomenon to the power supply line of the preceding circuit is reduced. Can be suppressed.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of an electronic circuit according to the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram of an electronic circuit according to the present embodiment. 1A and 1B, reference numeral 1 denotes a TCXO, 10 denotes an output terminal of the TCXO1, 2 denotes a power ON / OFF switch of the TCXO1, and 3 denotes a DC cutoff between the TCXO1 and a buffer circuit 6 described later. And a capacitor for AC connection, 4 is an inverter as a digital logic gate having a negative logic function, 41 is an input terminal of the inverter 4, 42 is an output terminal of the inverter 4, and 43 is a power supply of the inverter 4. A terminal 5 is a feedback resistor for causing the inverter 4 to function as an analog amplifier, as will be described later. A buffer circuit 6 is composed of the inverter 4 and the feedback resistor 5. A 7 is for turning on / off an input pull-up of the buffer circuit 6. A switch 8 is a control unit for controlling ON / OFF of each of the switches 2 and 7, and 9 is a capacitor for stabilizing the power supply voltage of the TCXO1. Is another.
[0011]
5A and 5B show a circuit including an NPN transistor and a peripheral resistor as a part of a load circuit connected to the subsequent stage of the buffer circuit 6. FIG. That is, 11 is a transistor, 12 is a base input resistance, 13 is a base ground resistance, and 14 is a collector series resistance. Further, the output of the buffer circuit 6 may be connected in parallel to another load circuit not shown in this figure.
[0012]
Here, the inverter 4 is generally formed of a complementary MOS (CMOS). In this case, by connecting the input terminal 41 and the output terminal 42 via the feedback resistor 5, the logic “0” is obtained. Alternatively, it functions not as a digital circuit that outputs a discrete binary voltage level corresponding to logic "1" but as an analog amplifier, and its gain is determined by the characteristics of the inverter 4 and the resistance value of the feedback resistor 5. ,well known. Also in the present embodiment, the buffer circuit 6 is configured using this technique.
[0013]
1A shows a state where the switch 2 is turned on and the switch 7 is turned off under the control of the control unit 8, and FIG. 1B shows a state where the switch 2 is turned off and the switch 7 is turned off under the control of the control unit 8. Indicates a state in which is turned on. The control unit 8 individually or interlocks the power supply voltage V1 supplied to the TCXO1 and the presence / absence of the input pull-up of the buffer circuit 6 by turning on / off the switch 2 and the switch 7 individually or interlocked. Can be turned on / off. It is also assumed that the power supply voltage V2 is supplied to the buffer circuit 6 and the subsequent stage regardless of whether the power supply voltage V1 of the TCXO1 is on or off.
[0014]
On the other hand, FIG. 2 is a circuit diagram in the case where the TCXO 1 and the buffer circuit 6 and the power supply voltage at the subsequent stage are configured to be commonly turned on / off by turning on / off the switch 2 without distinction. It is shown for the purpose. Since the input pull-up of the buffer circuit 6 is not necessary in this case, the switch 7 in FIG. 1 is omitted, and the power supply connection of the buffer circuit 6 and the subsequent stage is made common to that of the TCXO1. Are all common with FIG.
[0015]
Next, the operation of the electronic circuit according to the embodiment of the present invention will be described with reference to these drawings. For convenience of explanation, first, a phenomenon that occurs immediately after the power supply voltage V1 of the TCXO1 is turned off in the configuration of FIG. 2 and its problem are described, and it is shown that the configuration of FIG. 1 solves the problem.
[0016]
First, a steady operation in a state where the switch 2 is turned on in FIG. 2 will be described. In this state, the power supply voltage V1 is supplied to the TCXO1, and the reference frequency signal is continuously output from the output terminal 10 of the TCXO1. On the other hand, the input terminal 41 of the inverter 4 which is the input terminal of the succeeding buffer circuit 6 is connected to the output terminal 42 via the feedback resistor 5, and is DC equivalent to both logic "0" and logic "1". Not biased to intermediate voltage levels. The AC component of the reference frequency signal from the output terminal 10 of the TCXO 1 is input to the buffer circuit 6 via the capacitor 3 (that is, to the input terminal 41 of the inverter 4). The signal is amplified based on the gain determined by the resistance value, output to the output terminal 42 of the inverter 4, and supplied to the load circuit including the transistor 11 and the resistors 11 to 13 at the subsequent stage and to other load circuits.
[0017]
Here, it is assumed that the switch 2 is turned off under the control of the control unit 8, and the subsequent operation will be described. In this case, the power supply voltage applied to the TCXO 11, the inverter 4, and the collector series resistor 13 decreases with a certain time constant determined by the value of the power supply voltage stabilizing capacitor 9, and the like. On the other hand, the bias voltage immediately before the input terminal 41 of the inverter 4 remains at the input terminal 41 immediately after the switch 2 is turned off, and when the input impedance of the input terminal 41 is high, the speed of the decrease is as follows. The power supply voltage applied to the TCXO 11, the inverter 4, and the collector series resistor 13 may be slower than the speed at which the power supply voltage decreases.
[0018]
Then, the residual voltage of the input terminal 41 is applied to the base of the transistor 11 via the feedback resistor 5 and the base input resistor 12. On the other hand, the collector voltage of the transistor 11 is in a floating state because the connection with the original power supply line is cut off. Therefore, when the base voltage is applied, the base-collector is forward biased, and the collector voltage becomes Follows the base voltage. This collector voltage is applied to the TCXO1 which shares the power supply line, and the TCXO1 keeps oscillating until it becomes zero, which results in the consumption of power.
[0019]
In the embodiment of the present invention shown in FIG. 1, the above problem can be solved as follows. First, the operation in the steady state shown in FIG. 1A is the same as the operation before the switch 2 is turned off in FIG. Here, the power supply voltage V1 of the TCXO1 and the power supply voltage V2 of the buffer circuit 6 are separated, and the control unit 8 turns off the switch 2 and turns on the switch 7 at the same time.
[0020]
Thus, when the switch 2 is turned off, the voltage level of the input terminal of the buffer circuit 4 (the input terminal 41 of the inverter 4) is pulled up to the power supply voltage V2, and the output voltage of the inverter 4 which is the output terminal of the buffer circuit 6 is The output of output terminal 42 is fixed at a voltage level corresponding to logic "0" (ground signal level in the present embodiment). Therefore, there is no forward bias between the base and the collector, and the above-mentioned problem that may occur in the configuration of FIG. 2 is solved.
[0021]
According to the above-described embodiment of the present invention, the residual voltage of input terminal 41 is not fed back as the power supply voltage of TCXO1, and inverter 4 is also the most direct current CMOS digital logic gate for power consumption. Is fixed to a small state.
[0022]
The above-described embodiment of the present invention is an example, and the preceding circuit is not limited to the TCXO, but may be another oscillation circuit or a preceding amplifier circuit. Further, the buffer circuit in the subsequent stage is not limited to a circuit in which a CMOS digital logic gate has a feedback loop. This is because, depending on the circuit configuration used, the input may be pulled up or down or fixed to a certain DC level so as to minimize DC power consumption.
[0023]
In addition, the control of the power supply voltage V1 is performed by opening and closing the switch 2 inserted in series with the power supply line, but may be controlled by another method, for example, a method of turning on / off the power supply itself for the preceding circuit. . Even in such a case, if the time constant of the drop of the power supply voltage V1 is smaller than the time constant of the residual voltage effect of the buffer circuit input, the forcible fixation of the input of the subsequent buffer circuit at the same time as the turning off of the power supply voltage V1 This is because it is effective as in the case of the described embodiment of the present invention. In addition, the present invention works effectively for any load circuit as long as there is a possibility that the input voltage from the preceding buffer circuit may flow to the power supply line when the power supply is turned off.
[0024]
【The invention's effect】
According to the present invention, when the power supply of the preceding circuit is turned off, the transient power consumption caused by the voltage feedback from the subsequent circuit to the power supply line of the preceding circuit is minimized, and the subsequent , The steady power consumption of the circuit itself can be minimized, and power saving of an electronic device using the electronic circuit having this configuration can be achieved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an electronic circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of an electronic circuit in a case where control of a buffer circuit according to an embodiment of the present invention is not performed.
[Explanation of symbols]
1 TCXO
11 TCXO output terminal 2 TCXO power ON / OFF switch 3 Capacitor 4 Inverter 41 Inverter input terminal 42 Inverter output terminal 43 Inverter power supply terminal 5 Feedback resistor 6 Buffer circuit 7 Buffer circuit input pull-up ON / OFF Switch 8 Control unit 9 TCXO power supply voltage stabilizing capacitor 10 TCXO output terminal 11 Transistor 12 Base input resistance 13 Base ground resistance 14 Collector series resistance

Claims (6)

A first sub-circuit that generates and / or outputs an electric signal when the power is turned on;
A second partial circuit that is connected to a stage subsequent to the first partial circuit and that amplifies the electric signal and / or outputs it as a buffer when the electric signal is input;
Control means for controlling the second partial circuit so that the output voltage of the second partial circuit is made equal to a certain DC voltage level when the power of the first partial circuit is turned off. An electronic circuit, comprising: The control means controls the second partial circuit so that when the power supply of the first partial circuit is turned off, the output voltage of the second partial circuit becomes equal to the ground signal level. The electronic circuit according to claim 1, wherein: 3. The electronic circuit according to claim 1, wherein the first partial circuit is a crystal oscillation circuit or a temperature-compensated crystal oscillation circuit. In an electronic device having means for generating and / or amplifying and transmitting an electric signal, the means for generating, or amplifying and transmitting the electric signal includes:
A first sub-circuit that generates and / or outputs an electric signal when the power is turned on;
A second partial circuit that is connected to a stage subsequent to the first partial circuit and that amplifies the electric signal and / or outputs it as a buffer when the electric signal is input;
Control means for controlling the second partial circuit so that the output voltage of the second partial circuit is made equal to a certain DC voltage level when the power of the first partial circuit is turned off. An electronic device, comprising: The control means controls the second partial circuit so that when the power supply of the first partial circuit is turned off, the output voltage of the second partial circuit becomes equal to the ground signal level. The electronic device according to claim 4, wherein: The electronic device according to claim 4, wherein the first partial circuit is a crystal oscillation circuit or a temperature-compensated crystal oscillation circuit.

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