JP2004112288A - Cross polarized wave interference compensation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shift a cross polarized wave interference compensation circuit to a reset state without causing deterioration in the characteristics of a bit rate by poorly affecting the control of other circuits in digital microwave communication equipment when the cross polarized wave interference compensation circuit is reset. <P>SOLUTION: The cross polarized wave interference compensation circuit (XPIC circuit) comprises: a transversal filter 7 that generates an XPIC signal for canceling a different polarized wave side signal leaking out to an own polarized wave side signal according to a tap coefficient for outputting; and a tap coefficient generation circuit 8 that generates the tap coefficient of the transversal filter 7 according to the correlation between an error signal for indicating deviation from a specific lattice point in the own polarized wave side signal and I channel and Q channel signals at a different polarized wave side, and gradually brings the tap coefficient close to 0 in the input of an XPIC reset signal indicating the switching of the XPIC circuit to a reset state. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a cross polarization interference compensation circuit (XPIC) provided in a digital microwave communication apparatus of a dual polarization transmission system using two polarizations orthogonal to each other, and more particularly to a cross polarization interference canceller (XPIC) generated at reset. The present invention relates to a cross-polarization interference compensating circuit for preventing deterioration of a bit error rate characteristic.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a digital microwave communication apparatus, a dual-polarization transmission system for transmitting a signal using two orthogonal polarizations (self-polarization and different polarizations) having the same frequency has been used. In this dual-polarization transmission system, a cross-polarization interference compensating circuit (hereinafter referred to as an XPIC circuit) is provided to compensate for a cross-polarization interference component caused by a different polarization side signal leaked into the own polarization side signal. ) Is provided (for example, Patent Document 1).
[0003]
As an example of the XPIC circuit, a transversal filter that generates a cross-polarization interference compensation signal (hereinafter, referred to as an XPIC signal) that cancels a cross-polarization interference component in a signal on the own polarization side, and an XPIC output from the transversal filter And a tap coefficient generation circuit for generating a tap coefficient capable of canceling a cross-polarized interference component in the self-deviation side signal by a signal. In this XPIC circuit, an XPIC signal is generated by a transversal filter based on tap coefficients.
[0004]
Incidentally, the XPIC circuit is configured to be shifted to a reset state when not in use or during maintenance. As an example, a reset signal is input to a circuit corresponding to a tap coefficient generation circuit, and the output of the circuit is controlled. There is a configuration in which the XPIC circuit is reset due to this (for example, Patent Document 2). In Patent Document 2, there is no detailed description of the configuration of a control signal generation circuit corresponding to a tap coefficient generation circuit. However, a general tap coefficient generation circuit generates a tap coefficient using an up / down counter. It is configured as follows. FIG. 10 shows only the configuration of a tap controller, which is a part that actually generates tap coefficients, of the entire configuration of the tap coefficient generation circuit provided in the conventional XPIC circuit.
[0005]
The tap controller shown in FIG. 10 includes a correlator 22 that calculates a correlation between an error signal indicating a deviation of a data signal on the self-polarization side from a predetermined lattice point and a data signal on the different polarization side, and a correlator 22. , Performs a count-up or count-down operation in accordance with the calculation result, and an up-down counter 23 whose count value becomes an XPIC signal.
[0006]
The tap controller shown in FIG. 10 has a configuration in which a reset signal (XPIC reset signal) is directly input to the up / down counter 23. Therefore, at the moment when the XPIC reset signal is input to the up / down counter 23, the tap coefficient is immediately reset to 0, whereby the output of the XPIC signal output from the transversal filter suddenly changes to 0.
[0007]
[Patent Document 1]
JP 2000-165339 A
[Patent Document 2]
JP 05-122189 A
[0008]
[Problems to be solved by the invention]
However, in the conventional XPIC circuit, a sudden change in the output of the XPIC signal at the moment of resetting causes a deviation from the optimum control point in the control of other circuits in the digital microwave communication apparatus. Until the control point is converged, there is a problem that the bit error rate characteristics deteriorate.
[0009]
Therefore, an object of the present invention is to prevent the bit error rate characteristic from deteriorating by adversely affecting the control of other circuits in the digital microwave communication device when the cross polarization interference compensation circuit is switched to the reset state. An object of the present invention is to provide a cross polarization interference compensation circuit capable of shifting a cross polarization interference compensation circuit to a reset state.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a cross polarization interference compensation circuit of the present invention is provided.
In a cross-polarization interference compensation circuit provided in a digital microwave communication device of a dual polarization transmission system using self-polarization and different polarization orthogonal to each other,
A transversal filter that generates and outputs a cross-polarization interference compensation signal that cancels out the different polarization side signal leaked into the own polarization side signal according to the tap coefficient,
The tap coefficient is generated in accordance with a correlation between an error signal indicating a deviation of the self-polarization side signal from a predetermined lattice point and the different polarization side signal, and the cross polarization interference compensation circuit is switched to a reset state. Tap coefficient generating means for gradually bringing the tap coefficient closer to 0 when the tap coefficient is given.
[0011]
More specifically, the tap coefficient generation means includes:
An up-down counter that performs a count-up or count-down operation and generates the tap coefficient based on the count value;
Correlation means for calculating a correlation between the error signal representing the deviation from a predetermined lattice point of the self-polarization side signal and the different polarization side signal, and generating a signal according to the calculation result,
Counter control means for generating a signal for switching the polarity of count-up / count-down of the up-down counter when the cross-polarization interference compensation circuit is switched to a reset state,
The up-down counter performs a count-up or count-down operation in accordance with the polarity of the signal generated by the correlating means when the cross polarization interference compensation circuit is switched to a non-reset state. When the wave interference compensation circuit is switched to the reset state, the polarity of the count-up / count-down is switched according to the signal generated by the counter control means, and the count operation of the count-up or count-down is performed until the count value becomes zero. It is characterized by performing.
[0012]
According to the configuration described above, when the cross polarization interference compensation circuit is switched to the reset state, the tap coefficient output from the tap coefficient generation unit gradually approaches 0, and is output from the transversal filter. The cross polarization interference compensation signal will gradually approach zero. Therefore, when the cross polarization interference compensation circuit is switched to the reset state, the control of the other circuits in the digital microwave communication device is not adversely affected and the bit error rate characteristics are not deteriorated. Can be shifted to the reset state.
[0013]
The transversal filter and the transversal filter are used to generate cross polarization interference compensation signals for canceling different polarization side signals leaked into each of two orthogonal baseband signals of the self polarization side signal. Two sets of tap coefficient generation means are provided.
[0014]
In order to achieve the above object, a cross-polarization interference compensation circuit according to another aspect of the present invention is provided in a digital microwave communication device of a dual polarization transmission system using self-polarization and hetero-polarization orthogonal to each other. In the cross polarization interference compensation circuit,
A transversal filter that generates a signal for canceling the different polarization side signal leaked into the own polarization side signal according to the tap coefficient,
The tap coefficient is generated in accordance with a correlation between an error signal indicating a deviation of the self-polarization side signal from a predetermined lattice point and the different polarization side signal, and the cross polarization interference compensation circuit is switched to a reset state. Tap coefficient generating means for holding the tap coefficient at that point in time,
Output control means for generating a signal that gradually approaches 0 when the cross polarization interference compensation circuit is switched to a reset state;
Multiplication means for multiplying an output signal of the transversal filter by an output signal of the output control means and outputting a result of the multiplication as a cross polarization interference compensation signal.
[0015]
More specifically, the tap coefficient generation means includes:
An up-down counter that performs a count-up or count-down operation and generates the tap coefficient based on the count value;
Correlation means for calculating a correlation between an error signal indicating a deviation from a predetermined lattice point of the self-polarization side signal and the different polarization side signal, and generating a signal according to the calculation result,
The up-down counter performs a count-up or count-down operation in accordance with the polarity of the signal generated by the correlating means when the cross polarization interference compensation circuit is switched to a non-reset state. When the wave interference compensation circuit is switched to the reset state, the counting operation is stopped and the count value at that time is held,
The output control means presets a count value to 1.0 when the cross polarization interference compensation circuit is switched to the non-reset state, and counts a count value when the cross polarization interference compensation circuit is switched to the reset state. A down counter that counts down to zero, outputs a signal representing the count value of the down counter to the multiplying means, and counts the count value of the up / down counter when the count value of the down counter becomes zero. The value is set to 0.
[0016]
According to the above configuration, when the cross polarization interference compensation circuit is switched to the reset state, the output of the output control means gradually approaches 0, and the output is multiplied by the output of the transversal filter. Is output as a cross-polarization interference compensation signal, so that the cross-polarization interference compensation signal gradually approaches zero. Therefore, when the cross polarization interference compensation circuit is switched to the reset state, the control of the other circuits in the digital microwave communication device is not adversely affected and the bit error rate characteristics are not deteriorated. Can be shifted to the reset state.
[0017]
In addition, in order to generate cross polarization interference compensation signals for canceling different polarization side signals leaked into each of two orthogonal baseband signals of the self polarization side signal, the transversal filter, Two sets of tap coefficient generation means, the output control means, and the multiplication means are provided.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0019]
(1st Embodiment)
FIG. 1 is a diagram illustrating a configuration example of a demodulation device of a digital microwave communication device using a cross polarization interference compensation circuit (hereinafter, referred to as an XPIC circuit) 3 of the present invention. This demodulator is assumed to be a quadrature amplitude modulation (QAM) demodulator.
[0020]
The demodulator shown in FIG. 1 includes two A / D converters 1, two quadrature detectors 2, an XPIC circuit 3, two adders 4, an AGC (Auto Gain Control) circuit 5, And a detection circuit 6. The demodulator shown in FIG. 1 includes means for establishing clock synchronization and carrier synchronization, but these are omitted.
[0021]
The A / D converter 1 converts an XIF signal, which is an intermediate frequency (IF) signal on the self-polarization side or a reference IF signal on the different polarization side, from an analog signal in order to perform subsequent processing digitally. It has the function of converting to digital signals.
[0022]
The quadrature detector 2 has a function of converting the IF signal or the XIF signal input from the A / D converter 1 into two quadrature components (baseband signals). Hereinafter, the two orthogonal components are referred to as an Ich signal and a Qch signal as generally called. Since the quadrature detector 2 is not directly related to the function of the present invention, detailed description is omitted.
[0023]
Note that the configuration shown in FIG. 1 is, for example, a configuration in which an A / D converter 1 converts an IF signal or an XIF signal into a digital signal and then performs quadrature detection with a quadrature detector 2. It is also possible to adopt a configuration in which an IF signal or an XIF signal is orthogonally detected by a quadrature detector and then converted into a digital signal by an A / D converter. Changing the order of these parts has no effect on the effect of the present invention.
[0024]
The XPIC circuit 3 calculates the correlation between the Ich signal and the Qch signal input from the quadrature detector 2 on the different polarization side and the error signal input from the error detector 6, respectively. A cross polarization interference compensation signal that judges that the different polarization side signal leaks into the wave side signal and becomes a cross polarization interference component, and cancels the cross polarization interference component in the own polarization side signal independently. (Hereinafter referred to as an XPIC signal), and is reset by an externally input XPIC reset signal.
[0025]
The adder 4 adds the XPIC signal input from the XPIC circuit 3 to the Ich signal or Qch signal input from the quadrature detector 2 on the self-polarization side, and generates a cross polarization interference component in the self-polarization side signal. It has a function to cancel out.
[0026]
The AGC circuit 5 has a function of independently adjusting the gains of the Ich signal and the Qch signal input from the adder 4 so that the Ich signal and the Qch signal are on predetermined lattice points. The AGC circuit 5 adjusts the gain based on the error signal from the error detection circuit 6. Therefore, at each point of the output signal points of the AGC circuit 5, control is performed such that the average value is on the grid point, but detailed description is omitted.
[0027]
The error detection circuit 6 has a function of determining a deviation from a predetermined grid point at each of the output signal points of the AGC circuit 5. The error detection circuit 6 makes an independent determination on the Ich signal and the Qch signal, and outputs each determination result to the XPIC circuit 3 and the AGC circuit 5 as an error signal.
[0028]
Here, the configuration of the XPIC circuit 3 will be described in detail. In the following description, of the entire configuration of the XPIC circuit 3, only the configuration of the output portion of the Ich-side XPIC signal is illustrated and described, and the output portion of the Qch-side XPIC signal has the same configuration. Is omitted.
[0029]
FIG. 2 is a diagram showing the XPIC circuit 3 according to the first embodiment of the present invention, and shows only a configuration of an output portion of the Ich-side XPIC signal.
[0030]
The XPIC circuit 3 shown in FIG. 2 includes a transversal filter 7 that generates an Ich-side XPIC signal, and a tap coefficient generation circuit 8 that generates a tap coefficient of the transversal filter 7. The XPIC circuit 3 shown in FIG. 2 includes a transversal filter and a tap coefficient generation circuit equivalent to those in FIG. 2 at the output portion of the Qch-side XPIC signal, but these are omitted.
[0031]
FIG. 3 is a diagram illustrating a configuration example of the transversal filter 7 illustrated in FIG. Here, a transposed filter configuration is shown as an example.
[0032]
The transversal filter 7 shown in FIG. 3 converts the in-phase component data signal (Ich-side data signal) and the quadrature component data signal (Qch-side data signal) input from the quadrature detector 2 on the different polarization side. The output of each filter is added. That is, the transversal filter 7 includes a multiplier 9 that multiplies the tap coefficient C input from the tap coefficient generation circuit 8 by the data signal input from the quadrature detector 2 on the different polarization side, and a multiplication result of the multiplier 9. And a flip-flop (FF) 11 for delaying the addition result of the adder 10 by one sampling period (1T). Since the details of the operation of the transversal filter 7 are generally known, a detailed description will be omitted.
[0033]
FIG. 4 is a diagram illustrating a configuration example of the tap coefficient generation circuit 8 illustrated in FIG.
[0034]
The tap coefficient generation circuit 8 shown in FIG. 4 converts the tap coefficient C that can cancel the cross polarization interference component in the self-deviation side signal by the output of the transversal filter 7 into a quadrature detector on the different polarization side. 2 is generated based on the in-phase component data signal (Ich-side data signal) and the quadrature component data signal (Qch-side data signal) input from 2 and the Ich-side error signal input from the error detection circuit 6. Has become. That is, the tap coefficient generation circuit 8 includes a flip-flop 13, a shift register that shifts the data signal input from the quadrature detector 2 on the different polarization side every 1T, and a tap controller 12 that generates a tap coefficient C. It is composed of
[0035]
In the tap coefficient generation circuit 8, a continuous data signal sequence for a certain period on the different polarization side is prepared by the shift register, the correlation between each data signal sequence and the error signal is calculated, and the correlated tap coefficient C is calculated. Grows. Then, the transversal filter 7 generates an XPIC signal based on the tap coefficient C.
[0036]
Here, the configuration of the tap controller 12 will be described in detail.
[0037]
FIG. 5 is a diagram illustrating a configuration example of the tap controller 12 illustrated in FIG.
[0038]
The tap controller 12 shown in FIG. 5 is different from the data signal of the in-phase component (the data signal on the Ich side) and the data signal of the quadrature component (the data signal on the Qch side) input from the quadrature detector 2 on the different polarization side in error. It comprises a correlator 14 for obtaining a correlation with the Ich-side error signal input from the detection circuit 6, an up / down counter 17 for generating a tap coefficient C, a selector (SEL) 15, and a counter control circuit 16. .
[0039]
The correlator 14 calculates the correlation between the data signal input from the quadrature detector 2 on the different polarization side and the Ich error signal input from the error detector 6, and compares the calculation result with an up / down counter. It outputs to 17 up-down inputs.
[0040]
The up-down counter 17 counts up or down according to the polarity of the signal input from the correlator 14 to the up-down input via the selector 15, and the output value of the counter becomes the tap coefficient C. Here, it is assumed that the count-up is performed when the up-down input is H, and the count-down is performed when the up-down input is L. When the counter reset signal input to the reset input is L (reset state), the counter output is reset to 0.
[0041]
The selector 15 selects the output of the correlator 14 when the XPIC reset signal is H, that is, in the non-reset state, and outputs it to the up-down input of the up-down counter 17, and when the XPIC reset signal is L, that is, in the reset state. The output of the counter control circuit 16 is selected and output to the up / down input of the up / down counter 17.
[0042]
When the XPIC reset signal is H, the counter control circuit 16 sets the counter reset signal to H (non-reset state) and outputs it to the reset input of the up / down counter 17, and when the XPIC reset signal becomes L, the up / down counter If the counter output of 17 is other than 0, the polarity of the count-up / count-down of the up / down counter is switched according to the polarity. That is, when the counter output of the up / down counter 17 is positive, L (count down) is output to the selector 15 when the counter output is negative, and H (count up) is output. When the counter output of the up / down counter 17 becomes 0, the counter reset signal is set to L (reset state) and output to the reset input of the up / down counter 17.
[0043]
Hereinafter, the operation of the XPIC circuit 3 according to the present embodiment will be described.
[0044]
When the cross-polarization interference component leaks into the self-deviation side signal, the error signal generated by the error detection circuit 6 is affected by the cross-polarization interference component. There is a correlation between the error signal and the different polarization side signal. Therefore, in the XPIC circuit 3, the tap coefficient C at the position where the correlation can be obtained grows, and based on the tap coefficient C, the XPIC signal for canceling the cross polarization interference component from the self-deviation side signal is generated. Then, in the adder 4, the XPIC signal generated by the XPIC circuit 3 is added to the self-deviation side signal, so that the bit error characteristic deterioration due to the cross polarization interference component can be improved.
[0045]
Since the operation of the XPIC circuit 3 is disclosed in, for example, the above-mentioned Patent Document 1, the operation when the XPIC circuit 3 is reset will be described in detail below. Here, as a precondition, it is assumed that a certain degree of cross polarization interference component is leaked into the self-deviation side signal, and an XPIC signal for canceling the cross polarization interference component is output from the XPIC circuit 3. .
[0046]
FIG. 6 is a time chart for explaining the operation of each component shown in FIG.
[0047]
At time t1, when the XPIC circuit 3 is in the non-reset state, that is, when the XPIC reset signal is at the H level, the selector 15 selects the output of the correlator 14 and outputs it to the up / down input of the up / down counter 17.
[0048]
Since the counter reset signal output from the counter control circuit 16 to the reset input of the up / down counter 17 is H, the up / down counter 17 performs a normal counting operation. Therefore, in the up / down counter 17, a tap coefficient C corresponding to the output of the correlator 14 is generated.
[0049]
At time t2, when the XPIC circuit 3 is in the reset state, that is, when the XPIC reset signal becomes L, the selector 15 selects the output of the counter control circuit 16 and outputs it to the up / down input of the up / down counter 17. The output of the counter control circuit 16 is a signal L that counts down when the counter output value of the up / down counter 17, that is, the tap coefficient C is a positive value, and a signal H that counts up when the tap coefficient C is a negative value. It becomes. In this state, since the counter output of the up / down counter 17, that is, the tap coefficient C gradually approaches 0, the Ich-side XPIC signal output from the transversal filter 7 gradually approaches 0.
[0050]
At time t3, when the counter output of the up / down counter 17 finally becomes 0, the counter reset signal output from the counter control circuit 16 to the reset input of the up / down counter 17 becomes L. Reset. Thereafter, as long as the XPIC reset signal is at L, the up / down counter 17 does not operate.
[0051]
At time t4, when the XPIC circuit 3 is released from the reset state and the XPIC reset signal becomes H, the output of the correlator 14 is selected by the selector 15 and the reset input of the up-down counter 17 from the counter control circuit 16 is selected. The counter reset signal that is output to H is immediately released and becomes H. Therefore, in the up / down counter 17, the normal counting operation is started immediately at the moment when the XPIC circuit 3 is released from the reset state, and the tap coefficient C according to the output of the correlator 14 starts to be generated.
[0052]
As described above, in the present embodiment, when the XPIC circuit 3 is switched to the reset state, the tap coefficient output from the tap coefficient generation circuit 8 gradually approaches 0, and thus is output from the transversal filter 7. The XPIC signal will gradually approach zero.
[0053]
Therefore, as in the conventional XPIC circuit shown in FIG. 10, the tap coefficient changes suddenly to 0 at the moment when the XPIC circuit is switched to the reset state, and the output of the XPIC signal changes abruptly. The cross polarization interference compensation circuit can be shifted to the reset state without adversely affecting the control of other circuits in the digital microwave communication device and deteriorating the bit error rate characteristics.
[0054]
In the conventional XPIC circuit shown in FIG. 10, when the transversal filter has a configuration as shown in FIG. 3, the data signal remaining in the flip-flop 11 is kept for a while after the tap coefficient is set to 0. Is output. This signal is not sufficient as a compensation signal of the XPIC, but rather has a bad influence on the bit error rate characteristics.
[0055]
(Second embodiment)
The XPIC circuit 3 according to the second embodiment of the present invention is used by being incorporated in a demodulation device of a digital microwave communication device as shown in FIG. 1, as in the first embodiment. In the following description, as in the first embodiment, of the entire configuration of the XPIC circuit 3, only the configuration of the output portion of the Ich-side XPIC signal will be illustrated and described, and the output of the Qch-side XPIC signal will be described. The portions have the same configuration, and thus the description is omitted.
[0056]
FIG. 7 is a diagram showing an XPIC circuit 3 according to the second embodiment of the present invention, and shows only the configuration of an output portion of an Ich-side XPIC signal.
[0057]
The XPIC circuit 3 shown in FIG. 7 is different from the tap coefficient generation circuit 8 in that a tap coefficient generation circuit 18 that differs only in the configuration of a tap controller is provided, and an output controller 19 and an adder 20 are added. This is different from the XPIC circuit shown in FIG. The configuration of the transversal filter 7 is the same as that in FIG. The XPIC circuit 3 shown in FIG. 7 includes a transversal filter, a tap coefficient generation circuit, an output controller, and an adder set equivalent to those in FIG. 7 at the output portion of the Qch-side XPIC signal. Is omitted.
[0058]
FIG. 8 is a diagram illustrating a configuration example of the tap coefficient generation circuit 18 illustrated in FIG.
[0059]
The tap coefficient generation circuit 18 shown in FIG. 8 has an up / down counter 21 having a hold function instead of the up / down counter 17 and a point that the selector 15 and the counter control circuit 16 are deleted. Is different from the tap coefficient generation circuit 8 shown in FIG. The configuration of the correlator 14 is the same as that of FIG.
[0060]
The up / down counter 21 has the hold function as described above, and stops the count operation when the XPIC reset signal is L, that is, in the reset state, and holds the immediately preceding value. The count-up or count-down is performed according to the polarity of the signal directly input from the correlator 14 to the up-down input, and the counter output value becomes the tap coefficient C. Here, it is assumed that the count-up is performed when the up-down input is H, and the count-down is performed when the up-down input is L. When the counter reset signal input to the reset input is L, the counter output is reset to 0 regardless of the polarity of the XPIC reset signal.
[0061]
The output controller 19 is constituted by a down counter. When the XPIC reset signal is H, that is, in a non-reset state, the counter reset signal is set to H (non-reset state), and the up-down counter in the tap coefficient generation circuit 18 21 and a down counter is preset to 1.0. When the XPIC reset signal becomes L, the down counter starts counting down and counts down to 0. When the counter output of the down counter becomes 0, the counter reset signal is set to L (reset state) and output to the reset input of the up / down counter 21 in the tap coefficient generation circuit 18.
[0062]
The multiplier 20 multiplies the output of the transversal filter 7 by the output of the output controller 19, and outputs the multiplication result as an Ich-side XPIC signal.
[0063]
Hereinafter, as an operation of the XPIC circuit 3 according to the present embodiment, an operation when the XPIC circuit 3 is reset will be described. Here, as a precondition, it is assumed that a certain degree of cross polarization interference component is leaked into the self-deviation side signal, and an XPIC signal for canceling the cross polarization interference component is output from the XPIC circuit 3. .
[0064]
FIG. 9 is a time chart for explaining the operation of each component shown in FIG.
[0065]
At time t1, when the XPIC circuit 3 is in the non-reset state, that is, when the XPIC reset signal is at H, the down counter in the output controller 19 is preset to 1.0.
[0066]
Since the counter reset signal output from the output controller 19 to the reset input of the up / down counter 21 is H, the up / down counter 21 performs a normal counting operation. Therefore, in the up / down counter 21, a tap coefficient C corresponding to the output of the correlator 14 is generated.
[0067]
At time t2, when the XPIC circuit 3 is in the reset state, that is, when the XPIC reset signal becomes L, the up / down counter 21 stops the counting operation and holds the previous value.
[0068]
The down counter in the output controller 19 starts a countdown counting operation, and the output of the output controller 19 gradually approaches zero. Since the output of the output controller 19 is multiplied by the output of the transversal filter 7 by the multiplier 20, the Ich-side XPIC signal output from the transversal filter 7 gradually approaches zero.
[0069]
At time t3, when the output of the output controller 19 becomes 0, the counter reset signal output from the output controller 19 to the reset input of the up / down counter 21 becomes L. The value becomes 0.
[0070]
At time t4, when the XPIC circuit 3 is released from the reset state and the XPIC reset signal becomes H, the counter reset signal output from the output controller 19 to the reset input of the up / down counter 21 becomes H, The down counter in the output controller 19 is immediately preset to 1.0, and the hold and reset of the up / down counter 21 are immediately released. Therefore, in the up / down counter 21, the normal counting operation is started immediately at the moment when the XPIC circuit 3 is released from the reset state, and the tap coefficient C according to the output of the correlator 14 starts to be generated, and the convergence state is started. Heading. Therefore, the convergence time of the XPIC circuit 3 is not affected by the newly added circuit.
[0071]
The reason why the up / down counter 21 is held at the moment when the XPIC reset signal becomes L at the time t2 is compensated for when the output value of the Ich-side XPIC signal is narrowed down by the output controller 19 and the multiplier 20 and becomes small. This is because the tap coefficient C further increases, and the XPIC output cannot be gradually reduced.
[0072]
As described above, in the present embodiment, when the XPIC circuit 3 is switched to the reset state, the output of the output controller 19 gradually approaches 0, and this output is multiplied by the output of the transversal filter 7. Is output as an XPIC signal, the XPIC signal gradually approaches 0.
[0073]
Therefore, when the XPIC circuit is switched to the reset state, the cross polarization interference compensation circuit is reset to the reset state without adversely affecting the control of other circuits in the digital microwave communication device and deteriorating the bit error rate characteristics. Can be migrated.
[0074]
【The invention's effect】
As described above, according to the present invention, when the cross-polarization interference compensation circuit is switched to the reset state, the output of the cross-polarization interference compensation signal is gradually brought close to 0. Abruptly changes the output value of the cross polarization interference compensation circuit to the reset state without adversely affecting the control of circuits other than the XPIC circuit and deteriorating the bit error rate characteristics.
[0075]
Further, when the cross polarization interference compensation circuit is switched to the non-reset state, the tap coefficient starts to be generated immediately and goes to the convergence state, so that the present invention affects the convergence time of the cross polarization interference compensation signal. There is no.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a demodulation device of a digital microwave communication device using a cross polarization interference compensation circuit of the present invention.
FIG. 2 is a diagram illustrating a cross polarization interference compensation circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration example of a transversal filter illustrated in FIG. 2;
FIG. 4 is a diagram illustrating a configuration example of a tap coefficient generation circuit illustrated in FIG. 2;
FIG. 5 is a diagram illustrating a configuration example of a tap controller illustrated in FIG. 4;
FIG. 6 is a time chart for explaining the operation of each component shown in FIG. 5;
FIG. 7 is a diagram illustrating an XPIC circuit according to a second embodiment of the present invention.
8 is a diagram illustrating a configuration example of a tap controller provided in the tap coefficient generation circuit illustrated in FIG. 7;
FIG. 9 is a time chart for explaining the operation of each component shown in FIG. 8;
FIG. 10 is a diagram illustrating a configuration example of a conventional tap controller.
[Explanation of symbols]
1 A / D converter
2 Quadrature detector
3 Cross polarization interference compensation circuit (XPIC circuit)
4 Adder
5 AGC circuit
6 Error detection circuit
7 Transversal filter
8 Tap coefficient generation circuit
9 Multiplier
10 Adder
11 flip-flops
12 Tap controller
13 flip-flops
14 Correlator
15 Selector
16 Counter control circuit
17 Up / down counter
18 Tap coefficient generation circuit
19 Output controller
20 adder
21 Up / down counter

Claims (6)

In a cross-polarization interference compensation circuit provided in a digital microwave communication device of a dual polarization transmission system using self-polarization and different polarization orthogonal to each other,
A transversal filter that generates and outputs a cross-polarization interference compensation signal that cancels out the different polarization side signal leaked into the own polarization side signal according to the tap coefficient,
The tap coefficient is generated in accordance with a correlation between an error signal indicating a deviation of the self-polarization side signal from a predetermined lattice point and the different polarization side signal, and the cross polarization interference compensation circuit is switched to a reset state. A tap coefficient generating means for gradually bringing the tap coefficient closer to 0 when the tap coefficient is applied. The tap coefficient generation unit includes:
An up-down counter that performs a count-up or count-down operation and generates the tap coefficient based on the count value;
Correlation means for calculating a correlation between the error signal representing the deviation from a predetermined lattice point of the self-polarization side signal and the different polarization side signal, and generating a signal according to the calculation result,
Counter control means for generating a signal for switching the polarity of count-up / count-down of the up-down counter when the cross-polarization interference compensation circuit is switched to a reset state,
The up-down counter performs a count-up or count-down operation in accordance with the polarity of the signal generated by the correlating means when the cross polarization interference compensation circuit is switched to a non-reset state. When the wave interference compensation circuit is switched to the reset state, the polarity of the count-up / count-down is switched according to the signal generated by the counter control means, and the count operation of the count-up or count-down is performed until the count value becomes zero. The cross polarization interference compensation circuit according to claim 1, which performs the operation. The transversal filter and the tap coefficients for generating cross-polarization interference compensation signals for canceling different polarization side signals leaked into each of two orthogonal baseband signals of the self polarization side signal; 3. The cross polarization interference compensation circuit according to claim 1, wherein two sets of generation means are provided. In a cross-polarization interference compensation circuit provided in a digital microwave communication device of a dual polarization transmission system using self-polarization and different polarization orthogonal to each other,
A transversal filter that generates a signal for canceling the different polarization side signal leaked into the own polarization side signal according to the tap coefficient,
The tap coefficient is generated in accordance with a correlation between an error signal indicating a deviation of the self-polarization side signal from a predetermined lattice point and the different polarization side signal, and the cross polarization interference compensation circuit is switched to a reset state. Tap coefficient generating means for holding the tap coefficient at that point in time,
Output control means for generating a signal that gradually approaches 0 when the cross polarization interference compensation circuit is switched to a reset state;
A cross polarization interference compensation circuit comprising: a multiplication unit that multiplies an output signal of the transversal filter by an output signal of the output control unit and outputs a result of the multiplication as a cross polarization interference compensation signal. The tap coefficient generation unit includes:
An up-down counter that performs a count-up or count-down operation and generates the tap coefficient based on the count value;
Correlation means for calculating a correlation between an error signal indicating a deviation from a predetermined lattice point of the self-polarization side signal and the different polarization side signal, and generating a signal according to the calculation result,
The up-down counter performs a count-up or count-down operation in accordance with the polarity of the signal generated by the correlating means when the cross polarization interference compensation circuit is switched to a non-reset state. When the wave interference compensation circuit is switched to the reset state, the counting operation is stopped and the count value at that time is held,
The output control means presets a count value to 1.0 when the cross polarization interference compensation circuit is switched to the non-reset state, and counts a count value when the cross polarization interference compensation circuit is switched to the reset state. A down counter that counts down to zero, outputs a signal representing the count value of the down counter to the multiplying means, and counts the count value of the up / down counter when the count value of the down counter becomes zero. The cross polarization interference compensation circuit according to claim 4, wherein the value is set to 0. The transversal filter and the tap coefficient for generating cross-polarization interference compensation signals for canceling different polarization side signals leaked into each of two orthogonal baseband signals of the self polarization side signal. 6. The cross polarization interference compensation circuit according to claim 4, wherein two sets of a generation unit, the output control unit, and the multiplication unit are provided.

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