JP2004112217A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver capable of accurately differentiating the phase difference of I and Q signals outputted from mixers by 90 degrees. <P>SOLUTION: The receiver includes: two mixers 5, 6 for receiving modulated high frequency signals; and a signal generating section 7 for generating a local oscillation signal supplied to the two mixers 5, 6, and the signal generating section 7 is provided with: an oscillation circuit 8; and a signal distribution means 9 for distributing an oscillated signal outputted from the oscillation circuit 8 and receiver for supplying the distributed signal to the two mixers, the signal distribution means 9 for adjusting the phase difference between the distributed signals. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a receiver having two mixers and outputting an I signal and a Q signal whose phases are orthogonal.
[0002]
[Prior art]
A conventional receiver will be described with reference to FIG. For example, a digitally modulated high-frequency signal is received by a receiving unit 31 including a band-pass filter 32 and a low-noise amplifier 33 provided at a stage subsequent to the digital-modulated high-frequency signal. The distributed high-frequency signal is input to the first mixer 35 and the second mixer 36. A local oscillation signal is supplied from the oscillation circuit 37 to the first mixer 35 and the second mixer 36, but is supplied directly to the first mixer 35, and a 90 ° phase shifter is supplied to the second mixer 36. 38. Therefore, the phase difference between the local oscillation signals supplied to the two mixers 35 and 36 is 90 °. The local oscillation frequency matches, for example, the frequency of the received high-frequency signal.
[0003]
As a result, although the baseband signals are output from the two mixers 35 and 36, the I signal output from the first mixer 35 and the Q signal output from the second mixer 36 have a phase difference of 90 °. . These baseband signals are output to the subsequent stage through bandpass filters 39 and 40, respectively, in order to avoid image disturbance (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP-A-11-331011 (FIG. 11)
[0005]
The baseband signals that have passed through the bandpass filters 39 and 40 are added by an adding circuit (not shown), and then demodulated.
[0006]
[Problems to be solved by the invention]
In the above configuration, even if the phase difference between the local oscillation signals respectively supplied to the two mixers is 90 °, a slight difference in circuit characteristics between the two mixers and a slight difference between the two band-pass filters. The phase difference between the I signal and the Q signal is not always exactly 90 ° due to the difference in the circuit characteristics of the above. When the baseband signal is demodulated in such a state, a bit error occurs in the obtained digital signal.
[0007]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a receiver capable of accurately changing the phase difference between an I signal and a Q signal output from a mixer by 90 degrees.
[0008]
[Means for Solving the Problems]
In order to solve the above problem, the present invention comprises two mixers to which a modulated high-frequency signal is input, and a signal generator for generating a local oscillation signal to be supplied to the two mixers, wherein the signal The generator is provided with an oscillation circuit and signal distribution means for distributing the oscillation signal output from the oscillation circuit and supplying the divided signals to the two mixers, respectively, wherein a phase difference between the distributed signals is provided. Can be adjusted by the signal distribution means.
[0009]
The signal distribution unit compares the oscillation signal with a reference voltage, converts the signal into a substantially rectangular wave, and adjusts a duty cycle of the rectangular wave. A first signal that repeats turning off is output, and on and off are repeated at successive falling edges of the rectangular wave, and a second signal that is out of phase with the first signal by approximately 90 ° is output. / 1 divider circuit, wherein the first signal is supplied to one of the mixers, and the second signal is supplied to the other of the mixers.
[0010]
Further, the comparison circuit has two transistors whose emitters are connected to each other and whose collectors are each connected to a power supply resistor, applies a reference voltage to the base of one of the transistors, and applies the reference voltage to the base of the other transistor. An oscillation signal is input, the rectangular wave is output from the collector of one of the transistors, and the reference voltage can be changed.
[0011]
Further, the 回路 frequency dividing circuit has first and second D flip-flop circuits and an inverter, and inputs the rectangular wave to a clock input terminal of the first D flip-flop circuit, and connects the inverter to the clock input terminal. And a negative input terminal of the first flip-flop circuit is connected to a data input terminal of the first flip-flop circuit via the first flip-flop circuit. A positive output terminal of the flip-flop circuit is connected to a data input terminal of the second flip-flop circuit, and the first signal is output from a positive output terminal of the first flip-flop circuit; The second signal was output from the positive output terminal of the above.
[0012]
Further, the 回路 frequency dividing circuit has first and second D flip-flop circuits and an inverter, and inputs the rectangular wave to a clock input terminal of the first D flip-flop circuit, and connects the inverter to the clock input terminal. Input to the clock input terminal of the second flip-flop circuit, and the negative output terminal of the first flip-flop circuit to the data input terminal of the first flip-flop circuit and the data of the second flip-flop circuit. The first signal is output from the positive output terminal of the first flip-flop circuit, and the second signal is output from the positive output terminal of the second flip-flop circuit.
[0013]
Further, the frequency of the oscillation signal is twice as high as the frequency of the high frequency signal to be received.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
The receiver according to the present invention will be described with reference to FIGS. 1 is a circuit diagram showing a configuration of a receiver according to the present invention, FIG. 3 is a circuit diagram showing a specific configuration of a comparison circuit in FIG. 1, FIG. 3 is an explanatory diagram of operation of the comparison circuit, and FIG. FIG. 5 is a circuit diagram showing a specific configuration of the frequency divider, FIG. 5 is an explanatory diagram of the operation of the 1/2 frequency divider shown in FIG. 4, and FIG. 6 is a circuit diagram showing another specific configuration of the half frequency divider in FIG. FIG. 7 is an explanatory diagram of the operation of the 1/2 frequency dividing circuit shown in FIG.
[0015]
In FIG. 1, for example, a digitally modulated high-frequency signal is received by a receiving unit 1 including a band-pass filter 2 and a low-noise amplifier 3 provided at the next stage, and is divided into two by a distribution circuit 4. The distributed high-frequency signal is input to the first mixer 5 and the second mixer 6. A local oscillation signal is supplied from the signal generator 7 to the first mixer 5 and the second mixer 6.
[0016]
The signal generator 7 includes an oscillation circuit 8 and signal distribution means 9 for dividing the oscillation signal output from the oscillation circuit 8 into two and supplying the divided signals to the two mixers 5 and 6, respectively.
Further, the signal distribution means 9 compares the oscillation signal output from the oscillation circuit 8 with a reference signal to convert the oscillation signal into a substantially rectangular wave, and adjusts the duty cycle of the rectangular wave. It is composed of a 1/2 frequency divider circuit 11 which outputs a first signal and a second signal whose phases are different from each other by approximately 90 °. Then, the first signal and the second signal are supplied as local oscillation signals to the first mixer 5 and the second mixer 6, respectively.
[0017]
The comparison circuit 10 has two transistors 10a and 10b as shown in FIG. 2, and their emitters are connected to each other and connected to a constant current source 10c. The collectors of the transistors 10a and 10b are connected to power supply resistors 10d and 10e, respectively. The reference voltage Vr is applied to the base of one transistor 10a, and the oscillation signal output from the oscillation circuit 8 is input to the base of the other transistor 10b.
[0018]
In this configuration, the oscillation signal is compared with the reference voltage, and a substantially rectangular wave is output from the collector of each transistor. A rectangular wave OUT1 output from one transistor 10a is output from the other transistor 10b. The square wave OUT2 is inverted. The duty cycle of each rectangular wave changes according to the level of the reference voltage. For example, as the reference voltage increases, the duty cycle of the rectangular wave OUT1 output from one transistor 10a decreases as shown in FIG. On the contrary, the duty cycle of the rectangular wave OUT2 output from the other transistor 10b increases. When the reference voltage decreases, the duty cycle changes in the opposite direction as shown in FIG.
[0019]
As shown in FIG. 4, the 1/2 frequency divider circuit 11 has a first D flip-flop circuit 11a, a second flip-flop circuit 11b, and an inverter 11c, and a negative output terminal ( q) is connected to the data input terminal (D) of the first flip-flop circuit 11a, and the positive output terminal (Q) of the first flip-flop circuit 11a is connected to the data input terminal (D) of the second flip-flop circuit 11b. ). Then, the rectangular wave output from either the collector of the transistor 10a or 10b of the comparison circuit 10 is input to the clock input terminal (CP) of the first D flip-flop circuit 11a and the second flip-flop circuit is connected via the inverter 11c. Input to the clock input terminal (CP) of the loop circuit 11b.
[0020]
In the configuration of FIG. 4, a first signal that repeats on and off in order at successive rising edges of the input rectangular wave is output to the positive output terminal (Q) of the first grip flop circuit 11a, A second signal that repeats on and off in sequence at the falling edge of the square wave is output to the positive output terminal (Q) of the amplifier circuit 11b. Therefore, the first signal and the second signal are frequency-divided by half with respect to the input rectangular wave.
[0021]
Also, looking at the phase relationship between the first signal and the second signal, when the duty cycle of the input rectangular wave is 50% as shown in FIG. The phase of the second signal is delayed by π / 2 (90 °) as shown by C with respect to the phase. Then, the phase of the second signal changes according to the duty cycle of the input rectangular wave. If the duty cycle is smaller than 50%, the phase advances beyond π / 2, and if the duty cycle is larger than 50%, π / Late than 2.
[0022]
The first signal is supplied to, for example, a first mixer 5, the second signal is supplied to a second mixer 6, and a baseband signal is output from the first mixer 5 and the second mixer 6. The baseband signal (I signal) output from the first mixer 5 and the baseband signal (Q signal) output from the second mixer 6 pass through bandpass filters 12 and 13 for avoiding image interference, respectively. The signal is output to the subsequent stage, added by an adding circuit (not shown), and then demodulated.
[0023]
The phase difference between the I signal output from the first mixer 5 and the Q signal output from the second mixer 6 depends on the phase difference between the first signal and the second signal. Therefore, when the phase difference between the I signal and the Q signal deviates from π / 2, the deviation can be corrected by the phase difference between the first signal and the second signal. For this purpose, the duty cycle of the rectangular wave input to the 1/2 frequency divider 11 may be adjusted. Adjustment of the duty cycle is possible by the reference voltage applied to the base of one transistor 10a in the comparison circuit 10.
When the I signal and the Q signal do not have a phase difference of π / 2, the bit error of the demodulated digital signal deteriorates. Therefore, the duty cycle of the rectangular wave is adjusted while checking the bit error.
[0024]
FIG. 6 shows another configuration of the 周 frequency dividing circuit 11. The negative output terminal (q) of the first flip-flop circuit 11a is connected to the data input terminal (D) of the first flip-flop circuit 11a and the data input terminal (D) of the second flip-flop circuit 11b. To the clock input terminal (CP) of the first D flip-flop circuit 11a and to the clock input terminal (cp) of the second flip-flop circuit 11b via the inverter 11c. Then, the first signal is output from the positive output terminal (Q) of the first flip-flop circuit 11a, and the second signal is output from the positive output terminal (Q) of the second flip-flop circuit 11b.
[0025]
In the configuration of FIG. 6, when the duty cycle of the input rectangular wave is 50%, the second signal (C) is different from the first signal (A) as shown in FIGS. The phase advances by π / 2. The leading phase changes according to the duty cycle of the input rectangular wave as in the configuration of FIG.
[0026]
In the present invention, the oscillation frequency of the oscillation circuit 8 is set to twice the frequency of the high-frequency signal to be received, but is not necessarily limited to this. However, the frequency of the first signal and the frequency of the second signal supplied to the mixers 5 and 6 match the frequency of the high-frequency signal by setting the frequency to twice the frequency of the high-frequency signal to be received. Therefore, a so-called direct conversion receiver can be configured.
[0027]
【The invention's effect】
As described above, the signal generation unit is provided with the oscillation circuit and the signal distribution unit that distributes the oscillation signal output from the oscillation circuit and supplies the distributed signal to each of the two mixers. Since the phase difference between them can be adjusted by the signal distribution means, the phase difference between the baseband signals output from the two mixers can be π / 2. Therefore, the bit error of the demodulated data can be minimized.
[0028]
Further, the signal distribution means converts the oscillation signal into a substantially rectangular wave and outputs a comparison circuit capable of adjusting the duty cycle of the rectangular wave and a first signal which repeats on and off at successive rises of the rectangular wave. And a 1/2 frequency divider circuit which repeats on and off at successive falling edges of the rectangular wave and outputs a second signal having a phase difference of about 90 ° from the first signal. Is supplied to one of the mixers and the second signal is supplied to the other of the mixers, so that the phase difference between the first and second signals can be adjusted by adjusting the duty cycle.
[0029]
The comparison circuit has two transistors whose emitters are connected to each other and whose collectors are each connected to a power supply resistor. A reference voltage is applied to the base of one transistor and an oscillation signal is input to the base of the other transistor. Since a rectangular wave is output from the collector of one of the transistors and the reference voltage can be changed, the duty cycle of the rectangular wave can be adjusted.
[0030]
In addition, the rectangular wave is input to the clock input terminal of the first D flip-flop circuit and to the clock input terminal of the second flip-flop circuit via the inverter, and the negative output terminal of the first flip-flop circuit is A data input terminal of one flip-flop circuit, and a positive output terminal of the first flip-flop circuit is connected to a data input terminal of the second flip-flop circuit. Since one signal was output and the second signal was output from the positive output terminal of the second flip-flop circuit, the first signal and the second signal were adjusted by adjusting the duty cycle of the input rectangular wave. Can be adjusted.
[0031]
In addition, a rectangular wave is input to the clock input terminal of the first D flip-flop circuit and to the clock input terminal of the second flip-flop circuit via an inverter, and the negative output terminal of the first flip-flop circuit is connected to the negative output terminal. The first flip-flop circuit is connected to a data input terminal of the first flip-flop circuit and a data input terminal of the second flip-flop circuit, and outputs a first signal from a positive output terminal of the first flip-flop circuit. Since the second signal is output from the positive output terminal, the phase difference between the first signal and the second signal can be adjusted by adjusting the duty cycle of the input rectangular wave.
[0032]
In addition, since the frequency of the oscillation signal is twice the frequency of the high frequency signal to be received, the frequencies of the first signal and the second signal supplied to the two mixers match the frequency of the high frequency signal. Therefore, a receiver of the direct conversion system can be configured.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a receiver according to the present invention.
FIG. 2 is a circuit diagram showing a specific configuration of a comparison circuit used in the receiver of the present invention.
FIG. 3 is an operation explanatory diagram of a comparison circuit used in the receiver of the present invention.
FIG. 4 is a circuit diagram showing a specific configuration of a 1/2 frequency divider used in the receiver of the present invention.
FIG. 5 is an explanatory diagram of an operation of a 1/2 frequency dividing circuit used in the receiver of the present invention.
FIG. 6 is a circuit diagram showing a specific configuration of another 1/2 frequency dividing circuit used in the receiver of the present invention.
FIG. 7 is an operation explanatory diagram of another 1/2 frequency divider circuit used in the receiver of the present invention.
FIG. 8 is a circuit diagram showing a configuration of a conventional receiver.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Receiving part 2 Band-pass filter 3 Low noise amplifier 4 Distribution circuit 5 First mixer 6 Second mixer 7 Signal generation part 8 Oscillation circuit 9 Signal distribution means 10 Comparison circuits 10a, 10b Transistors 10c Constant current sources 10d, 10e Resistor 11 1/2 frequency dividing circuit 11a First D flip-flop circuit 11b Second D flip-flop circuit 11c Inverters 12, 13 Band-pass filters

Claims (6)

It is provided with two mixers to which the modulated high-frequency signal is input, and a signal generation unit for generating a local oscillation signal to be supplied to the two mixers, wherein the signal generation unit includes an oscillation circuit, Signal distributing means for distributing an output oscillation signal and supplying the divided signals to the two mixers, respectively, so that a phase difference between the distributed signals can be adjusted by the signal distributing means. Receiver. The signal distribution unit converts the oscillation signal into a substantially rectangular wave by comparing the oscillation signal with a reference voltage, and a comparison circuit capable of adjusting the duty cycle of the rectangular wave, and ON and OFF at successive rises of the rectangular wave. And outputs a second signal having a phase that is different from the first signal by approximately 90 ° while repeating on and off at successive falling edges of the rectangular wave. The receiver according to claim 1, further comprising a frequency divider, wherein the first signal is supplied to one of the mixers, and the second signal is supplied to the other of the mixers. The comparison circuit has two transistors whose emitters are connected to each other and whose collectors are connected to a power supply resistor, respectively. A reference voltage is applied to the base of one of the transistors, and the oscillation signal is applied to the base of the other transistor. 3. The receiver according to claim 2, wherein the rectangular wave is output from a collector of one of the transistors to change the reference voltage. The 分 divider circuit has first and second D flip-flop circuits and an inverter, and inputs the rectangular wave to a clock input terminal of the first D flip-flop circuit and, via the inverter, A clock input terminal of the second flip-flop circuit, a negative output terminal of the first flip-flop circuit is connected to a data input terminal of the first flip-flop circuit, and the first flip-flop circuit Connected to the data input terminal of the second flip-flop circuit, outputs the first signal from the positive output terminal of the first flip-flop circuit, and outputs the positive signal of the second flip-flop circuit. The receiver according to claim 2, wherein the second signal is output from an output terminal. The 分 divider circuit has first and second D flip-flop circuits and an inverter, and inputs the rectangular wave to a clock input terminal of the first D flip-flop circuit and, via the inverter, A clock input terminal of the second flip-flop circuit is input, and a negative output terminal of the first flip-flop circuit is a data input terminal of the first flip-flop circuit and a data input terminal of the second flip-flop circuit. And outputting the first signal from the positive output terminal of the first flip-flop circuit and outputting the second signal from the positive output terminal of the second flip-flop circuit. The receiver according to claim 2. 6. The receiver according to claim 1, wherein the frequency of the oscillation signal is twice as high as the frequency of the high frequency signal to be received.

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