WO2019092440A1

WO2019092440A1 - Radio frequency communication

Info

Publication number: WO2019092440A1
Application number: PCT/GB2018/053260
Authority: WO
Inventors: Ola BRUSET
Original assignee: Nordic Semiconductor Asa; Samuels, Adrian James
Priority date: 2017-11-10
Filing date: 2018-11-12
Publication date: 2019-05-16
Also published as: GB201718633D0

Abstract

A circuit portion (100) is provided which comprises a phase expansion portion (111) arranged to receive an oscillating input signal (202) with a first frequency and output a first digital signal (206) having a plurality of parts each having a different phase. The circuit portion also comprises a phase selection portion (114) arranged to select a sub-set of the plurality of parts of the first digital signal (206) and to combine said sub-set to produce a second digital signal (210) having a second frequency. The sub- set of the plurality of parts of the first digital signal (206) is selected by the phase selection portion (114) so that the first frequency is not an integer multiple of the second frequency.

Description

496.409.130146/01

Radio Frequency Communication

This invention relates to radio transmitters and receivers. It relates particularly, although not exclusively, to frequency synthesisers used for short range digital radio communication.

When transmitting data using electromagnetic waves, a transmitting device typically generates an oscillating carrier signal and encodes the data to be transmitted onto this carrier signal using some form of modulation, for instance quadrature amplitude modulation (QAM) or binary phase shift keying (BPSK). The modulated signal is then broadcast via an antenna.

To generate the carrier signal, the transmitting device typically utilises an oscillating electronic circuit as a local oscillator to provide an oscillating signal with a frequency determined by the physical characteristics of the components of the electronic circuit. However if the modulated signal broadcast via the antenna has the same or a similar frequency to the local oscillator, the broadcast signal can couple back into the local oscillator causing spectral regrowth or remodulation. This increases the bandwidth of the broadcast signal and can degrade the error vector magnitude in the signal, both of which are highly undesirable in radio systems.

One solution to this problem which has been proposed is to run the local oscillator at a multiple of the desired carrier signal frequency, and to use a frequency divider to convert the local oscillator signal to the desired frequency. However because the broadcast signal will always have a certain amount of energy in harmonics of the carrier frequency, and one of these will be at the local oscillator frequency, this does not entirely solve the problem.

Other proposals for minimising coupling effects require multiple mixing stages which can be complex and have high current demands. In applications where energy efficiency is essential, such as in battery powered devices where long battery life is important, these additional current demands are highly undesirable. The present invention sets out at least partially to alleviate these problems.

From a first aspect, the invention provides a circuit portion comprising:

a phase expansion portion arranged to receive an oscillating input signal with a first frequency and output a first digital signal having a plurality of parts each having a different phase; and

a phase selection portion arranged to select a sub-set of the plurality of parts of the first digital signal and to combine said sub-set to produce a second digital signal having a second frequency;

wherein the sub-set of the plurality of parts of the first digital signal is selected by the phase selection portion so that the first frequency is not an integer multiple of the second frequency.

Thus it will be seen by those skilled in the art that, in accordance with the invention, there is provided a circuit portion that receives an input signal and outputs a digital signal whose frequency or harmonics do not clash with the frequency of the input signal. As will be explained below, this can allow radio system designers to reduce the energy usage of their end product while avoiding oscillator coupling issues. Because the invention allows a fully digital implementation, the current demands and the physical space taken up by the circuit portion can be lower than in conventional frequency synthesis arrangements, in which analogue mixers are used to convert an oscillating signal into a carrier signal with a frequency not equal to an integer division of the oscillating signal. This analogue mixing process can be current intensive and it requires suppression of unwanted mixing products.

The invention provides a digital signal whose frequency or harmonics do not clash with the frequency of the input signal, however the Applicant has appreciated that even in situations where no harmonic of the second frequency clashes with the first frequency there may be scenarios in which a harmonic of the second frequency clashes with a harmonic of the first frequency. This can lead to the coupling-back issues as discussed earlier, however the sub-set of the plurality of parts is preferably selected to mitigate these harmonic-harmonic clashes, at least in the lower orders where most energy is present. ln a set of embodiments, the circuit portion further comprises at least one delay element, preferably a resistor, arranged to add a delay to at least one of the selected parts prior to being combined to provide the second digital signal. This allows the second digital signal to be adjusted such that "jitter" - where the selected parts of the first digital signal do not have an evenly spaced phase in the second digital signal - can be minimised. In some embodiments a plurality of delay elements are provided on respective signal parts to adjust the second digital signal. In a set of embodiments the delay element(s) comprise(s) a resistor. It has been found that resistors of suitable value can provide a desired delay by forming an RC element in conjunction with the input capacitance of an associated logic gate.

In some embodiments, the phase expansion portion comprises a frequency divider and a phase expander. The frequency divider may be arranged to receive the oscillating input signal and output an X-part signal, where each part has a 1/X duty cycle and is evenly spaced in phase. In one embodiment X is equal to 4, such that the frequency divider outputs a four-part signal with each part being spaced at 90° phase intervals and having a 25% duty cycle, a so called "one-hot" 4-part signal. The phase expander may be arranged to receive the X-part signal and output an N- part signal, where N is larger than X. In some embodiments the phase expander comprises at least one D-type flip flop. The phase expander may comprise at least one AND gate.

The phase selection portion may select M parts of the first digital signal to produce the second digital signal. In some embodiments, the phase selection portion comprises at least one NOR gate, and at least one of the inputs of the at least one NOR gate may be connected to an output of the phase expansion portion. In embodiments comprising a delay element, the delay element may be arranged between the output of the phase expansion portion and the input of the at least one NOR gate. A further input of the at least one NOR gate may be connected to one of the outputs of the phase expansion portion via a further delay element which may introduce a different amount of delay.

M may be chosen to be an odd number, preferably 3, 5 or 7. N may be greater than 2M. N may be a multiple of 4, preferably chosen from the group 8, 12, 16, 20 and 24. In one preferred embodiment M = 3 and N = 8, and the second frequency equals 3/4 times the first frequency. In another preferred embodiment M = 3 and N = 16, and the second frequency equals 3/8 times the first frequency. M and N may be chosen to minimise harmonic-harmonic clashes as discussed above. In preferred embodiments the circuit portion is battery powered, although any suitable power source, for example a mains-powered transformer or a solar cell could be used.

In some embodiments, the phase expansion and/or phase selection portions are provided on an integrated circuit. Because no bulky and current intensive signal mixers or mixing product suppression components are required in accordance with the invention, the space and heat dissipation demands are minimised.

The circuit portion preferably forms part of a frequency synthesiser module for a radio frequency transmitter. Thus when viewed from a second aspect, the invention provides a radio frequency transmitter system comprising:

a baseband module;

an antenna; and

a frequency synthesiser, which comprises a circuit portion according to the first aspect of the invention as described herein;

wherein a digital signal provided by the circuit portion is used as a local oscillator signal to modulate a baseband signal provided by the baseband module to produce an output signal for broadcast on the antenna. Thus it will be appreciated by those skilled in the art that, in accordance with the present invention, there is provided a radio frequency transmitter system that minimises the coupling of a broadcast signal back to a local oscillator. This helps ensure that bandwidth of the output signal is narrow and that the error vector magnitude in the signal is not degraded.

Features of any aspect or embodiment described herein may, wherever appropriate, be applied to any other aspect or embodiment described herein. Where reference is made to different embodiments or sets of embodiments, it should be understood that these are not necessarily distinct but may overlap. Certain preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

Figure 1 is a schematic view of an output stage of a digital frequency synthesiser module in accordance with the invention;

Figure 2 is a timing diagram illustrating the operation of the frequency synthesiser module shown in Figure 1 ;

Figure 3 is an example of a phase expander which can be used in the embodiment of Figure 1 ;

Figure 4 shows a phase selector which can be used in the embodiment of Figure 1 ;

Figure 5 shows a schematic view of a radio transmitter system incorporating the frequency synthesiser module shown in Figure 1 ;

Figure 6 shows an example of a duty cycle conversion circuit can be used in the embodiment of Figure 1 ; and

Figures 7a-c are phasor diagrams illustrating a phase selection process.

Figure 1 shows a digital frequency synthesiser module 100 in accordance with an embodiment of the invention. The synthesiser comprises a voltage controlled oscillator (VCO) 102 that produces an oscillator signal at an oscillator frequency fvco which can be controlled in a manner known in the art per se. The oscillator signal is output via an oscillator output 104. The output 104 of the VCO 102 is connected to a divide-by-two divider circuit 106, which has a four-part output 108. The four-part output 108 is connected to a four-to-eight phase expander 110 which has an eight-part output 112. The divider circuit 106 and the phase expander 1 10 together form a phase expansion module 11 1. The eight-part output 1 12 is connected to a three-of-eight phase selector 114, which generates a four-part local oscillator (LO) signal on a four-part output 116. This can be used for radio transmission as is explained below. With reference to Figure 5, the frequency synthesiser module 100 described above is shown implemented in an RF transmitter 500, which is arranged to transmit RF data from an antenna 508. The LO signal 1 16 generated by the frequency synthesiser module 100 is mixed using a mixer 506 with a baseband signal produced by a digital baseband module 502 and a digital to analogue converter (DAC) 504,. The mixed signal is then amplified using a power amplifier 514 and passed through a bandpass filter 516 before being sent to the antenna 508 to be broadcast.

The Applicant has appreciated that in a typical conventional transmitter, if the frequency of the broadcast signal (or one of its harmonics) is near or equal to the frequency of the oscillator signal produced by the VCO it employs, there would a risk that the signal from the antenna will couple back into the VCO. This can cause demodulation or spectral regrowth, both of which are highly undesirable in an RF transmitter device. In accordance with the present invention however, as will be explained below, the frequency synthesiser 100 is produces an LO signal 116 that does not clash with the VCO frequency or any of its harmonics since it is a complex fraction of the VCO frequency. In the embodiment described herein, a signal with a frequency equal to ¾ of the VCO frequency is produced and therefore there is minimal coupling of the broadcast radiation back into the VCO 102 (represented by the wavy arrow line), reducing the likelihood of the adverse effects described above.

The digital synthesizer shown in Figure 1 will now be described in more detail with reference to Figures 2 to 4.

The VCO 102 generates a differential oscillating signal 202 shown at the top of Fig. 2_. In one example f_Vco = 3.2 GHz. The oscillator signal 202 is output from the VCO 102 via the output 104 to the divide-by-two divider circuit 106, which is arranged to output a four-part digital signal with a frequency of ½ f_Vco = 1.6 GHz, with each of the four-parts having a 25% duty cycle and each being phase offset by 90° to produce a four-part, one-hot signal 204. Various implementations of such a divider circuit are possible using flip-flops and other simple logic gates, but a convenient implementation comprises a divide-by-two circuit which outputs a four-part 90° phase offset signal, with each part having arbitrary duty cycles within the 25% to 50% range, along with a duty cycle conversion circuit comprising four inverters, which precisely controls the duty cycle of each of the parts of the frequency divider output to produce the four-part one-hot signal 204.

One example of a suitable duty cycle conversion circuit is illustrated in Figure 6, wherein a duty cycle conversion circuit 601 comprises four Boolean inverters 602, 604, 606, 608. Each inverter 602, 604, 606, 608 respectively comprises: an input terminal to 602a, 604a, 606a, 608a; an output terminal 602b, 604b, 606b, 608b; a positive power terminal 602c, 604c, 606c, 608c; and a negative power terminal 602d, 604d, 606d, 608d.

Each inverter 602, 604, 606, 608 is arranged to receive a different input signal 610a, 610b, 610c, 61 Od at its respective input terminal 602a, 604a, 606a, 608a and produce an output signal 612a, 612b, 612c, 612d at its respective output terminal 602b, 604b, 606b, 608b, wherein the output signals 612a-d are the logical negation of the respective input signals 610a-d so long as the corresponding inverter 602, 604, 606, 608 is powered on.

While the negative power terminal 602d, 604d, 606d, 608d of each inverter 602, 604, 606, 608 is connected to ground, the positive power terminal 602c, 604c, 606c, 608c of each inverter 602, 604, 606, 608 is connected to the input signal 610a-d applied to a different inverter 602, 604, 606, 608. In this particular arrangement the positive power terminal 602c of the first inverter 602 is connected to the input signal 61 Od applied to the input terminal 608a of the fourth inverter 608; the positive power terminal 604c of the second inverter 604 is connected to the input signal 610a applied to the input terminal 602a of the first inverter 602; the positive power terminal 606c of the third inverter 606 is connected to the second input signal 610b applied to the input terminal 604a of the second inverter 604; and the positive power terminal 608c of the fourth inverter 608 is connected to the third input signal 610c applied to the input terminal 606a of the third inverter 606. Thus it will be seen that the inverters 602, 604, 606, 608 are arranged in a loop wherein the input signal 610a-d applied to each inverter 602, 604, 606, 608 is used to power the next inverter 602, 604, 606, 608 in the loop.

As a result, so long as the rising edges of each of the input signals (provided by the divide-by-two circuit) 610a-d are well defined at the correct intervals and that each input signal 610a-d has a duty cycle between 25% and 50% (i.e. between 1/N and 2/N wherein N=4), each of the output signals 612a-d will have a duty cycle of exactly 25% triggered by only the rising edges of the input signals. The four-part, one-hot signal 204 produced by the divider circuit 106 is sent via the four-part output 108 to the four-to-eight phase expander 110. The phase expander 1 10 transforms the four-part one-hot signal 204 into an eight-part one-hot signal 206 with half the frequency of the four-part one-hot signal 204 as seen on the third row of Fig. 2. As shown in Figure 3, the phase expander 1 10 is, for example, implemented using four D-type flip flops 302a-d and eight AND gates 304a-h. The four phase signal is input via inputs 108a-d and is distributed to the flip flops 302a-d and AND gates 304a-h. The resultant eight-part signal is output via eight outputs 116a-h. The operation of the phase expander will be described in more detail below.

Each of the D-type flip flops 302a-d comprises a clock input 306a-d, a data input 308a-d, a non-inverted output 310a-d and an inverted output 312a-d. The first flip flop 302a is configured with its inverted output 312a connected to its data input 308a, and the third input 108c connected to its clock input 306a, such that for every rising edge of the third input 108c, the non-inverted output 310a of the first flip flop 302a alternates between HIGH and LOW. The non-inverted output 310a of the first flip flop 302a is connected to the data input 308b of the second flip flop 302b, which has its clock input 306b connected to the fourth input 108d. As a result, the non- inverted output 310b of the second flip flop 302a alternates between HIGH and LOW for every rising edge of the fourth input 108d.

The third and fourth flip flops 302c, 302d are similarly configured, clocked by the first and second inputs 108a, 108b respectively. The result is that with each cycle of the four inputs 108a-d, the outputs of the four flip flops 302a-d alternate between HIGH and LOW.

Each of the AND gates 304a-h comprises two inputs and one output and is configured to operate as a conventional AND gate, such that each output is only HIGH when both inputs are HIGH. The outputs of the eight AND gates 304a-h provide the eight outputs 1 16a-h of the phase expander 1 10. The first four AND gates 304a-d each have one input connected to the respective inputs 108a-d and the other input connected to the non-inverted outputs 310a-d of the four flip flops 302a-d. The final four AND gates 304e-h each have one input connected to the respective inputs 108a-d and the other input connected to the inverted outputs 312a-d of the four flip flops 302a-d. As explained above, and seen in Figure 2, the four inputs 108a-d carry a four-part, one-hot signal 204, which has a frequency of ½ fvco_. The AND gates 304a-h are connected, as described above, such that when the first input 108a is on, one input of the first AND gate 1 16a and one input of the fifth AND gate 1 16e is on. At the beginning of a first cycle of the four-part signal 204 (the first rising edge, or "tick"), the first input 108a is HIGH, the non-inverted output 310a of the first flip flop 302a is HIGH, and the inverted output 312a of the first flip flop 302a is LOW. Consequently the first AND gate 304a receives two HIGH inputs, and its output is therefore HIGH, however the fifth AND gate only receives one HIGH input, and its output is therefore LOW. Additionally, due to the arrangement of connections explained above, the first tick (from the first input 108a) also serves to switch the output of the third flip flop to HIGH. Similarly, the second flip flop 302b is configured such that, during the second tick of the first cycle of the four-part one hot signal 204 (with the second input 108b HIGH), the output of the second AND gate 1 16b is HIGH. Additionally, as for the first tick, the second tick also serves to switch the non-inverted output 31 Od of the fourth flip flop 302d HIGH.

The third and fourth ticks of the first cycle similarly cause HIGH output from the third and fourth AND gates 304c, 304d, and switch the non-inverted outputs of the first and second flip flops 310a, 310b LOW. As a result, when a second cycle of the four-part one hot signal 204 begins, the first input 108a being HIGH does not trigger the first AND gate 304a, but instead drives the fifth AND gate 304e HIGH. Similarly, during the second cycle, the second, third and fourth inputs 108b-d drive the sixth, seventh and eighth outputs 116f-h respectively HIGH.

As a consequence, during the first cycle of the four-part one hot signal 204, the signal is effectively directed to the first four outputs 116a-d, while during the second cycle, the signal is directed to the second four outputs 116e-h. The flip flops 302a-d thereby act as "select pulse" generators, and the AND gate pairs act as multiplexers such that the four-part one hot signal 204 is expanded to an eight-part one-hot signal 206 with a frequency of ¼ f_Vco, as seen on the third row of Fig. 2. While in this case the phase expander 110 is configured to output an eight-part signal 206, in principle the number, N, of parts could be expanded to other values although some values (as will be discussed below) are more useful than others. A higher value of N increases the number of parts that can be chosen from by the phase selector when "building" the output signal. As will be explained in more detail below, the output signal may comprise a certain amount of jitter, whereby the selected parts do not exactly coincide with those of the ideal signal. Splitting the signal into a larger number of parts enables more optimal parts to be selected, reducing the size of any such "phase excursions", reducing spurious emissions and so potentially reducing filtering requirements. In addition, a larger N allows for the output signal to be produced with frequencies that are more 'complex' fractions of the VCO frequency. By complex fractions is meant that the numerator is greater than one and the denominator is not too low - e.g. more than 5. The value of N which can be implemented at a reasonable cost (financially and in terms of power consumption) is limited because the circuit complexity increases with N to the point where the current consumption of the phase expander becomes greater than the savings made by using a digital approach as described herein. With current technology a four-to-sixteen or four-to-twenty four phase expander may be worthwhile and in the future even greater expansion may be effective. Currently, practicable values of N are typically multiples of four, but other values of N are also envisaged.

The eight-part one-hot signal 206 is sent from the phase expander 110 via the eight-part output 1 12 to the phase selector 114, which is implemented using four, three-input NOR gates as illustrated in Figure 4. The phase selector 114 'selects' different respective subsets of three of the eight parts to send to each of four outputs in order to produce a four-part output signal 210 with a frequency of ¾ f_Vco = 2.4 GHz. With reference to Figure 4, the eight-to-three phase selector 1 14 comprises four three-input NOR gates 402, 404, 406, 408, each of which comprises three inputs along with a power source (not shown) and a respective output 430, 431 , 432, 433. Eight signal lines 420-427 that correspond to the eight-part output 1 12 of the phase expander 110, are provided to the phase selector 114. The phase selector 1 14 comprises four output lines 430-433, which make up the four-part LO output 116. The zeroth, third and fifth signal lines 420, 423, 425 are connected to the three inputs of the first NOR gate 402 via first, second and third resistors 410a, 410b, 410c (the purpose of which will be explained later). Similarly, the first, third and sixth signal lines 421 , 423, 426 are connected to the three inputs of the second NOR gate 404 via resistors 412a-c; the first, fourth and seventh signal lines 421 , 424, 427 are connected to the three inputs of the third NOR gate 406 via resistors 414a-c and the second, fifth and seventh signal lines 422, 425, 427 are connected to the three inputs of the fourth NOR gate 408 via resistors 416a-c.

The output of the first NOR gate 402 is connected to the first output line 430, the output of the second NOR gate 404 is connected to the second output line 431 , the output of the third NOR gate 406 is connected to the third output line 432 and the output of the fourth NOR gate 408 is connected to the fourth output line 433.

As a result, each part of the four-part LO output 1 16 of the eight-to-three phase selector 1 14 described above is a composite signal obtained by adding different respective subsets of three components of the eight-part signal 206 produced by the phase expander 1 10. The effect of this can be seen by referring again to Fig. 2. The four-part signals 210 seen in the fifth row show what the resultant signals would be if the above-mentioned subsets of the eight-part signal 206 were simply OR'ed together. Thus the Ό' part of the signal 210 is a sum of the Ό', '3' and '5' parts of the eight-part signal 206; the Ί ' part of the signal 210 is a sum of the Ί ', '3' and '6' parts of the eight-part signal 206; the '2' part f the signal 210 is a sum of the , '4' and 7' parts of the eight-part signal 206; and the '3' part of the signal 210 is a sum of the '2', '5' and 7' parts of the eight-part signal 206.

The ideal output of the frequency synthesiser would be the four-part one-hot signal 208 with a frequency of ¾f_Vco = 2.4 GHz shown in the fourth row of Fig. 2. By comparing this with the signal 210 shown in the row below, it can be seen that the 'simplistic' output signal 210 which would be generated by simply adding the respective subsets in the phase selector 114 has the desired average frequency of ¾fvco = 2.4 GHz, which would substantially mitigate problems with 'couple-back' as previously described, but it displays a certain amount of undesirable "jitter", where the selected parts do not exactly line up with the ideal signal 208. However this jitter can be reduced by introducing some delay elements to the phase selector 1 14, to delay at least some of the selected parts by an appropriate amount, such that they come as close as possible to the ideal signal 208. Specifically the different delays are provided by the resistors 410a-c, 412a-c, 414a-c and 416a-c shown in Fig. 4, since the resulting RC low-pass filter comprising the resistor and the input capacitance of the respective NOR gate 402, 404, 406, 408 provides the required delay. The resistance of each resistor is selected to give the correct delay for each input line. Although this will be explained in more detail below, the result can be seen by looking at the last row of Fig. 2 where the delays which are introduced shift some of the peaks so that they are aligned with corresponding peaks in the 'ideal' signal 210.

It can also be seen that whilst the ideal output signal 208 would have negligible rise and fall times (i.e. vertical pulse edges), in reality the rise and fall time on the beginning and end of each pulse are finite, and the edges of the pulses in the rest of the timing diagram are illustrated as being slightly sloped to reflect this.

The number of parts that are selected, while in this case is three, is not restricted to this. Indeed more generally when the four-part (or indeed any other number of parts) one-hot signal 204 is expanded up to N parts, any M of those parts can be selected to send to each output to generate a signal of the target frequency, which is therefore not restricted to being ¾ f_Vco- The best values of N and M to select depend on the desired output frequency and while there is no deterministic formula for calculating the ideal values there are certain criteria that make some values preferable. For example M should be an odd number, and N is preferably a multiple of four and greater than 2M. The values should be selected such that the 'phase excursions' (the differences between the actual composite signal and the ideal signal) on each output are as small as possible as it is desirable to limit the amount of delay that it is necessary to apply. Of course the values should primarily be such that as far as possible the base and harmonics of the VCO and the LO frequencies do not interfere, especially at lower orders of either. As alluded to above, N may also be limited by manufacturing convenience. For the N = 8, M = 3 case illustrated here, in order to select the three parts that will be fed into each part of the four-part LO output, the relative phase offset between each of the eight parts of the eight-part signal 206 from the phase expander 110 and the ideal ¾f_Vco output signal 208 is calculated (i.e. the phase offset of each of the eight parts were they to be part of a ¾f_Vco signal). The relative phase offset Φ_η is equal to 2π ^j n, wrapped to the 0-360° range, where n runs from 0 to 7. A couple of the phase offsets in the N = 8, M = 3 case are marked on Fig. 2: = 135° and Φ₃ = 45°. Figure 7a illustrates these in a different way. It is a phasor diagram of the components of the eight-part signal 206. The complete set of relative phases for the N = 8, M = 3 case is:

Φ₀ = 0°

0_! = 135°

Φ₂ = 270°

Φ₃ = 45°

Φ₄ = 180°

Φ₅ = 315°

Φ₆ = 90°

Φ₇ = 225°

The closest 3 phases for each output phase (0°, 90°, 180°, 270°) are therefore:

Out 0 = Φ₀ (0°), Φ₃ (45°), Φ₅ (315° = - 45°);

Out 90 = ι (135°), Φ₃ (45°), Φ₆ (90°);

Out 180 = Φι (135°), Φ₄ (180°), Φ₇ (225°); and

Out 270 = Φ₂ (270°), Φ₅ (315°), Φ₇ (225°).

The final four-part LO signal 212 is produced by adding the required delays to each of the input parts. Output part Ό', for instance, is constructed of the Ό', '3' and '5' parts of the output from the phase expander 110, which have relative phases of 0°, +45° and -45° respectively. A delay element can therefore be added which delays the phase of the Ό' output by 45°. A second delay element delays the '3' output by 0° (i.e. no delay) and a third delay element delays the '5' part by 90°. This means that the phases of each of the Ό', '3', and '5' parts of the outputs are now all at +45°, which can be treated as a new "zero reference".

The remaining delay elements are selected to align the phases of the remaining output parts to +90°, +180° and + 270° relative to this new "zero reference" of +45° (i.e. +135°, +225°, +315° relative to the original zero reference phase) .

As will be appreciated from the above, a consequence of adding the delays to align the output parts is that the entire final four-part LO signal 212 is delayed by +45° compared to the initial output signal 210. In order to aid comparison with the rest of the timing diagram however, in Fig. 2 the final four-part LO signal 212 is displayed with a -45° shift, such that the beginning of the cycles of all the elements of the timing diagram align, however in reality, the four-part output will be 45° out of phase with the initial output signal 210.

Using an example of the first NOR gate 402 in Figure 4, the first resistor 410a acts as the first delay element discussed above, delaying the phase of the zeroth or Ό' signal line 420 by 45°. The second and third resistors 410b, 410c similarly delay the third and fifth signal lines 423, 425 by 0° and 90° as discussed above. The phase delay introduced by each of the resistors 410a-c is proportional to their resistance, i.e. the resistance of the third resistor 410c is twice that of the first resistor 410a such that the delay introduced is twice as large (90° compared to 45°).

The resistances of each of the resistors 412a-c, 414a-c and 416a-c connected to the inputs of the other NOR gates 404, 406, 408 are similarly selected to align the phases of the remaining output lines 431 , 432, 433 to +90°, +180° and + 270° relative to this new "zero reference" of +45° (+135°, +225°, +315° relative to the original zero reference phase) such that a jitter free four-part signal is produced. The final jitter-free final four-part LO signal 212 generated by the phase selector

1 14 can then can mixed with a baseband signal and broadcast via an antenna with a significantly reduced risk of feedback to the VCO 102. The duty cycle of the final signal 212 can be seen to be around 33%, differing from the 25% of the ideal output signal 208 however this may be easily adjusted if desired using another duty cycle conversion circuit as described above and illustrated in Figure 6. While in this example the final LO signal is a four-part signal 212, the number of parts of which the final signal is composed could be chosen as desired. For instance the phase selection portion could combine the selection of parts from the phase expansion portion into a single part signal, or indeed a signal with any number of parts. A four part signal is shown in this embodiment simply because it is convenient in the transmitter architecture used by the Applicant.

Figures 7a-c are phasor diagrams illustrating in a different way the phase selection process utilised in the phase selector 114. In each of the plots the solid circles represent components of the output of the phase expander, plotted at their relative phase from the ideal output signal, and the dashed lines contain the components selected by the phase selector to produce each part of the four-part output. As mentioned above, Figure 7a is a phasor diagram of the N = 8, M = 3 example described in detail herein. The eight solid circles (for N = 8) show the phases of the parts of the eight-part signal 206 relative to the ideal 3/4f_Vco signal 208, with, for example, the first component q^at 135° and the third component cp₃ at 45°

(360°+45°). The three parts (M = 3) selected for each respective part of the four- part LO output212 are shown enclosed by dashed lines. The degree of jitter described above can be seen in the spread of the components making up each output part.

Figure 7b shows a phasor diagram for N = 16, M = 3. In this example, the output signal has a frequency of 3/8 f_Vco, and the spread of the component parts making up each sub-set of three is lower than in the N = 8, M = 3 case, corresponding to less jitter on the output signal. However, as alluded to earlier, the complexity of the phase expander is increased, and the VCO frequency would need to be doubled to produce the same output frequency.

Figure 7c shows a phasor diagram for N = 24, M = 5. This case has an output signal with a frequency of 5/12 f_Vco, and a relatively low spread in the selected components. Again however the complexity of the phase expander required to produce a 24-part output may be prohibitive. It will be appreciated by those skilled in the art that the invention has been illustrated by describing one or more specific embodiments thereof, but is not limited to these embodiments; many variations and modifications are possible, within the scope of the accompanying claims.

Claims

1. A circuit portion comprising:

2. The circuit portion as claimed in claim 1 , further comprising at least one delay element arranged to add a delay to at least one of the selected parts prior to being combined to provide the second digital signal.

3. The circuit portion as claimed in claim 2, wherein a plurality of delay elements are provided on respective signal parts.

4. The circuit portion as claimed in claim 2 or 3, wherein one or more of the delay element(s) is a resistor.

5. The circuit portion as claimed in any preceding claim, wherein the phase expansion portion comprises a frequency divider and a phase expander.

6. The circuit portion as claimed in claim 5, wherein the frequency divider is arranged to receive the oscillating input signal and output an X-part signal, where each part has a 1/X duty cycle and is evenly spaced in phase.

7. The circuit portion as claimed in claim 5 or 6, wherein the phase expander is arranged to receive the X-part signal and output an N-part signal, where N is larger than X.

8. The circuit portion as claimed in claim 6 or 7, wherein X is equal to 4.

9. The circuit portion as claimed in any preceding claim, wherein the phase selection portion selects M parts of the first digital signal to produce the second digital signal.

10. The circuit portion as claimed in claim 9, wherein M is an odd number.

1 1. The circuit portion as claimed in claim 10, wherein M is 3, 5 or 7.

12. The circuit portion as claimed in any of claims 9-11 , wherein N is greater than 2M.

13. The circuit portion as claimed in any of claims 7-12, wherein N is a multipl of 4.

14. The circuit portion as claimed in any of claims 7-13, wherein N is chosen from the group 8, 12, 16, 20 and 24.

15. The circuit portion as claimed in any of claims 9-14, wherein M = 3 and N = 8.

16. The circuit portion as claimed in any of claims 9-14, wherein M = 3 and N = 16.

17. The circuit portion as claimed in any preceding claim, wherein the circuit portion is battery powered.

18. The circuit portion as claimed in any preceding claim, wherein the phase expansion and/or phase selection portions are provided on an integrated circuit.

19. A radio frequency transmitter system comprising:

a baseband module;

an antenna; and

a frequency synthesiser, which comprises a circuit portion according to any preceding claim; wherein a digital signal provided by the circuit portion is used as a local oscillator signal to modulate a baseband signal provided by the baseband module to produce an output signal for broadcast on the antenna.