JP2004110900A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory having a page mode in a virtual grounding system which reduces the influence of disturbance. <P>SOLUTION: Intermediate grounding lines 31-0, etc., 34-0, 31-1, and 32-1 to which the switches of Y selectors 5 connected to bit lines 2 connected with the sources of memory cells 3 are made independent by each of respective page blocks and the respective intermediate grounding lines are made independently settable as to whether the grounding lines are connected to the ground or made floating. During a reading-out operation, all the intermediate grounding lines are grounded, but during a writing operation, only the intermediate grounding lines of the page blocks to which the memory cells performing the writing operation belong are grounded and the other intermediate grounding lines are kept floating. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device (nonvolatile memory) such as a flash memory, and in particular, a virtual ground (Virtual) that can select whether a source-side bit line selected by a Y selector is connected to ground or floating. (Ground) type nonvolatile memory.
[0002]
[Prior art]
Non-volatile memories include EPROM, E ² PROM, flash memory, and the like are known, each having various modifications. The present invention can be applied to any nonvolatile memory as long as it is a virtual ground system, but here, a flash memory, particularly a flash memory called a NOR type will be described as an example. Since the flash memory is widely used and its basic configuration is widely known, a detailed description of the flash memory is omitted here, and only the portion related to the present invention will be described.
[0003]
FIG. 1 is a diagram showing an array configuration of a virtual ground flash memory. As illustrated, a plurality of word lines 1 and a plurality of bit lines 2 orthogonal to the plurality of word lines 1 are arranged, and a plurality of nonvolatile memory cells 3 are arranged corresponding to the intersections. Is called a memory cell array. Each memory cell is composed of a transistor having a floating gate, the gate is connected to the word line 1, and the source and drain are connected to the adjacent bit line 2, respectively. The X decoder 4 applies a voltage to one of the plurality of word lines 1 to select a row (row) of the memory cell array to be accessed. The Y selector 5 connects two adjacent ones of the plurality of bit lines to the read / write (R / W) circuit 7 and the ground circuit 8 of the I / O circuit 6, respectively.
[0004]
For example, when accessing the memory cell indicated by reference numeral 11 in FIG. 1, the X decoder 4 applies a selection voltage to the lowermost word line, and the Y selector 5 corresponds to the source of the memory cell 11. The bit line indicated by G is connected to the ground circuit 8, and the bit line indicated by D corresponding to the drain is connected to the R / W circuit 7. At the time of writing, the R / W circuit 7 is in a writing state, and at the time of reading, the R / W circuit 7 is in a reading state. At this time, another bit line adjacent to the bit line indicated by D is in a floating state. Therefore, the drain of the memory cell adjacent to the memory cell 11 is connected to the R / W circuit 7 and a selection voltage is applied to the gate, but no read or write operation is performed.
[0005]
As described above, in the configuration of the memory cell array of FIG. 1, not only can the drain side bit line (drain bit line) be connected to the R / W circuit 7 but also the source side bit line (source bit) can be selected. It is necessary to be able to select whether the line) is connected to the ground circuit 8 or not (is floating when not connected). This is a system called a virtual ground system. Therefore, in the case of the virtual ground method, a selection circuit (switch) for selecting whether to connect the terminal of the Y selector 5 connected to the drain bit line to the R / W circuit 7 and a Y selector connected to the source bit line. Both of the selection circuits for selecting whether the 5 terminals are connected to the ground circuit 8 are necessary. The Y selector 5 selects two adjacent bit lines, and the selected two bit lines are connected to the corresponding R / W circuit 7 or ground circuit 8 respectively.
[0006]
The current flash memory can be partially erased in units of sectors. The flash memory has a multi-bit data input / output. FIG. 2 is a diagram showing a configuration of a one-sector flash memory having a multi-bit configuration. As shown in FIG. 2, one sector memory cell array (usually a flash memory is provided with a plurality of memory cell arrays) is divided into a plurality of blocks 10-0 to 10-n along the bit lines. In each block, data input / output (I / O) circuits 6-0 to 6-n and Y selectors (Ysel) 5-0 to 5-n are provided, and (n + 1) pieces of data corresponding to the number of blocks are parallelized. I can input and output. For example, when data is input / output with a 16-bit width, one sector is set to 512K bits and arranged in 512 × 1024. This is divided into 16 blocks composed of 512 × 64 memory cells, and data is input / output in parallel to the memory cell array of 16 blocks. Note that one sector word line is common, and the memory cell array connected to the same word line of 16 blocks is accessed.
[0007]
Further, recent flash memories have an operation mode capable of high-speed data reading called a page mode. FIG. 3 is a diagram showing the configuration of the flash memory in the multi-bit page mode. As shown in the drawing, each of the blocks 10-0 to 10-n (here, n is 16) is further added to a plurality (for example, four here) of page blocks 10-0-0 to 10-0- along the bit line. 3, 10-1-0 to 10-1-3,..., 10-n-0 to 10-n-3, and each block has a data input / output (I / O) circuit 6 corresponding to each page block. -0-0 to 6-0-3, ... 6-n-0 to 6-n-3 and Y selector (Ysel) 5-0-0 to 5-0-3, ... 5-n-0 to 5- n-3 and multiplexers 9-0, 9-1,..., 9-n are provided for each block. At the time of reading, data is simultaneously read from four memory cells of four page blocks of each block, and data corresponding to one page block is selected and sequentially output by a multiplexer. Since the same operation is performed in each block, in the above example, 4n memory cells are read simultaneously, and the read 4n-bit data is output in 4 cycles of n bits. . Compared with the read operation from the memory cell, the conversion operation by the multiplexer can be performed at a high speed, and thus the data can be read at a speed four times faster. Here, an example is shown in which each block is divided into four page blocks. However, it is also possible to divide each block into other numbers such as eight.
[0008]
Further, the page mode is provided only for the data read operation, and is not provided for the write operation. This is because the write operation requires a relatively high voltage to be applied to each part of the memory cell, so the operation time is long and the amount of current is large, and the write operation is performed less frequently than the read operation. There is no particular problem.
[0009]
In a flash memory, a predetermined voltage is applied to a word line and a bit line to which a memory cell to be accessed is connected. Therefore, electrical stress is also applied to other memory cells connected to the word line and the bit line to which a predetermined voltage is applied, and the stored contents are adversely affected. This is called disturb, and at the time of writing, an unselected memory cell in the erased state may be affected by the writing.
[0010]
During the write operation, a higher voltage (a larger absolute value) than that during the read operation is applied to each part of the memory cell (transistor) to inject electrons into the floating gate. As shown in FIG. 1, when a selection voltage for writing is applied to a word line and two adjacent bit lines are connected to an R / W circuit 7 and a ground circuit 8, data can be written to the memory cell 11. it can. At this time, a drain voltage for writing is applied to the bit line D from the R / W circuit 7, and the bit line G is connected to the ground. Therefore, in the memory cells connected to the bit lines D and G other than the memory cell 11 (memory cells in the same column as the memory cell 11), the selection voltage is not applied to the gate, but the drain and the source are for writing. A voltage is applied and an electrical stress is applied. This is called a drain disturb. In addition, since memory cells other than the memory cell 11 connected to the word line to which the selection voltage is applied are applied with a selection voltage for writing to the gate, problems such as data change may occur in the same manner. This is called gate disturb.
[0011]
Japanese Patent Laid-Open No. 2000-68485 is floating in order to prevent erroneous data from being written in non-selected cells due to the floating of some source lines and drain lines during writing in the virtual ground method. A technique for setting the source line and the drain line to an appropriate potential is disclosed.
[0012]
In the virtual ground flash memory, it has been found that the memory cell adjacent in the row direction of the memory cell to be accessed is more stressed than the disturb. FIG. 4 is a diagram for explaining the stress on the adjacent memory cell.
[0013]
As shown in FIG. 4A, in order to write to the memory cell A surrounded by a circle, a write gate voltage (a voltage higher than that at the time of reading) is applied to the word line to which the gate is connected, and the drain is connected. A write drain voltage (a voltage higher than that at the time of reading) is applied to the bit line to be connected, and the bit line to which the source is connected is grounded. At this time, the write gate voltage is applied to the gate of the memory cell adjacent to the memory cell A, the write drain voltage is applied to the drain, and the source is floating.
[0014]
As described above, the flash memory is divided into blocks in order to increase the number of bits, and writing is performed in parallel to the memory cells of each block. If the block configuration is as shown in FIG. As shown in A), the bit line to which the source of the memory cell B separated by 64 cells in the row direction is connected is grounded. A write gate voltage is applied to the word line, all the memory cells connected to the word line are in a conductive state, and the source of the memory cell adjacent to the memory cell A is grounded through the 64 conductive cells. Will be grounded. Therefore, the disturbance becomes larger than that in the conventional method in which the bit line to which the drain is connected is not shared by adjacent columns, that is, in the case of not using the virtual ground method. Actually, the memory cell has an on-resistance, and the sum of the resistances of the 64 memory cells is large. Therefore, the source of the adjacent memory cell is not completely grounded, and hardly causes a problem.
[0015]
However, as shown in FIGS. 4B and 4C, when the width of one block is 16 cells or 8 cells, the memory cells C and D and E and F accessed in the adjacent blocks are used. Since the number of cells in between decreases and the total on-resistance of the memory cells also decreases, the disturbance increases and the adverse effects cannot be ignored. Therefore, when dividing into a plurality of blocks in order to increase the number of bits, it is necessary to determine the block width so that the block width (number of cells) does not become smaller than a predetermined value.
[0016]
[Patent Document 1]
JP 2000-68485 A (all).
[0017]
[Problems to be solved by the invention]
As described above, the page mode is provided for high-speed data reading. In the page mode, each block is further divided into a plurality of page blocks, a Y selector and an input / output circuit are provided for each page block, and memory cells of a plurality of page blocks of the plurality of blocks are simultaneously accessed during a read operation. Since it is difficult to make the operation of the Y selector different between the read process and the write process due to the number of wirings and the like, the memory cells of a plurality of page blocks in a plurality of blocks are simultaneously accessed even during the write operation. As shown in (B) and (C), the problem arises that the interval between the memory cells in which the write operation is simultaneously performed becomes narrow. For example, when one block width is 64 cells and each block is divided into 4 page blocks, the memory cell interval at which the write operation is performed simultaneously becomes 16 cells as shown in FIG. Is divided into 8 page blocks, it becomes 8 cells, and the disturbance cannot be ignored.
[0018]
In order to solve such a problem, in the page mode, memory cells of a plurality of page blocks of a plurality of blocks are accessed at the same time only during a read operation, and memory cells of a plurality of blocks are accessed at the same time during a write operation. As a reference example, a solution focusing on the fact that the memory cells of a plurality of page blocks are not accessed simultaneously in each block. In this reference example, the number of intermediate ground lines corresponding to the number of page blocks is provided, and the source bit line of each page block is connected to the corresponding intermediate ground line via the Y selector, and each intermediate ground line is connected to the ground. In the read operation, all these switches are turned on and all intermediate ground lines are connected to the ground. In the write operation, only the intermediate ground line corresponding to the page block to be accessed is connected to the ground. It is conceivable to control the switch so that the intermediate ground line is in a floating state. However, this solution has problems and is practically ineffective.
[0019]
FIG. 5 is a diagram for explaining that the above reference example is insufficient, and shows a case where the width of one block is 64 cells and each block is divided into four page blocks. As shown in the figure, four intermediate ground lines ARVSS 21 to 24 are provided, and each intermediate ground line is connected to the ground via switches (transistors) 25 to 28. When writing to a memory cell G in a certain block, the switch of the Y selector connected to the bit line to which the source of the memory cell G is connected is turned on, and the bit lines 16, 32, and 48 are separated. The switch of the connected Y selector is turned on and the switch 25 is turned on, but the switches 26 to 28 are turned off. Similarly, since writing is also performed on the memory cell H in the adjacent block, the switch of the Y selector connected to the bit line to which the source of the memory cell H is connected is turned on, and 16, 32, 48 The switch of the Y selector connected to the bit line far away is turned on.
[0020]
The switch of the Y selector connected to the bit line to which the source of the memory cell adjacent to the memory cell G is connected is OFF, but the dotted line extending from this bit line to the ground via the ON memory cell and the switch Such a path is formed. As shown in the figure, since all the memory cells in this row are in the on state, the source of the memory cell adjacent to the memory cell G is connected to the switch of the on-state Y selector through 15 memory cells. Connected to the ground line 22. The switch 26 of the intermediate ground line 22 is off, but the intermediate ground line 22 is an on-state Y selector switch of an adjacent block connected to the intermediate ground line 22, 16 on-state memory cells, on-state Are connected to the intermediate ground line 21 through the switch of the Y selector. If the on-resistance of the switch is ignored, the intermediate ground line 22 is connected to the intermediate ground line 21 through a path in which 16 on-resistances of the memory cells are connected in series. When the input / output data width is 16 bits, there are 16 blocks, and 15 paths from the intermediate ground line 22 to the intermediate ground line 21 exist in parallel. Therefore, the resistances of these paths are combined. Then, the resistance of the path from the intermediate ground line 22 to the intermediate ground line 21 is 16/15 of the on-resistance of the memory cell. Therefore, the source of the memory cell adjacent to the memory cell G is grounded to the ground with a resistance of (15 + 16/15) = 16.07 times the on-resistance of the memory cell. That is, it can be seen that the disturbance substantially the same as the case where the write operation is simultaneously performed on two memory cells separated by 16 cells as shown in FIG.
[0021]
As described above, the solution shown in FIG. 5 is insufficient.
[0022]
An object of the present invention is to realize a non-volatile semiconductor memory having a page mode in a virtual ground method with reduced influence of disturb.
[0023]
[Means for Solving the Problems]
In order to achieve the above object, the nonvolatile semiconductor memory device of the present invention is configured such that an intermediate ground line to which a switch of a Y selector connected to a bit line to which a memory cell source is connected is connected to each page block independently. The intermediate ground line of each page block can be independently set to be connected to the ground or floating. In the read operation, all intermediate ground lines are grounded. In the write operation, only the intermediate ground line of the page block to which the memory cell performing the write operation belongs is grounded, and the other intermediate ground lines are set in a floating state.
[0024]
According to the present invention, during the write operation, in each block, the intermediate ground line of the page block of the memory cell to be accessed is grounded, but the intermediate ground lines of other page blocks are not grounded, and each intermediate ground line Since they are independent, a route passing through an adjacent block is not formed. Therefore, the source of the memory cell adjacent to the memory cell to which writing is performed during the writing operation is grounded via the number of cells having the block width as in the case of the page mode, and the disturbance is small.
[0025]
Naturally, the read / write (R / W) circuit for each page block in each page block is in all read states at the time of reading, and only one corresponding R / W circuit in each block is written at the time of writing. The other R / W circuits are turned off.
[0026]
One switch circuit is provided between the intermediate ground line and the ground, and this is switched on / off to switch the intermediate ground line between ground and floating.
[0027]
Alternatively, a common ground line may be provided, each intermediate ground line may be connected to a corresponding common ground line via a switch, and the common ground line may be grounded via a switch. With this configuration, for example, the intermediate ground line can be set to an appropriate voltage other than the ground.
[0028]
In a memory cell array, when a bit line to which only the source of the memory cell is connected and a bit line to which only the drain of the memory cell are connected are alternately arranged, each bit line is connected to the R / W circuit via the Y selector. And only one of the ground circuits.
[0029]
In recent years, there has been proposed a new flash memory called an NROM that can store a binary value in one memory cell by reversing the voltage applied to terminals corresponding to the source and drain of one memory cell. The present invention is also applicable to this NROM. When the present invention is applied to an NROM, it is necessary to selectively connect each bit line to both the R / W circuit and the ground circuit. Therefore, a plurality of ground switches for independently connecting the Y selector terminals of each page block to the ground and an R / W switch for connecting to the R / W circuit are provided. The Y selector by page block of each page block is connected to other terminals so that the three adjacent ones are not connected to a plurality of common Y lines with a reduced number, and the same number of grounds as the number of common Y lines. A switch and an R / W switch are provided, and each common Y line is connected to both the ground switch and the R / W switch. Thereby, the number of switches can be reduced.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 6 is a diagram showing the configuration of the Y selector and I / O circuit portion of the flash memory according to the first embodiment of the present invention. The flash memory according to the first embodiment is a flash memory having a multi-bit page mode in the virtual ground system shown in FIGS. 1 to 3, and a memory cell array having a width of 1024 cells is replaced with 16 blocks having a width of 64 cells. Assume that each block is further divided into four page blocks each having a 16-cell width.
[0031]
As shown in the drawing, the bit lines (drain bit lines) to which the drains of the memory cells of each page block are connected are drain lines 41-0 and 42-0 for each page block via the Y switch (transistor) of the Y selector 5. , 43-0, 44-0, 41-1, and 42-1 are connected. The drain lines 41-0, 42-0, 43-0, 44-0, 41-1, and 42-1 for each page block are R / W switches (transistors) 45-0, 46-0, 47-0, 48. R / W circuits 6-0-0, 6-0-1, 6-0-2, 6-0-3, 6-1-0, 6-6 through -0, 45-1, 46-1. Connected to 1-2. The bit lines (source bit lines) to which the memory cell sources of each page block are connected are connected to the page block-specific ground lines (intermediate ground lines) 31-0 and 32-0 via the Y switch (transistor) of the Y selector 5. , 33-0, 34-0, 31-1, 32-1. The intermediate ground lines 31-0, 32-0, 33-0, 34-0, 31-1, 32-1 are connected to ground switches 35-0, 36-0, 37-0, 38-0, 35-1, It is connected to the ground via 36-1. The ground switches 35-0, 36-0, 37-0, 38-0, 35-1, and 36-1 correspond to the above-described ground circuit.
[0032]
FIG. 7 is a diagram illustrating a configuration of each R / W circuit. The R / W signal connected through the R / W switches 45-0, 46-0, 47-0, 48-0, 45-1, and 46-1 is connected to the writing unit and the reading unit. During the write operation, the program EN signal becomes “high (H)” in the write unit, the output of the NAND gate 51 changes according to the program data, the level is adjusted by the level shift circuit 52, and the gate of the transistor 53 is changed. Applied. A voltage Vprog for programming (writing) is supplied to the source of the transistor 53, and when the write data is changed from “1” to “0”, a high voltage is output as an R / W signal. During the read operation, the read EN becomes “H”, and the R / W signal is supplied to the inverter 55 and the transistor 56 through the transistor 54. When the R / W signal is “low (L)”, the transistor 56 is turned on and “L” is output as a read output, and when the R / W signal is “H”, the transistor 56 is turned off. “H” is output as a read output.
[0033]
Returning to FIG. 6, during the read operation, the ground switches 35-0, 36-0, 37-0, 38-0, 35-1, 36-1 and the R / W switches 45-0, 46-0, 47-0. , 48-0, 45-1, and 46-1 are all turned on, and data is read from memory cells of a plurality of page blocks of a plurality of blocks. In this example, data is read from 64 memory cells.
[0034]
In the write operation, writing is performed on the memory cells of one page block in each block. In this example, writing is performed on 16 memory cells. For example, when writing to the memory cell of the leftmost page block of each block, the ground switches 35-0 and 35-1 and the R / W switches 45-0 and 45-1 are turned on, and the ground switch All of 36-0, 37-0, 38-0, 36-1 and R / W switches 46-0, 47-0, 48-0, 46-1 are turned off. At this time, the source of the memory cell adjacent to the memory cell to be written is connected to the intermediate ground line 32-0 via the ON switch of the adjacent page block via the 15 ON memory cells. However, since the intermediate ground line 32-0 is not connected to other intermediate ground lines and the ground switch 36-0 is in an off state and is floating, no disturbance occurs. Therefore, the source of the memory cell adjacent to the memory cell to be written is connected to the bit line grounded to the ground of the adjacent block via the 64 on-state memory cells. This is the state of FIG. 4A, and disturb does not become a problem.
[0035]
Comparing the circuit of the first embodiment of FIG. 6 with the circuit of the reference example of FIG. 5, in the circuit of FIG. 5, there are four switches 25 to 28 for connecting the intermediate ground lines 21 to 24 to the ground. In the circuit of FIG. 6, it is necessary to provide 64 ground switches, which is disadvantageous in that the number of ground switches is 16 times. However, since the total number of ground switches in the circuit of FIG. 5 is only four, it is necessary to increase the driving capability as compared with the ground switch of the circuit in FIG. 6, and the required area is not so different.
[0036]
FIG. 8 is a diagram for explaining this. FIG. 8A shows the size of the ground switch of the circuit of FIG. 5, and FIG. 8B shows the size of the ground switch of the circuit of FIG. In FIG. 8, transistors indicated by T1 and T3 correspond to ground switches, ARVSS (w) corresponds to the intermediate ground lines (ARVSS) 21 to 24 in FIG. 5, and ARVSSnw represents the intermediate ground lines 31-0 and 31-0 in FIG. It corresponds to any one of 32-0, 33-0, 34-0, 31-1, 32-1,. The size of the transistor constituting the ground switch of FIG. 6 is 1/16 of that of FIG. Note that the signal for controlling the ground switch in FIG. 6 is the same control signal as that for the R / W switch. If the ground switch and the R / W switch are arranged close to each other, an increase in the area due to wiring hardly poses a problem.
[0037]
In FIG. 8, transistors indicated by T2 and T4 are switches that connect the intermediate ground line to the global Vss line (GARVSS), and are not shown in FIGS. The source bit line is not only grounded to the ground or in a floating state, but a small voltage value may be applied, and such a voltage is supplied to the global Vss line.
[0038]
FIG. 9 is a diagram showing a configuration of the Y selector and the ground connection portion of the flash memory according to the second embodiment of the present invention. Here, only the Y switch transistor connected to the source bit line and the portion related to the intermediate ground line to which they are connected are shown, and the Y switch transistor and R / W circuit connected to the drain bit line are omitted. It is. As shown in the figure, a common ground line 61 is provided, and each ground line is connected to the common ground line 61 via intermediate ground switches 51-0, 52-0, 53-0, 54-0, 51-1. The common ground line 61 is a global Vss line (GARVSS), and may be grounded via the common ground switch 65 or may be supplied with an appropriate voltage.
[0039]
In the second embodiment, during the write operation, only the intermediate ground switch of the page block to which the memory cell to be written belongs is turned on, and the other intermediate ground switches are turned off. Disturbance does not matter.
[0040]
FIG. 10 shows the sizes of the intermediate ground switch and the common ground switch of the circuit of the second embodiment. T6 corresponds to an intermediate ground switch, and T5 corresponds to a common ground switch. The number of intermediate ground switches in the circuit of FIG. 9 is 16 times the number of transistors indicated by T1 in FIG. 8, but the size is 1/6. The number of common ground switches in the circuit of FIG. This is 1/4 times the number of transistors indicated by T2, but the size is 13 times. Therefore, the size of the transistor is somewhat larger as a whole.
[0041]
FIG. 11 is a diagram showing the overall configuration of the flash memory according to the third embodiment of the present invention. The flash memory of the third embodiment applies the present invention to an NROM capable of storing binary values in one memory cell by reversing the voltage applied to terminals corresponding to the source and drain of one memory cell. This is an example. As shown, the memory cell array is divided into n blocks, and each block is further divided into eight page blocks 10-0-0, 10-0-1,..., 10-0-7, 10-1-0,. , 10-1-7, 10-n-0,..., 10-n-7. Accordingly, the Y selectors (Ysel) for each page block 5-0-0, ..., 5-0-7, 5-1-0, ..., 5-1-7, 5-n-0, ..., 5 -N-7 and page block specific I / O circuits 6-0-0, ..., 6-0-7, 6-1-0, ..., 6-1-7, 6-n-0, ..., 6 -N-7 and n multiplexers (MUX) are provided.
[0042]
FIG. 12 is a diagram showing the configuration of a set of page block-specific Y selectors and page block-specific I / O circuits. In the NROM, each bit line becomes both a drain bit line and a source bit line. Each bit line is connected to switches (transistors) 5-0 to 5-7 of the Y selector. The switch terminals of the Y selector are connected to the 0th and the 4th, the 1st and the 5th, the 2nd and the 6th, the 3rd and the 7th, respectively, and R respectively via the R / W switches 71-0 to 71-3. / W circuit 7 and connected to switch 73 via ground switches 72-0 to 72-3. The switch 73 is connected to the ground and corresponds to a ground circuit. Two adjacent Y selector switches 5-0 to 5-7 are selected, and one of the two Y selector switches is connected to the R / W circuit 7 when the corresponding R / W switch is turned on. On the other hand, the corresponding ground switch is turned on and grounded. In this way, any bit line can be selectively connected to both the R / W circuit 7 and the ground.
[0043]
Since the operation of the flash memory of the third embodiment is the same as that of the first embodiment, it is omitted here.
[0044]
【The invention's effect】
As described above, in the nonvolatile semiconductor memory having the page mode in the virtual ground system of the present invention, the influence of disturb can be reduced and the reliability can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing an array configuration of a virtual ground flash memory.
FIG. 2 is a diagram illustrating a configuration of a multi-bit flash memory.
FIG. 3 is a diagram showing a configuration of a flash memory in a multi-bit page mode.
FIG. 4 is a diagram for explaining the influence of cell spacing when simultaneously writing in a multi-bit virtual ground flash memory.
FIG. 5 is a diagram illustrating a problem of a reference example in which common ground lines are provided for the number of cells that are simultaneously read in the page mode.
FIG. 6 is a diagram showing a configuration of a Y selector and an I / O circuit portion of the flash memory according to the first embodiment of the present invention.
FIG. 7 is a diagram illustrating a configuration example of an R / W circuit.
FIG. 8 is a diagram showing a comparison of transistor sizes between a reference example and a first example.
FIG. 9 is a diagram showing a configuration of a Y selector and a ground connection portion of a flash memory according to a second embodiment of the present invention.
FIG. 10 is a diagram showing the transistor size of the second embodiment.
FIG. 11 is a diagram showing an overall configuration of a flash memory according to a third embodiment of the present invention.
FIG. 12 is a diagram showing a configuration of a Y selector and an I / O circuit portion of a third embodiment.
[Explanation of symbols]
1 ... Word line
2 ... Bit line
3. Memory cell
4 ... X decoder
5 ... Y selector
6 ... I / O circuit
7 ... R / W circuit
8 ... Ground circuit
31-0 to 34-0, 31-1, 32-1 ... Intermediate ground line
35-0 to 38-0, 35-1, 36-1 ... Ground switch

Claims (8)

A memory having a plurality of word lines, a plurality of bit lines orthogonal to the plurality of word lines, and a plurality of nonvolatile memory cells arranged corresponding to intersections of the plurality of word lines and the plurality of bit lines A cell array; an X decoder for selectively driving the plurality of word lines; a Y selector for selecting the plurality of bit lines; a read / write circuit to which a corresponding terminal of the Y selector is connected; and a ground circuit. A data input / output circuit,
The memory cell array includes a plurality of blocks along the bit line, and each block includes a data input / output circuit and a Y selector,
The memory cells of the plurality of blocks are accessed simultaneously, and data corresponding to the number of bits corresponding to the number of blocks is input / output simultaneously,
The memory cell array of each block further includes a plurality of page blocks along the bit line, and each page block includes a data input / output circuit for each page block and a Y selector for each page block,
Each block further includes a multiplexer that selects data corresponding to one page block from data simultaneously read from a plurality of page blocks in each block,
When reading data from the device, data is simultaneously read from the memory cells of the plurality of page blocks of the plurality of blocks, and then the data of each page block is selected by the multiplexer, and the bit corresponding to the number of blocks Several minutes of data are output as continuous data corresponding to the number of page blocks,
When writing data to the device, in a nonvolatile semiconductor memory device that simultaneously writes data to one memory cell in each block,
The data input / output circuit for each page block of each page block includes a read / write circuit for each page block and a ground circuit for each page block,
The Y selector for each page block of each page block is connected to the corresponding read / write circuit for each page block or the ground circuit for each page block,
When reading, all the page block ground circuits are turned on and the corresponding page block Y selector terminals are connected to the ground. When writing, only one page block ground circuit in each block is turned on. The corresponding page block Y selector terminal is connected to the ground in the state, and the other page block ground circuit is turned off and the corresponding page block Y selector terminal is in the floating state. A non-volatile semiconductor memory device. At the time of reading, all the read / write circuits for each page block are in a read state, and at the time of write, only one of the read / write circuits for each page block in each block is in a write state. The nonvolatile semiconductor memory device according to claim 1, wherein the write circuit is turned off. 2. The nonvolatile semiconductor memory device according to claim 1, wherein each page block-specific ground circuit includes one switch circuit that commonly connects the corresponding page block-specific Y selector terminal to the ground. A common ground wire,
A common ground switch circuit for connecting the common ground line to the ground,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of page block-specific ground circuits of the plurality of blocks include an intermediate switch circuit that connects a terminal of the corresponding page block-specific Y selector to the common ground line. The nonvolatile semiconductor memory device according to claim 1, wherein each bit line is connected to only one of the read / write circuit and the ground circuit. The nonvolatile semiconductor memory device according to claim 1, wherein each bit line is selectively connected to both the read / write circuit and the ground circuit. The ground circuit for each page block includes a plurality of ground switches for independently connecting terminals of the Y selectors for each page block in the block to the ground,
The nonvolatile semiconductor memory device according to claim 6, wherein the page block read / write circuit includes a plurality of R / W switches for independently connecting to the terminals of the page block Y selectors in the block. The terminals of the page block Y selectors in each block are connected to other terminals so that the three adjacent ones are not connected, and the number of common Y lines is less than half the number of terminals of the page block Y selectors. Forming,
The number of the ground switches and the R / W switches is the same as the number of the plurality of common Y lines,
The nonvolatile semiconductor memory device according to claim 7, wherein the plurality of common Y lines are connected to both the ground switch and the R / W switch.

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