CN113345489B

CN113345489B - Memory and operation method thereof

Info

Publication number: CN113345489B
Application number: CN202110722171.5A
Authority: CN
Inventors: 郭路; 陶伟; 曹坚; 陶媛; 程泊轩
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-06-28
Filing date: 2021-06-28
Publication date: 2023-08-08
Anticipated expiration: 2041-06-28
Also published as: CN113345489A

Abstract

The embodiment of the invention provides a memory and an operation method thereof. Wherein the memory comprises: at least one memory cell array block including a plurality of memory cells and a word line layer disposed corresponding to each of the memory cells; a word line driver coupled to the memory cell array block; and a control circuit for controlling the word line driver; the memory cell array block includes: a first memory cell array sub-block and a second memory cell array sub-block disposed adjacent to each other; and a sub-block configuration area including K memory cell layers and corresponding K word line layers disposed between the first memory cell array sub-block and the second memory cell array sub-block, and for controlling selection of the first memory cell array sub-block and the second memory cell array sub-block, wherein K is an integer greater than or equal to 2; and the number of the storage unit layers for storing data of the first storage unit array sub-block is equal to that of the storage unit layers for storing data of the second storage unit array sub-block through the sub-block configuration area.

Description

Memory and operation method thereof

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a memory and an operating method thereof.

Background

With the continuous development of three-dimensional NAND-type memory technology, the number of layers of a stacked structure in a three-dimensional NAND-type memory is increased from 24 layers to 48, 96, 128, 192, and even higher layers, so that the capacity of a single storage array block in the memory is increased. However, in the context of the current mainstream of a high layer number, there is still a need for a small-capacity memory cell array block. Therefore, it is desirable to provide a memory that can accommodate the needs of small memory cell array blocks without requiring firmware update.

Disclosure of Invention

In order to solve one or more of the existing technical problems, an embodiment of the invention provides a memory and an operation method thereof.

The embodiment of the invention provides a memory, which comprises:

at least one memory cell array block including a plurality of memory cells and a word line layer disposed corresponding to each of the memory cells;

a word line driver coupled with the memory cell array block; and

a control circuit for controlling at least the word line driver; the memory cell array block comprises a first memory cell array sub-block and a second memory cell array sub-block which are adjacently arranged; and

A sub-block configuration region including K memory cell layers and corresponding K word line layers disposed between the first memory cell array sub-block and the second memory cell array sub-block, and for controlling selection of the first memory cell array sub-block and the second memory cell array sub-block, wherein K is an integer greater than or equal to 2;

and enabling the number of storage unit layers of the first storage unit array sub-block for storing data to be equal to the number of storage unit layers of the second storage unit array sub-block for storing data through the sub-block configuration area.

In the above aspect, the memory cell array block is formed by a three-dimensional stacked structure including a first sub-stacked structure and a second sub-stacked structure stacked adjacently;

the first sub-stack structure is provided with M layers of memory cell layers and corresponding M layers of word line layers, and the second sub-stack structure is provided with N layers of memory cell layers and corresponding N layers of word line layers, wherein M and N are integers greater than or equal to 2 and M is greater than N;

wherein the K-layer memory cell layers and the corresponding K-layer word line layers of the sub-block configuration region are included in the first sub-stack structure.

In the above aspect, the first memory cell array sub-block is entirely included in the first sub-stack structure.

In the above scheme, the N memory cell layers and the corresponding N word line layers of the second sub-stack structure are defined in the second memory cell array sub-block, and the F memory cell layers and the corresponding F word line layers of the first sub-stack structure are defined in the second memory cell array sub-block through the sub-block configuration area, F is an integer greater than or equal to 1, where (f+n) is equal to the number of memory cell layers for storing data of the second memory cell array sub-block, and (M-F-K) is equal to the number of memory cell layers for storing data of the first memory cell array sub-block.

In the above scheme, the number of storage unit layers for storing data of the first storage unit array sub-block and the second storage unit array sub-block is C, where C is an integer greater than or equal to 2;

wherein C2+K = m+n.

In the above aspect, the word line driver includes:

a first sub-driver for driving a word line layer of the first memory cell array sub-block;

a second sub-driver for driving a word line layer of the second memory cell array sub-block correspondingly; and

and a third sub-driver for driving the K-layer word line layer of the sub-block configuration region.

In the above scheme, the control circuit is configured to control the third sub-driver and the first selection transistor corresponding to the first memory cell array sub-block to implement selection control of the first memory cell array sub-block; the control circuit is further configured to control the third sub-driver and a second selection transistor corresponding to the second memory cell array sub-block to realize selection control of the second memory cell array sub-block.

In the above scheme, the K-layer word line layer includes a first word line layer and a second word line layer, and the K-layer memory cell layer includes a first memory cell layer and a second memory cell layer corresponding to the first word line layer and the second word line layer, respectively;

the first word line layer, the first memory cell layer and the first selection transistor are used for controlling and selecting the first memory cell array subblock, and the second word line layer, the second memory cell layer and the second selection transistor are used for controlling and selecting the second memory cell array subblock.

In the above scheme, the K-layer memory cell layer is not used for storing data.

In the above scheme, the first sub-stack structure and the second sub-stack structure further have a dummy memory cell layer and a corresponding dummy word line layer.

In the above scheme, the memory cell array block includes a plurality of word line layers, and a plurality of dummy word line layers asymmetrically interposed in the plurality of word line layers; the multi-layer word line layer comprises a first type word line layer and a second type word line layer; a memory cell layer coupled to the first type word line layer for forming the first memory cell array sub-block and the second memory cell array sub-block; the second type word line layer is used for forming the sub-block configuration area.

In the above scheme, K is an odd number or an even number.

In the above solution, the memory further includes: a first bad block detection circuit provided corresponding to the first memory cell array sub-block and configured to detect a bad block condition of the first memory cell array sub-block;

and the second bad block detection circuit is arranged corresponding to the second storage unit array sub-block and used for detecting bad block conditions of the second storage unit array sub-block.

In the above scheme, the first bad block detection circuit and/or the second bad block detection circuit is configured to output the result identifier in a multi-bit binary data manner.

In the above scheme, the memory comprises a three-dimensional NAND type memory.

The embodiment of the invention also provides a memory system, which comprises:

One or more memories as described in the above embodiments; and

a memory controller coupled to the memory.

In the above aspect, the memory controller is configured to designate corresponding memory cell layers and word line layers from the memory cell array block as the K-layer memory cell layers and the K-layer word line layers, respectively, to define the sub-block configuration region.

An embodiment of the present invention further provides a method for operating the memory according to any one of the above embodiments, where the memory includes:

receiving a first instruction, wherein the first instruction characterizes that the memory cell array block is erased, read or written by adopting a sub-block mode;

selecting the first storage unit array subblock and/or the second storage unit array subblock in the storage unit array block by driving and controlling the subblock configuration region;

and performing erasing, reading or writing operation on the memory cell layers in the selected first memory cell array subblock and/or the second memory cell array subblock.

In the above scheme, the method further comprises:

receiving a second instruction; the second instruction represents that the memory cell array block is erased, read or written by adopting a block mode;

Selecting a memory cell array block;

an erase, read, or write operation is performed on the memory cell layers in the selected memory cell array block.

In the above scheme, the memory further comprises a substrate;

the performing an erase operation on memory cells in the selected memory cell array sub-block includes:

applying a first voltage to word line layers coupled to memory cell layers in the selected first memory cell array sub-block/second memory cell array sub-block, and applying a second voltage to dummy word line layers corresponding to the first memory cell array sub-block/second memory cell array sub-block; applying a third voltage to both the word line layers coupled to the memory cell layers in the unselected second memory cell array sub-block/first memory cell array sub-block and the K-layer word line layers of the sub-block configuration region; applying a fourth voltage to the substrate;

wherein the difference between the first voltage and the fourth voltage is greater than a threshold voltage; the difference between the second voltage and the fourth voltage is smaller than the threshold voltage; the difference between the third voltage and the fourth voltage is less than the threshold voltage.

In the above scheme, the first voltage is ground, the third voltage is realized by floating, and the fourth voltage is an erase voltage of the memory cell.

In the above scheme, the memory further comprises a substrate;

the performing a write operation to a memory cell in the selected memory cell array sub-block includes:

applying a fifth voltage to word line layers coupled to memory cell layers in the selected first memory cell array sub-block/second memory cell array sub-block, applying a sixth voltage to corresponding memory cell layers in the unselected first memory cell array sub-block/second memory cell array sub-block, to dummy word line layers corresponding to the first memory cell array sub-block/second memory cell array sub-block, and to K-layer word line layers of the sub-block configuration region, and applying a seventh voltage to the substrate;

wherein the difference between the fifth voltage and the seventh voltage is greater than a threshold voltage; the difference between the sixth voltage and the seventh voltage is smaller than the threshold voltage; the fifth voltage is greater than the sixth voltage.

In the above scheme, the fifth voltage is a programming voltage of the memory cell, the sixth voltage is a passing voltage of the memory cell, and the seventh voltage is a ground voltage.

In the above scheme, the memory further comprises a substrate;

the performing a read operation on memory cells in the selected memory cell array sub-block includes:

Applying an eighth voltage to the word line layers coupled to the memory cell layers in the selected first memory cell array sub-block/second memory cell array sub-block, applying a ninth voltage to the corresponding memory cell layers in the unselected first memory cell array sub-block/second memory cell array sub-block, the dummy word line layers corresponding to the first memory cell array sub-block/second memory cell array sub-block, and the K-layer word line layers of the sub-block configuration region, and applying a tenth voltage to the substrate; wherein an eleventh voltage is applied to bit lines connected to memory cells in the selected memory cell array sub-block;

wherein the difference between the eighth voltage and the tenth voltage is greater than a threshold voltage; the difference between the ninth voltage and the tenth voltage is less than the threshold voltage; the eighth voltage is greater than the ninth voltage.

In the above scheme, the eighth voltage is a read voltage of the memory cell, the ninth voltage is a pass voltage of the memory cell, the tenth voltage is a ground voltage, and the eleventh voltage is a sensing voltage.

In the above scheme, the method further comprises:

detecting bad block conditions of the first storage unit array sub-block and the second storage unit array sub-block in the storage unit array sub-block respectively by using a bad block detection control circuit of the first storage unit array sub-block and the second storage unit array sub-block which are correspondingly selected;

And judging bad block detection conditions of the first storage unit array sub-block and the second storage unit array sub-block according to the result identification output by the bad block detection control circuit.

In the embodiment of the invention, the single memory cell array block is arranged into a plurality of sub memory cell array blocks, so that the operation of the sub memory cell array blocks can be utilized to meet the requirement of the memory cell array block with small capacity; meanwhile, in the embodiment of the invention, the word line layer is used as a control switch to divide a single memory cell array block into a plurality of memory cell array sub-blocks with the same memory cell layer number, so that the memory controller can be ensured to treat the same when facing each sub-memory cell array block, and firmware update caused by different memory cell numbers contained in each memory cell array sub-block is avoided.

Drawings

FIG. 1 is a schematic diagram illustrating a relationship between a detection circuit and a memory cell array of a memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram showing a memory cell array block structure of a memory according to the related art;

FIG. 3 is a schematic diagram of a memory cell array block structure of a memory according to an embodiment of the present invention;

FIG. 4 is a schematic flow chart of an operation method of a memory according to an embodiment of the present invention;

FIG. 5 is a schematic diagram showing a relationship between a driver and a memory cell array block of a memory according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of voltage levels for performing an erase operation in a memory according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a voltage diagram of a memory performing a write operation according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a memory performing a read operation according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a relationship between a control circuit, a driver and a memory cell array block of a memory according to an embodiment of the present invention.

Detailed Description

In order to make the technical scheme and advantages of the embodiments of the present invention more clear, the following describes the specific technical scheme of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.

The memory in the embodiment of the present invention includes, but is not limited to, a three-dimensional NAND-type memory, and for ease of understanding, the three-dimensional NAND-type memory is exemplified.

In practical applications, the three-dimensional NAND memory may include a memory cell array and peripheral circuitry; wherein the memory cell array includes at least one memory cell array block. The memory cell array block may include a Top Select Transistor (TSG), a bottom Select transistor (BSG, bottom Select Gate), a multi-layered word line layer, and a multi-layered memory cell layer coupled to the multi-layered word line layer.

The peripheral circuitry may include any suitable digital, analog, and/or mixed signal circuitry for facilitating various operations of the memory implementation, read operations, write operations, erase operations, and the like. For example, the peripheral circuits may include control logic, data buffers, decoders (which may also be referred to as decoders), drivers and read and write circuits and so forth. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages generated from the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read-write of the data and perform data interaction with the outside through the data buffer.

An embodiment of the present invention provides a memory, including:

a word line driver coupled with the memory cell array block; and

Here, the memory may include one or more memory cell array blocks; each memory cell array block may include a plurality of memory cell array sub-blocks. The number of memory cell layers coupled to the word line layers is the same as the number of word line layers included in the plurality of memory cell array sub-blocks. Here, one memory cell layer (one layer of memory cells) can also be understood as a page of memory cells. Here, the sub-block configuration region includes two word line layers for use as selection control layers of adjacent two memory cell array sub-blocks. That is, one word line layer in the sub-block arrangement region is used as a bottom selection transistor of one memory cell array sub-block positioned above in two adjacent memory cell array sub-blocks; and simultaneously, the other word line layer in the sub-block configuration area is used as a top selection transistor of one memory cell array sub-block positioned below the adjacent two memory cell array sub-blocks.

In practical applications, the sub-block configuration area may include more than two word line layers. At this time, the number of word line layers for the bottom selection transistor as one of the adjacent two memory cell array sub-blocks located above may be greater than one; and/or the number of word line layers for the top selection transistor as one memory cell array sub-block located below in the adjacent two memory cell array sub-blocks may be greater than one.

The memory cell layer connected to the word line layer in the sub-block layout area is not used to store data.

It will be appreciated that the more the number of word line layers included in the sub-block arrangement region, the more the physical separation between adjacent two memory cell array sub-blocks is, the lower the probability of interference between adjacent two memory cell array sub-blocks. However, the more memory cell layers are connected to the word line layers in the sub-block arrangement area, the more memory cell layers are not used for storing data.

In some embodiments, the number of word line layers included in the sub-block configuration area includes an odd number or an even number.

In practical applications, when the number of layers of the word line layers included in the sub-block configuration area is even, the word line layers included in the sub-block configuration area may be equally distributed to two adjacent memory cell array sub-blocks. When the number of word line layers included in the sub-block configuration area is odd, the number of word line layers used as a bottom selection transistor of one memory cell array sub-block positioned above in two adjacent memory cell array sub-blocks is odd, and simultaneously, the number of word line layers used as a top selection transistor of one memory cell array sub-block positioned below in two adjacent memory cell array sub-blocks is even; alternatively, the number of word line layers for the bottom selection transistor as the upper one of the adjacent two memory cell array sub-blocks is an even number, and the number of word line layers for the top selection transistor as the lower one of the adjacent two memory cell array sub-blocks is an odd number.

The sub-block configuration area includes two word line layers, and when the memory cell array block includes two memory cell array sub-blocks, namely a first memory cell array sub-block and a second memory cell array sub-block, the first word line layer included in the two word line layers may be used as a selection control layer of the first memory cell array sub-block; the second word line layer included in the two word line layers may serve as a selection control layer for the second memory cell array sub-block.

The sub-block configuration area includes three word line layers, and when the memory cell array block includes two memory cell array sub-blocks, namely, a first memory cell array sub-block and a second memory cell array sub-block, one word line layer included in the three word line layers may be used as a selection control layer of the first memory cell array sub-block; the remaining two word line layers included in the three word line layers may serve as selection control layers for the second memory cell array sub-block.

It is understood that the number of word line layers included in the sub-block configuration region may be determined according to the number of total word line layers included in the memory cell array block.

In practical applications, the number of sub-block configuration areas is related to the number of sub-blocks of the memory cell array. When the memory cell array block includes two memory cell array sub-blocks, one sub-block configuration area is required, and when the memory cell array block includes N memory cell array sub-blocks, N-1 sub-block configuration areas are required.

As mentioned above, with the development of the memory technology, the number of memory cell layers (english may be expressed as Layer) included in the memory is increasing, from 24 layers to 48, 96, 128, 192 and higher. The memory including 48 or more memory cell layers is formed by stacking a plurality of sub-stack structures (Deck) in the memory cell array block, and the Channel Holes (CH) corresponding to the sub-stack structures are not formed at one time.

In some embodiments, the number of layers of the memory cell layer included in the sub-stack structure at the bottom position is greater than the number of layers of the memory cell layer included in the sub-stack structure at the upper position because the sub-stack structure at the bottom position is more stable than the sub-stack structure at the higher position. That is, there is an asymmetric structure between the sub-stacks. Also, to accommodate manufacturing requirements, a dummy word line layer may be present in addition to the conventional word line layer in the sub-stack structure. Since the memory cell layers coupled with the multi-layered dummy word line layer are not used to store data, in some embodiments, a single memory cell array block may be divided into a plurality of memory cell array sub-blocks using the dummy word line layer as a control switch for a memory having a plurality of sub-stack structures.

Specifically, a single memory cell array block shown in fig. 1 is described. In fig. 1, a single memory cell array block includes: a 1-layer bottom select transistor, a 4-layer bottom dummy word line layer, for example, on the bottom select transistor, a 111-layer word line layer, for example, on the bottom dummy word line layer, a 4-layer middle dummy word line layer, for example, on the 111-layer word line layer, a 81-layer word line layer, for example, on the middle dummy word line layer, a 3-layer top dummy word line layer, for example, on the 81-layer word line layer, and a top select transistor on the top dummy word line layer.

Here, for the memory of the asymmetric sub-stack structure shown in fig. 2, a dummy word line layer may be employed as a division region between memory cell array sub-blocks, and at this time, word line layers included in two divided memory cell array sub-blocks are 81 layers and 111 layers. That is, the asymmetric sub-stack structure brings about the direct result that the capacities of the two (or more) memory cell array sub-blocks are different.

It will be appreciated that for the current Firmware (FW, english may be expressed as Firmware), the number of memory Cell layers (e.g. the number of pages) that the Firmware can distinguish from is a fixed number, and the Firmware needs to be updated for different numbers of memory Cell layers, whether the memory cells in one memory Cell array sub-block are Single-Level memory cells (SLC), double-Level memory cells (MLC), triple-Level memory cells (TLC), or Quad-Level memory cells (QLC).

To simplify the operation of the firmware, it is necessary to ensure that the number of memory cell layers included in a memory cell array sub-block is the same. One way to easily achieve the uniformity of the number of memory cell layers included in a memory cell array sub-block is to discard a portion of the capacity of a larger capacity memory cell array sub-block, i.e., taking the minimum capacity as a reference, taking the single memory cell array block shown in fig. 1 as an example, 30 word line layers out of 111 word line layers can be discarded to keep uniformity with the number of 81 word line layers. The defects caused by the method mainly comprise two points, namely, the reject capacity is too large, and the final data writing quantity (TBW) of the memory is greatly damaged; secondly, the discarded word line layer also participates in the erase operation, and dummy data needs to be written into the memory cell layer coupled to the discarded word line layer to ensure the performance of the memory.

For the above-mentioned asymmetric sub-stack structure with the dummy word line layer, the scheme of the embodiment of the invention can be adopted to realize that the number of memory cell layers contained in the divided different memory cell array sub-blocks is the same.

In some embodiments, the memory cell array block is formed by a three-dimensional stacked structure including a first sub-stacked structure and a second sub-stacked structure stacked adjacently;

Illustratively, the first sub-stack structure may include the 111 memory cell layers and the corresponding 111 word line layers in the foregoing embodiments, i.e., m=111; the second sub-stack structure may include 81 memory cell layers and a corresponding 81 word line layer in the foregoing embodiment, i.e., n=81. As shown in fig. 2, the sub-block configuration area may include 4 memory cell layers and a corresponding 4 word line layer, i.e., k=4.

Here, M and N are different values, and k+n < M.

In some embodiments, the first memory cell array sub-block is entirely included in the first sub-stack structure.

In practical applications, the first sub-stack structure may include a plurality of memory cell array sub-blocks, and it is understood that the first sub-stack structure may be integrally included in the first memory cell array sub-block or may be integrally included in the second memory cell array sub-block; here, the first sub-stack structure includes a first memory cell array sub-block, i.e., the first sub-stack structure has M memory cell layers and corresponding M word line layers.

Thus, in some embodiments, N memory cell layers and corresponding N word line layers of the second sub-stack structure are defined in the second memory cell array sub-block, and F memory cell layers and corresponding F word line layers of the first sub-stack structure are defined in the second memory cell array sub-block by the sub-block configuration region, F being an integer greater than or equal to 1, wherein (f+n) is equal to the number of memory cell layers for storing data of the second memory cell array sub-block and (M-F-K) is equal to the number of memory cell layers for storing data of the first memory cell array sub-block.

In practical application, the second sub-stack structure has N memory cell layers and corresponding N word line layers, and compared with the first sub-stack structure, the second sub-stack structure has M memory cell layers and corresponding M word line layers, which are fewer than the first sub-stack structure. The K memory cell layers and the corresponding K word line layers in the first sub-stack are arranged as sub-block arrangement areas, so that the number of M-N-K memory cell layers and the corresponding word line layers in the first sub-stack is greater than the number of memory cell layers and the corresponding word line layers in the second sub-stack. In order to make the first memory cell array sub-block and the second memory cell array sub-block have the same number of memory cell layers and corresponding word line layers, the M-N-K layer memory cell layers and the corresponding M-N-K layer word line layers are equally divided into two parts, i.e., M-N-k=2f, and one part (i.e., the F layer memory cell layers and the corresponding F layer word line layers) is arranged in the second sub-stack structure, forming the second memory cell array sub-block having the n+f layer memory cell layers and the corresponding n+f layer word line layers. Another portion (i.e., an F-layer memory cell layer and a corresponding F-layer word line layer) is arranged in the first sub-stack structure forming a first memory cell array sub-block having an M-F-K layer memory cell layer and a corresponding M-F-K layer word line layer; wherein f=1/2 (M-N-K).

In this way, the number of memory cell layers and corresponding word line layers included in the first memory cell array sub-block is made the same as the number of memory cell layers and corresponding word line layers included in the second memory cell array sub-block.

Illustratively, as shown in fig. 2, the first sub-stack structure has 111 memory cell layers and corresponding 111 word line layers, and the second sub-stack structure has 81 memory cell layers and corresponding 81 word line layers, wherein 4 memory cell layers and corresponding 4 word line layers in the first sub-stack structure are configured as sub-block configuration regions. Thus, the memory cell layers and corresponding word line layers in the first sub-stack except for the sub-block layout area are different from the memory cell layers and corresponding word line layers in the second sub-stack by 26 memory cell layers and corresponding 26 word line layers, i.e., 111-81-4=26.

The 26 memory cell layers and the corresponding 26 word line layers, which differ from each other in the first sub-stack structure and the second sub-stack structure, are equally divided into two equalization regions, i.e., 2×13.

Next, a second memory cell array sub-block having (81+13=94) memory cell layers and corresponding 94 word line layers is formed by configuring 13 memory cell layers and corresponding 13 word line layers in a first of the two equalizing regions in a second sub-stack structure through control selection of the sub-block configuration region. Meanwhile, 13 memory cell layers and corresponding 13 word line layers included in a second of the two equalizing regions are arranged in a second sub-stack structure, forming a first memory cell array sub-block having (111-13-4=94) memory cell layers and corresponding 94 word line layers.

Thus, the number of memory cell layers for storing data of the first memory cell array sub-block is equal to the number of memory cell layers for storing data of the second memory cell array sub-block. Therefore, the memory controller can be guaranteed to treat the same when facing each memory cell array sub-block, and firmware update caused by different numbers of memory cells contained in each memory cell array sub-block is avoided.

In some embodiments, the number of memory cell layers for storing data of the first memory cell array sub-block and the second memory cell array sub-block is C, where C is an integer greater than or equal to 2;

wherein C2+K = m+n.

Illustratively, as shown in fig. 2, the number of memory cell layers C for storing data of the first memory cell array sub-block and the second memory cell array sub-block is 94, and the sub-block configuration area includes 4 memory cell layers; in this way, the total number of memory cell layers included in the first memory cell array sub-block and the second memory cell array sub-block and the sub-block configuration area is equal to the sum of the first sub-stack structure including 111 memory cell layers and the second sub-stack structure including 81 memory cell layers, that is, 94×2+4=111+81.

In some embodiments, the word line driver includes:

In practical application, the memory further comprises a word line driver and a control circuit, wherein the word line driver is coupled with the memory cell array block; and a control circuit may be used to control the word line drivers.

Here, the first memory cell array sub-block, the second memory cell array sub-block, and the sub-block configuration area are respectively provided with corresponding drivers, i.e., a first sub-driver, a second sub-driver, and a third sub-driver. The first sub-driver is used for driving a word line layer of the first memory cell array sub-block; the second sub-driver is used for driving a word line layer of a second memory cell array sub-block; the third sub-driver is used for driving the word line layer of the sub-block configuration area.

In some embodiments, the control circuit is configured to control the third sub-driver and a first selection transistor corresponding to the first memory cell array sub-block to implement selection control of the first memory cell array sub-block; the control circuit is further configured to control the third sub-driver and a second selection transistor corresponding to the second memory cell array sub-block to realize selection control of the second memory cell array sub-block.

Here, the first selection transistor may be understood as the aforementioned top selection transistor, and the second selection transistor may be understood as the aforementioned bottom selection transistor.

In some embodiments, the K-layer word line layer includes a first word line layer and a second word line layer, and the K-layer memory cell layer includes a first memory cell layer and a second memory cell layer corresponding to the first word line layer and the second word line layer, respectively;

Here, K is an odd number or an even number. Here, the memory controller may equally distribute the K-layer word line layers included in the sub-block configuration area to two adjacent memory cell array sub-blocks, where the K-layer word line layers are used together with the corresponding memory cell layers and the selection transistors to control and select the corresponding memory cell array sub-blocks, and the distribution manner is described above and will not be repeated herein.

In some embodiments, the K-layer memory cell layer is not used to store data.

In some embodiments, the first and second sub-stacks further have a dummy memory cell layer and a corresponding dummy word line layer.

Here, the bottom dummy word line layer and/or the middle dummy word line layer in fig. 2 may be exemplarily classified into a first sub-stack structure, the top dummy word line layer and/or the middle dummy word line layer may be classified into a second sub-stack structure, but the middle dummy word line layer may be classified into only one sub-stack structure.

The dummy memory cell layer and the corresponding dummy word line layer included in the dummy word line layer are not counted in the memory cell layer and the corresponding word line layer included in the sub-stack structure, that is, the dummy memory cell layer and the corresponding dummy word line layer are not counted in the M-layer memory cell layer and the corresponding M-layer word line layer of the first sub-stack structure, and are not counted in the N-layer memory cell layer and the corresponding N-layer word line layer of the second sub-stack structure.

In some embodiments, the memory cell array block includes a plurality of word line layers, and a plurality of dummy word line layers asymmetrically interspersed among the plurality of word line layers; the multi-layer word line layer comprises a first type word line layer and a second type word line layer; a memory cell layer coupled to the first type word line layer for forming the first memory cell array sub-block and the second memory cell array sub-block; the second type word line layer is used for forming the sub-block configuration area.

Here, the word line layers are divided into two main types, a first type word line layer and a second type word line layer; the memory cell layer connected with the first type word line layer is used for forming the plurality of memory cell array subblocks, namely the memory cell layer connected with the first type word line layer is used for storing data; the second word line layer is used to form the sub-block configuration area, that is, the second word line layer is used as a control switch to distinguish the plurality of memory cell array sub-blocks, the memory cell layer connected with the second word line layer is not used to store data, and the second word line layer may be obtained by defining a corresponding word line layer in a certain sub-stack structure, for example, the corresponding word line layer in the certain sub-stack structure is configured as the second word line layer in a memory controller of the corresponding memory system.

It should be noted that the plurality of dummy word line layers are symmetrically interposed between the plurality of word line layers, and it is understood that, limited by the process, the plurality of dummy word line layers need to be formed between the plurality of word line layers during the process of forming the plurality of word line layers; the positions and the layers of the formed multi-layer dummy word line layers are set according to the process requirements of the memory, have certain randomness and are not dependent on the layers of the multi-layer word line layers formed in the memory.

The description will be made with respect to a single memory cell array block shown in fig. 2.

In the embodiment of the present invention, as shown in fig. 2, 192 (00-191) word line layers included in the single memory cell array block are divided into two types; the 00 th to 93 th (94 th) and 97 th to 191 th (94 th) layers are first type word line layers, and the 94 th to 97 th (4 th) layers are second type word line layers. Forming a first memory cell array sub-block with memory cell layers coupled to the 00 th through 93 th layers, the first memory cell array sub-block comprising 94 memory cell layers; the memory cell layers coupled with layers 98 through 191 form a second memory cell array sub-block that also includes 94 memory cell layers. The 94 th to 97 th word line layers are used as control layers, and specifically, the 94 th to 95 th word line layers can be used as bottom selection transistors of the second memory cell array sub-block, and the 96 th to 97 th word line layers can be used as top selection transistors of the first memory cell array sub-block.

In some embodiments, the memory further comprises:

a first bad block detection circuit provided corresponding to the first memory cell array sub-block and configured to detect a bad block condition of the first memory cell array sub-block;

Here, the bad block detection control circuit is configured to detect a bad block condition of the memory cell array block, such as a factory bad block condition. The first bad block detection control circuit and the second bad block detection control circuit are in one-to-one correspondence with the first storage unit array sub-block and the second storage unit array sub-block, so that each bad block detection control circuit is used for detecting bad block conditions of a corresponding storage unit array sub-block.

The memory cell array block including two memory cell array sub-blocks is described as an example. As shown in fig. 3, the memory cell array block includes a first memory cell array sub-block and a second memory cell array sub-block, and a first bad block detection control circuit of the two bad block detection control circuits is used for detecting a bad block condition of the first memory cell array sub-block; the second bad block detection control circuit of the two bad block detection control circuits is used for detecting bad block conditions of the second memory cell array sub-blocks. When the bad block detection is performed, the two memory cell array sub-blocks in the memory cell array block can be detected respectively, so that the two memory cell array sub-blocks can be detected at the same time, that is, the bad block condition of the two memory cell array sub-blocks can be detected at the same time.

It should be noted that the first memory cell array sub-block may be located above the second memory cell array sub-block or may be located below the second memory cell array sub-block; here, the description will be given taking an example in which the first memory cell array sub-block is located above the second memory cell array sub-block.

In some embodiments, the first bad block detection circuit and/or the second bad block detection circuit are configured to output the result identification in the form of multi-bit binary data.

Here, the final result identifiers output by the first bad block detection circuit and/or the second bad block detection circuit may be expressed by using multi-bit binary data.

In practical applications, a one-bit binary system typically utilizes two states, 0 and 1, to measure data; two-bit binary typically scales data with four states, 00, 01, 10, 11; three bit binary typically scales data with eight states of 000, 001, 010, 011, 100, 101, 110, 111. By analogy, N-bit binary typically employs 2 ^N The state measures the data.

The memory cell array block including two memory cell array sub-blocks is described as an example. When the detection result is performed on two memory cell array sub-blocks using one-bit binary data expression, the detection result is shown in table 1. Wherein the 11 state in the two-bit binary is set to pass and the 00, 01, 10 states are set to fail.

TABLE 1

Thus, bad block conditions in the multiple memory cell sub-blocks can be screened out according to the test results of table 1.

The embodiment of the invention also provides a memory system, which comprises:

one or more memories as described in the above embodiments; and

a memory controller coupled to the memory.

In practical applications, the memory controller may be configured to control the memory to perform erasing, reading or writing operations, and decode, parse or operate on instructions sent or received in the memory.

In some embodiments, the memory controller is configured to designate corresponding memory cell layers and word line layers from the memory cell array block as the K-layer memory cell layers and K-layer word line layers, respectively, to define the sub-block configuration region.

In practical applications, the memory controller may be configured to control and select the memory cell layer and the word line layer corresponding to the sub-block configuration area, that is, the memory controller may be configured to control and select the memory cell layer and the word line layer corresponding to the first memory cell array sub-block and the second memory cell array sub-block, respectively.

In this way, the number of memory cell layers for storing data of the first memory cell array sub-block is made equal to the number of memory cell layers for storing data of the second memory cell array sub-block by selectively controlling the memory cell layers and the word line layers corresponding to the sub-block arrangement region.

The embodiment of the invention provides a method for operating a memory. Fig. 4 is a schematic flow chart of an implementation of an operation method of the memory according to an embodiment of the present invention. As shown in fig. 4, the method comprises the steps of:

step 401, receiving a first instruction, wherein the first instruction characterizes that the memory cell array block is erased, read or written by adopting a sub-block mode;

Step 402, selecting the first memory cell array sub-block and/or the second memory cell array sub-block in the memory cell array block by driving and controlling the sub-block configuration area;

step 403, performing an erasing, reading or writing operation on the memory cell layer in the selected first memory cell array sub-block and/or the second memory cell array sub-block.

Here, the memory may include at least one memory cell array block, and the memory cell array sub-block may include a first memory cell array sub-block and/or a second memory cell array sub-block and a sub-block configuration region; the first memory cell array sub-block and/or the second memory cell array sub-block may each include a plurality of memory cell layers; the sub-block configuration region may include a plurality of word line layers.

Here, in step 401, the first instruction characterizes selecting a first memory cell array sub-block and/or a second memory cell array sub-block in one memory cell array block of the memory as a target block, and performs a corresponding operation on the target block.

In practical application, the memory further includes a control logic unit, where the control logic unit is configured to receive an instruction to control the memory to perform erasing, reading or writing operations, so that a memory cell layer included in a corresponding memory cell array block in the memory performs a corresponding operation according to the received control instruction.

In practical application, after receiving the control instruction, the control logic unit determines to perform erasing, reading or writing operation on a memory cell array block in different modes according to the instruction content of the instruction.

In some embodiments, in step 402, the selected first memory cell array sub-block and/or second memory cell array sub-block is used as a target block. Here, the relationship between the selected first memory cell array sub-block and/or the second memory cell array sub-block and the memory cell array and the sub-block configuration area is the same as that described in the previous embodiment, and the description thereof is omitted.

In some embodiments, the selection is achieved by controlling a word line layer of a sub-block configuration area disposed between two adjacent memory cell array sub-blocks, which may specifically achieve the area configuration of the first memory cell array sub-block and the second memory cell array sub-block by the word line layer of the sub-block configuration area as a control switch.

In practical applications, the word line driver may be used to generate a corresponding voltage, and the generated voltage is applied to the corresponding word line layer to realize the selection of the first memory cell array sub-block and the second memory cell array sub-block.

Next, in step 403, an erase, read, or write operation is performed on the respective memory cell layers included in the selected first memory cell array sub-block and/or second memory cell array sub-block.

In practice, erase operations are typically performed in sub-block units, and read and write operations are typically performed in page units.

In some embodiments, the method further comprises:

selecting a memory cell array block;

an erase, read, or write operation is performed on memory cells in the selected memory cell array block.

Here, the second instruction characterizes one memory cell array block of the memory as a target block, and performs a corresponding operation on the target block.

For ease of understanding, the foregoing description will be given taking as an example that one memory cell array block includes two memory cell array sub-blocks.

Fig. 5 shows a schematic diagram of a control circuit of a memory. As shown in fig. 5, the memory cell array block includes a first memory cell array sub-block and a second memory cell array sub-block; after receiving the second instruction, it is determined to target the entire memory cell array block (i.e., the first memory cell array sub-block and the second memory cell array sub-block together). After receiving the first instruction, determining to take the first storage unit array sub-block or the second storage unit array sub-block as a target block. After the target block is determined, a corresponding operation is performed on the target block.

In some embodiments, the memory cell array block includes a plurality of word line layers, and a plurality of dummy word line layers asymmetrically interspersed among the plurality of word line layers; the multi-layer word line layer comprises a first type word line layer and a second type word line layer; a memory cell layer coupled to the first type word line layer for forming the plurality of memory cell array sub-blocks; the second type word line layer is used for forming the sub-block configuration area.

Here, the memory cell array block includes a plurality of word line layers coupled to the plurality of memory cell layers, and a plurality of dummy word line layers interposed in the plurality of word line layers; here, the word line layers are divided into two main types, a first type word line layer and a second type word line layer; the memory cell layer connected with the first type word line layer is used for forming the plurality of memory cell array subblocks, namely the memory cell layer connected with the first type word line layer is used for storing data; the second type word line layer is used for forming the sub-block configuration area, namely, the second type word line layer is used for being used as a control switch to distinguish the plurality of memory cell array sub-blocks, and the memory cell layer connected with the first type word line layer can not be used for storing data. Here, the plurality of dummy word line layers may be formed as needed in the process.

It should be noted that, the plurality of dummy word line layers are asymmetrically interposed between the plurality of memory cell array sub-blocks, which is limited by the process; in the process of forming the multi-layer word line layers, a plurality of dummy word line layers are required to be formed between the multi-layer word line layers, and the positions and the layers of the formed multi-layer dummy word line layers are set according to the process requirements, so that the multi-layer word line layers have certain randomness and are not dependent on the layers of the formed multi-layer word line layers. It is understood that the number of layers of the plurality of dummy word line layers between adjacent two memory cell array sub-blocks may be different.

In some embodiments, the memory further comprises a substrate; the performing an erase operation on the selected corresponding memory cells in the first memory cell array sub-block and/or the second memory cell array sub-block includes:

applying a first voltage to a first type word line layer included in the selected first memory cell array sub-block and/or second memory cell array sub-block; applying a second voltage to the dummy word line layers corresponding to the first memory cell array sub-block/the second memory cell array sub-block; applying a third voltage (e.g., in a floating state) to both the word line layers to which the memory cell layers in the unselected second memory cell array sub-block/first memory cell array sub-block are coupled and the K-layer word line layers of the sub-block configuration region; applying a fourth voltage to the substrate;

In some embodiments, the first voltage is ground, the third voltage is implemented by floating, and the fourth voltage is an erase voltage of the memory cell.

Here, the threshold voltage of the memory may include a tunneling voltage that is turned on during the memory performing an erase operation.

For ease of understanding, the foregoing description will be given taking as an example that one memory cell array block includes two memory cell array sub-blocks. As shown in fig. 6, the memory cell array block may include a first memory cell array sub-block, a second memory cell array sub-block; the first memory cell array sub-block is selected for erasing.

In practical application, a first voltage is applied to a first type word line layer contained in a selected first memory cell array sub-block and/or a second memory cell array sub-block, where the first voltage may be a ground voltage, and a voltage value of the first voltage may be specifically 0V; applying a second voltage to the multi-layer dummy word line layer corresponding to the first memory cell array sub-block/second memory cell array sub-block, the second voltage being a high voltage (V _{High Vol.} ) The second voltage is greater than the first voltage; applying a third voltage to the unselected multi-layered word line layer, which may be a relatively high voltage, or may be set in a floating state to the unselected multi-layered word line layer; applying a fourth voltage to the substrate, the fourth voltage being an erase voltage (V _ERA )。

Under the action of the first voltage, the second voltage, the third voltage and the fourth voltage, the voltage difference applied to the substrate and the first type word line layer in the selected memory cell array subblock is larger than the tunneling voltage, and then the multi-layer memory cell layer coupled to the first type word line layer in the selected memory cell array subblock performs an erasing operation. Here, a voltage difference between the second voltage applied to the dummy word line layer and the substrate is smaller than the tunneling voltage, and thus the erase operation is not performed.

In the embodiment of the invention, the write operation and the read operation can be performed on the memory cell layer in the selected memory cell array subblock. The foregoing description will be given taking as an example that one memory cell array block includes two memory cell array sub-blocks.

As shown in fig. 7, the memory cell array block may include a first memory cell array sub-block and a second memory cell array sub-block, and the write operation is exemplified by selecting a memory cell layer in the first memory cell array sub-block.

In some embodiments, the memory further comprises a substrate;

In some embodiments, the fifth voltage is a programming voltage of the memory cell, the sixth voltage is a pass voltage of the memory cell, and the seventh voltage is a ground voltage.

Here, the threshold voltage of the memory may include a voltage programmed during the memory performing a write operation.

Here, for the first type selected in the selected first memory cell array sub-block/second memory cell array sub-blockThe word line layer applies a fifth voltage, which may be a programming voltage (V _PGM ) The method comprises the steps of carrying out a first treatment on the surface of the Applying a sixth voltage to all the first type word line layers corresponding to the first memory cell array sub-block/second memory cell array sub-block, the unselected first type word line layers, the unselected second type word line layers, and the unselected first type word line layers included in the sub-block configuration region, wherein the sixth voltage may be a pass voltage (V _PASS ) The method comprises the steps of carrying out a first treatment on the surface of the A seventh voltage, which may be a ground voltage, may be applied to the substrate, and the voltage value may be 0V. Under the action of the fifth voltage, the sixth voltage and the seventh voltage, the writing operation can be performed on the memory cell layer coupled with the first type word line layer selected in the selected memory cell array subblock.

As shown in fig. 8, the memory cell array block may include a first memory cell array sub-block and a second memory cell array sub-block, and the reading operation is exemplified by selecting a memory cell layer in the first memory cell array sub-block.

In some embodiments, the memory further comprises a substrate;

In some embodiments, the eighth voltage is a read voltage of the memory cell, the ninth voltage is a pass voltage of the memory cell, the tenth voltage is a ground voltage, and the eleventh voltage is a sense voltage.

Here, the threshold voltage of the memory may include a voltage that is read during a read operation performed by the memory.

Here, an eighth voltage is applied to the first-type word line layer selected in the selected first memory cell array sub-block/second memory cell array sub-block, the eighth voltage being a read voltage (V _READ ) The method comprises the steps of carrying out a first treatment on the surface of the Applying a ninth voltage to the dummy word line layer corresponding to the first memory cell array sub-block/second memory cell array sub-block, the unselected first type word line layer, the unselected second type word line layer, and all the first type word line layers included in the unselected sub-block configuration region in the first memory cell array sub-block/second memory cell array sub-block, the ninth voltage being a pass voltage (V _PASS ) The method comprises the steps of carrying out a first treatment on the surface of the A tenth voltage, which may be a ground voltage, may be applied to the substrate, and the voltage value may be 0V.

Applying an eleventh voltage, which is a sense voltage (V _DD ) The method comprises the steps of carrying out a first treatment on the surface of the Under the action of the eighth voltage, the ninth voltage, the tenth voltage and the eleventh voltage, the reading operation can be performed on the memory cell layer coupled with the first type word line layer selected in the selected memory cell array sub-block.

In some embodiments, the method further comprises:

The foregoing description will be given taking as an example that one memory cell array block includes two memory cell array sub-blocks.

As shown in fig. 9, when the memory cell array block includes a first memory cell array sub-block and a second memory cell array sub-block, the selected sub-block configuration region includes a first equalization region and a second equalization region; the first equalization region may be for bottom select transistors that are sub-blocks of the first memory cell array; the second equalization region may be used as a top select transistor of a second memory cell array sub-block. In this way, the top select transistor, the first memory cell array sub-block, and the first equalization region form a complete first sub-memory that can be used alone to perform erase, read, or write operations. Likewise, the second equalization region, the second memory cell array sub-block, and the bottom select transistor form a complete second sub-memory that is used alone to perform erase, read, or write operations. In this way, the bad block detection control circuits of the first memory cell array sub-block and the second memory cell array sub-block are in one-to-one correspondence with the first memory cell array sub-block and the second memory cell array sub-block, so that one bad block detection control circuit is used for detecting bad block conditions of the corresponding one memory cell array sub-block. And when the bad block detection is performed, detecting the first storage unit array sub-block and the second storage unit array sub-block in the storage unit array block respectively, so that the bad block condition of the two storage unit array sub-blocks can be detected simultaneously, and the bad block detection efficiency in the memory is improved.

It should be noted that: "first," "second," etc. are used to distinguish similar objects and not necessarily to describe a particular order or sequence.

In addition, the embodiments of the present invention may be arbitrarily combined without any collision.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A memory, comprising:

a word line driver coupled with the memory cell array block; and

a control circuit for controlling at least the word line driver;

wherein the memory cell array block includes:

a first memory cell array sub-block and a second memory cell array sub-block disposed adjacent to each other; and

2. The memory according to claim 1, wherein the memory cell array block is formed by a three-dimensional stacked structure including a first sub-stacked structure and a second sub-stacked structure adjacently stacked;

3. The memory of claim 2, wherein the first memory cell array sub-block is entirely included in the first sub-stack structure.

4. The memory of claim 3, wherein N memory cell layers and corresponding N word line layers of the second sub-stack structure are defined in the second memory cell array sub-block, and wherein F is an integer greater than or equal to 1, with the sub-block configuration region, with the F memory cell layers and corresponding F word line layers of the first sub-stack structure being defined in the second memory cell array sub-block, wherein (f+n) is equal to the number of memory cell layers of the second memory cell array sub-block for storing data, and (M-F-K) is equal to the number of memory cell layers of the first memory cell array sub-block for storing data.

5. The memory according to claim 2, wherein the number of memory cell layers for storing data of the first memory cell array sub-block and the second memory cell array sub-block are each C, C being an integer greater than or equal to 2;

wherein C2+K = m+n.

6. The memory of claim 1, wherein the word line driver comprises:

7. The memory of claim 6, wherein the control circuit is configured to control the third sub-driver and a first selection transistor corresponding to the first memory cell array sub-block to implement selection control of the first memory cell array sub-block; the control circuit is further configured to control the third sub-driver and a second selection transistor corresponding to the second memory cell array sub-block to realize selection control of the second memory cell array sub-block.

8. The memory of claim 7, wherein the K-layer word line layers include a first word line layer and a second word line layer, and the K-layer memory cell layers include a first memory cell layer and a second memory cell layer corresponding to the first word line layer and the second word line layer, respectively;

9. The memory of claim 1, wherein the K-layer memory cell layer is not used to store data.

10. The memory of claim 2, wherein the first and second sub-stacks further have a dummy memory cell layer and a corresponding dummy word line layer.

11. The memory of claim 1, wherein the memory cell array block includes a plurality of word line layers, and a plurality of dummy word line layers asymmetrically interspersed among the plurality of word line layers; the multi-layer word line layer comprises a first type word line layer and a second type word line layer; a memory cell layer coupled to the first type word line layer for forming the first memory cell array sub-block and the second memory cell array sub-block; the second type word line layer is used for forming the sub-block configuration area.

12. The memory of claim 1 wherein K is an odd or even number.

13. The memory of claim 1, wherein the memory further comprises:

14. The memory of claim 13, wherein the first bad block detection circuit and/or the second bad block detection circuit is configured to output the result identification in the form of multi-bit binary data.

15. The memory of claim 1, wherein the memory comprises a three-dimensional NAND-type memory.

16. A memory system, comprising:

one or more memories as claimed in any of claims 1 to 15; and

a memory controller coupled to the memory.

17. The memory system of claim 16, wherein the memory controller is configured to designate corresponding memory cell layers and word line layers from the memory cell array block as the K-layer memory cell layers and K-layer word line layers, respectively, to define the sub-block configuration region.

18. A method of operating a memory as claimed in any one of claims 1 to 15, comprising:

and performing erasing, reading or writing operation on the memory cell layer of the selected first memory cell array subblock and/or the second memory cell array subblock.

19. The method of claim 18, wherein the method further comprises:

selecting a memory cell array block;

20. The method of claim 18, wherein the memory further comprises a substrate;

Applying a first voltage to the word line layers coupled to the memory cell layers in the selected first memory cell array sub-block/second memory cell array sub-block, applying a second voltage to the dummy word line layers corresponding to the first memory cell array sub-block/second memory cell array sub-block, and applying a third voltage to the word line layers coupled to the memory cell layers in the unselected second memory cell array sub-block/first memory cell array sub-block and the K-layer word line layers of the sub-block configuration region; applying a fourth voltage to the substrate;

21. The method of claim 20, wherein the first voltage is ground, the third voltage is implemented by floating, and the fourth voltage is an erase voltage of a memory cell.

22. The method of claim 18, wherein the memory further comprises a substrate;

23. The method of claim 22, wherein the step of determining the position of the probe is performed,

the fifth voltage is a programming voltage of the memory cell, the sixth voltage is a passing voltage of the memory cell, and the seventh voltage is a ground voltage.

24. The method of claim 18, wherein the memory further comprises a substrate;

25. The method of claim 24, wherein the eighth voltage is a read voltage of the memory cell, the ninth voltage is a pass voltage of the memory cell, the tenth voltage is a ground voltage, and the eleventh voltage is a sense voltage.

26. The method of claim 18, wherein the method further comprises: