JP2004110881A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of correctly reading data in a core cell with a large margin. <P>SOLUTION: The semiconductor memory is provided with the core cell 11, at least one internal reference cell 12, 13 arranged within the area of core cell, at least one external reference cell 50 arranged outside the core cell, and a reference voltage generation circuit 40 for generating the reference voltage Vref by using at least one of the internal reference cells and at least one external reference cell jointly at the same time. The reference voltage generation circuit is provided with switch circuits 41, 42 for controlling the connections between the internal reference cells and the external reference cells and a control circuit 43 for controlling the switch circuits, and is configured so as to read the data stored in the core cell by using the output of the reference voltage generation circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that reads data of a core cell using a reference cell.
[0002]
Conventionally, there has been proposed a method in which a reference cell having the same data deterioration characteristic as that of a core cell is provided in a core cell region, and data of the core cell is read using the reference cell. However, when a reference cell is provided in the core cell region, the threshold value of the reference cell also has a distribution due to variations in the manufacturing process of the semiconductor memory device and the physical position of the cell in the core cell region. Therefore, it becomes difficult to correctly read the data of the core cell. Therefore, there is a demand for a semiconductor memory device capable of correctly reading data of a core cell with a large margin.
[0003]
[Prior art]
In general, data in a core cell deteriorates as rewriting is performed, and therefore, a countermeasure is required. Conventionally, for example, there has been proposed a method in which a reference cell having the same data deterioration characteristic as that of a core cell is provided in a core cell area, and data of the core cell is read using the reference cell.
[0004]
Conventionally, a reference cell is provided for each column block of a memory cell, each column block is compared with a reference cell close to the column block, and data is determined for each column block to disperse noise generation and generate large noise. There has been proposed a nonvolatile semiconductor memory device in which the access time is shortened while suppressing the delay (for example, see Patent Document 1).
[0005]
FIG. 1 is a block diagram schematically showing an example of a conventional semiconductor memory device. A nonvolatile semiconductor memory device having two reference cells in a core cell region (for example, having a charge trap layer in a gate insulating film) Flash memory, however, the nonvolatile semiconductor memory device is not limited to this, and is applicable to, for example, a nonvolatile semiconductor memory device using a floating gate such as a polysilicon electrode as a charge storage region.) This is an example. In FIG. 1, reference numeral 100 denotes a core cell region, 101 denotes a core cell, 102 denotes a first reference cell, 103 denotes a second reference cell, 201 to 203 denote cascode circuits, and 300 denotes a sense amplifier.
[0006]
When reading data stored in the core cell 101 (arbitrary memory cell in the core cell 101) in the semiconductor memory device illustrated in FIG. 1, first, the first and second reference cells ( Data “0” and “1” are written to two dynamic reference cells) 102 and 103, respectively.
[0007]
The output (current) of the first reference cell 102 for “0” data and the output of the second reference cell 103 for “1” data are short-circuited (coupled), and further subjected to current-voltage conversion by cascode circuits 202 and 203, respectively. After that, the reference voltage (intermediate potential) Vref is generated.
[0008]
The reference voltage Vref is applied to the sense amplifier 300, and a signal (data voltage: data read from an arbitrary memory cell in the core cell 101) obtained by current-voltage conversion of the data output (current) from the core cell 101 by the cascode circuit 201 (A potential determined by the threshold value of the memory cell from which the data is read), it is determined whether the read data output from the core cell 101 is “0” or “1”.
[0009]
As a result, even after repeatedly rewriting data, the deterioration characteristics of the reference cells 102 and 103 can be made to follow the deterioration characteristics of the core cell 101, and data can be correctly read.
[0010]
It is proposed that two dynamic reference cells (first and second reference cells 102 and 103) are provided in the core cell area 100 and the two dynamic reference cells are used together when reading data stored in the core cell 101. (For example, see Patent Document 2).
[0011]
[Patent Document 1]
JP-A-4-11392 [Patent Document 2]
Japanese Patent Application No. 2001-53994
[Problems to be solved by the invention]
As described above, conventionally, there has been proposed a configuration in which reference cells 102 and 103 having the same data deterioration characteristics as the core cell 101 are provided in the core cell region 100 and the data of the core cell is read using the reference cells.
[0013]
By the way, the data of the memory cells (the core cell 101 and the reference cells 102 and 103) in the core cell region 100 vary, and even if the same data is stored, the threshold has a distribution.
[0014]
That is, the distribution is provided for the data “0” and the data “1” of the core cell 101, respectively, and the same applies to the reference cells 102 and 103 provided in the core cell region 100.
[0015]
For example, a reference voltage (Vref) generated from a reference cell having a high threshold value when data is “0” and “1”, and a reference voltage generated from a reference cell having a low threshold value when data is “0” and “1”. The potential becomes different from the voltage, and the reference voltage has a distribution similarly to the core cell 101.
[0016]
Therefore, in reading data from the memory cell (core cell 101), the reference voltage (intermediate potential) closest to the data “0” (or data “1”) and the data “0” (or the data “ If the difference from the potential determined by the threshold value of “1”) is a margin in reading data “0” (or data “1”), the reference voltage generated from the reference cell has a distribution. There is a problem that the size becomes smaller for both “0” and data “1”.
[0017]
The present invention has been made in view of the above-described problems of the conventional semiconductor memory device, and has as its object to provide a semiconductor memory device capable of correctly reading data of a core cell with a large margin.
[0018]
[Means for Solving the Problems]
According to the present invention, a core cell, at least one internal reference cell provided in a region of the core cell, at least one external reference cell provided outside a region of the core cell, and at least one of the internal reference cells And a reference voltage generation circuit for generating a reference voltage by using at least one of the external reference cells, wherein the reference voltage generation circuit controls a connection between the internal reference cells and the external reference cells. And a control circuit for controlling the switch circuit, wherein the data stored in the core cell is read using the output of the reference voltage generation circuit.
[0019]
As described above, since there is a distribution in the reference cells provided in the core cell region, a margin in reading becomes small. In order to cope with this, in the semiconductor memory device of the present invention, an intermediate reference potential for reading data of a core cell is generated by using a reference cell provided outside a core cell region with no distribution (or with a small distribution). . As a result, the distribution of the intermediate reference potential can be reduced, and as a result, a margin in reading can be increased.
[0020]
That is, according to the semiconductor memory device of the present invention, the distribution of the reference voltage can be reduced by using the reference cell outside the core cell region together with the reference cell inside the core cell region, but this generates the reference voltage. This is because the threshold distribution of the virtual reference cell can be reduced. Therefore, if the threshold distribution of the virtual reference cell that generates the reference voltage is reduced, the read margin is improved.
[0021]
FIG. 2 is a diagram showing a threshold distribution of a virtual reference cell for generating a reference voltage in the conventional and the semiconductor memory devices of the present invention, and FIG. 2A shows the generation of a reference voltage in the above-described conventional semiconductor memory device. FIG. 2B shows a threshold distribution of a virtual reference cell, and FIG. 2B shows a threshold distribution of a virtual reference cell that generates a reference voltage in the semiconductor memory devices according to first and second embodiments of the present invention to be described later. FIG. 2 (c) shows a threshold distribution of a virtual reference cell for generating a reference voltage in a semiconductor memory device according to a third embodiment of the present invention described later.
[0022]
With reference to FIGS. 2A to 2C, a description will be given of how the threshold distribution of a virtual reference cell that generates a reference voltage decreases. Here, in the reference cells in the core cell region, the threshold distributions of data “1” and data “0” are ΔVE and ΔVP, respectively, and the threshold distribution of the reference cells outside the core cell region is ΔVext.
[0023]
First, as shown in FIG. 2A, in the conventional dynamic reference method (that is, a method using two reference cells in a core cell region), a threshold distribution ΔVdref of a virtual reference cell is
ΔVdref = (ΔVE + ΔVP) / 2
It becomes.
[0024]
On the other hand, as shown in FIG. 2B, the threshold value of the virtual reference cell in the three-cell system (first and second embodiments of the present invention: when a reference cell outside the core cell region is added) The distribution ΔV1 / 3 is
ΔV1 / 3 = (ΔVE + ΔVP + ΔVext) / 3
It becomes. Here, to simplify the description, if ΔVE = ΔVP = ΔV and ΔVext = 0, then ΔVdref and ΔV1 / 3 are
ΔVdref = ΔV
ΔV1 / 3 = 2ΔV / 3
It becomes. Therefore, it can be understood that the threshold distribution of the virtual reference cells is reduced by introducing reference cells outside the core cell region.
[0025]
On the other hand, as shown in FIG. 2C, the two-cell system (the third embodiment of the present invention: a case where one reference cell in the core cell region and one reference cell outside the core cell region are used as a set) is used. The threshold distribution ΔV1 / 2 of the virtual reference cell is
ΔV1 / 2 = (ΔV + ΔVext) / 2 = ΔV / 2
It becomes. Therefore, it can be seen that the threshold distribution of the virtual reference cell is further reduced.
[0026]
As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of correctly reading data of a core cell with a large margin.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.
[0028]
FIG. 3 is a block diagram schematically showing a first embodiment of the semiconductor memory device according to the present invention, in which two reference cells are provided in a core cell region and one reference cell is provided outside the core cell region. Nonvolatile semiconductor memory device (for example, a flash memory having a charge trap layer in a gate insulating film: a memory cell uses a trap level of an ONO film (oxide film / nitride film / oxide film) or the like as a charge storage region). This is an example of a type of flash memory used. However, the semiconductor memory device to which the present invention is applied is not limited to a flash memory having a charge trapping layer in a gate insulating film. For example, a nonvolatile memory using a floating gate such as a polysilicon electrode as a charge storage region is used. The present invention may be applied to a semiconductor memory device, and further to a semiconductor memory device for reading data of a core cell using a reference cell.
[0029]
3, reference numeral 1 denotes a core cell region, 11 denotes a core cell, 12 denotes a first internal reference cell, 13 denotes a second internal reference cell, 21 to 24 denotes a cascode circuit, 30 denotes a sense amplifier, and 40 denotes a reference voltage generator. Reference numerals 41 and 42 denote selection circuits, 43 denotes a control circuit, and 50 denotes an external reference cell. Here, the control circuit 43 controls on / off of the switches SWAX, SWAB, SWBX in the selection circuit 41 and the switches SWAR, SWBR, SWXR in the selection circuit 42, for example, by an external address signal.
[0030]
In the semiconductor memory device of the first embodiment shown in FIG. 3, when reading data stored in the core cell 1 (arbitrary memory cell in the core cell 1), the switches SWAX, SWAX, SWAB and SWBX are turned on, and switches SWAR, SWBR and SWXR in the selection circuit 42 are turned on.
[0031]
That is, by turning on the switches SWAX, SWAB, and SWBX in the selection circuit 41, three reference cells (the first internal reference cell 12 and the second internal reference cell 13 provided inside the core cell region 1, and the core cell The output (current) of the external reference cell 50 provided outside the region 1 is short-circuited, and the short-circuited outputs of the three reference cells are turned on by turning on the switches SWAR, SWBR, and SWXR in the selection circuit 42. After the current-voltage conversion in the cascode circuits 22 to 24, the cascode circuits are short-circuited, and a reference voltage (intermediate potential) Vref is generated.
[0032]
The reference voltage Vref is applied to the sense amplifier 30, and a signal obtained by current-voltage conversion of the data output (current) from the core cell 11 by the cascode circuit 21 (data voltage: data read from any memory cell in the core cell 11) Is read out from the core cell 11 to determine whether the read data output from the core cell 11 is “0” or “1”.
[0033]
As a result, even after repeatedly rewriting data, the deterioration characteristics of the reference cells 102 and 103 can be made to follow the deterioration characteristics of the core cell 101, and data can be correctly read.
[0034]
As described above, according to the semiconductor memory device of the first embodiment, the three reference cells of the first internal reference cell 12, the second internal reference cell 13, and the external reference cell 50 are used together, and these three reference cells are used. The reference voltage (intermediate potential) Vref is generated by averaging the cell thresholds equivalently. That is, since the distribution of the reference voltage Vref is suppressed to be small by averaging the threshold values of the reference cells, the read margin can be increased, and the data of the core cells can be correctly read.
[0035]
FIG. 4 is a block diagram schematically showing a second embodiment of the semiconductor memory device according to the present invention.
[0036]
As is clear from the comparison between FIG. 4 and FIG. 3, the semiconductor memory device according to the second embodiment eliminates the selection circuits 41 and 42 and the control circuit 43 in the semiconductor memory device according to the first embodiment. Equivalent to something.
[0037]
That is, in the second embodiment, the first internal reference cell 12 and the second internal reference cell 13 provided inside the core cell region 1 and the external reference cell 50 provided outside the core cell region 1 are provided. Are short-circuited, and further subjected to current-voltage conversion by the cascode circuits 22 to 24, and then short-circuited to generate the reference voltage Vref.
[0038]
The semiconductor memory device of the second embodiment also has three reference cells, a first internal reference cell 12, a second internal reference cell 13, and an external reference cell 50, similarly to the semiconductor memory device of the first embodiment. Is used, and the threshold values of these three reference cells are equivalently averaged to generate the reference voltage Vref, so that the distribution of the reference voltage Vref can be suppressed small and the read margin can be increased. That is, it is possible to correctly read the data of the core cell with a large margin.
[0039]
In the above, the number of the internal reference cells provided inside the core cell region 1 is not limited to two (two for each sense amplifier 30; the first and second internal reference cells 12 and 13, respectively). Further, the number of external reference cells provided outside the core cell region 1 is not limited to one. That is, as described later with reference to FIG. 5, one internal reference cell may be provided inside the core cell region 1, or three or more internal reference cells may be provided.
[0040]
FIG. 5 is a block diagram schematically showing a third embodiment of the semiconductor memory device according to the present invention.
[0041]
As is clear from the comparison between FIG. 5 and FIG. 3, the semiconductor memory device of the third embodiment has two internal reference cells (the first and second internal reference cells) in the semiconductor memory device of the first embodiment. (Cells 12, 13) as one internal reference cell 14.
[0042]
In the semiconductor memory device of the third embodiment shown in FIG. 5, when data stored in the core cell 1 (arbitrary memory cell in the core cell 1) is read, the switch SWX in the selection circuit 41 is switched by the output of the control circuit 43. At the same time, the switches SWR and SWXR in the selection circuit 42 are turned on.
[0043]
That is, when the switch SWX in the selection circuit 41 is turned on, the output (current) of the two reference cells (the internal reference cell 14 provided inside the core cell region 1 and the external reference cell 50 provided outside the core cell region 1) ) Is short-circuited, and by turning on the switches SWR and SWXR in the selection circuit 42, the short-circuited outputs of the two reference cells are short-circuited after current-voltage conversion in the cascode circuits 25 and 24, and the reference voltage ( An intermediate potential Vref is generated.
[0044]
The semiconductor memory device of the third embodiment has the same structure as the semiconductor memory device of the first embodiment shown in FIG. 3 having two internal reference cells (first and second internal reference cells 12, 13). The same configuration is obtained by adjusting the control of the switches of the selection circuits 41 and 42 by the circuit 43. That is, in the semiconductor memory device of the first embodiment shown in FIG. 3, when reading data stored in the core cell 1, the switch SWAX in the selection circuit 41 is turned on by the output of the control circuit 43 by an external address signal, and the selection is performed. By turning on the switches SWAR and SWXR in the circuit 42, the semiconductor memory device of the third embodiment shown in FIG. 5 can be configured with the first internal reference cell 12 used.
[0045]
Further, the semiconductor memory device of the third embodiment has, for example, the semiconductor memory device of the first embodiment shown in FIG. 3 having two internal reference cells (first and second internal reference cells 12, 13). By adjusting the control of each switch of the selection circuits 41 and 42 by the control circuit 43, a similar configuration can be realized in a state where the second internal reference cell 13 is used. That is, in the semiconductor memory device of the first embodiment shown in FIG. 3, when data stored in the core cell 1 is read, the switch SWBX in the selection circuit 41 is turned on by the output of the control circuit 43 by an external address signal, and the control is performed. By turning on the switches SWBR and SWXR in the circuit 42, the semiconductor memory device of the third embodiment shown in FIG. 5 can be configured.
[0046]
Note that an external address can be input to the control circuit 43 and the control method can be changed according to the external address. In other words, the output of the control circuit 43 is controlled by an external address, and the switches of the selection circuits 41 and 42 are turned on / off, whereby, for example, the first internal reference cell 12 in the semiconductor memory device of the first embodiment shown in FIG. Or the use of the second internal reference cell 13 can be changed.
[0047]
The semiconductor memory device of the third embodiment also uses the two reference cells, the internal reference cell 14 and the external reference cell 50, and averages the threshold values of these two reference cells equivalently to generate the reference voltage Vref. Thereby, the distribution of the reference voltage Vref can be suppressed to be small, the read margin can be increased, and the data of the core cell can be correctly read.
[0048]
FIG. 6 is a block diagram schematically showing a fourth embodiment of the semiconductor memory device according to the present invention. Similar to the second embodiment shown in FIG. 4, the semiconductor memory device of the third embodiment shown in FIG. This corresponds to the device in which the selection circuits 41 and 42 and the control circuit 43 are removed.
[0049]
That is, in the fourth embodiment, the output (current) of the internal reference cell 14 provided inside the core cell region 1 and the output (current) of the external reference cell 50 provided outside the core cell region 1 are short-circuited. Circuits 25 and 24 are short-circuited after current-voltage conversion to generate reference voltage Vref.
[0050]
The semiconductor memory device of the fourth embodiment also uses two reference cells, the internal reference cell 14 and the external reference cell 50, similarly to the semiconductor memory device of the third embodiment described above, and sets the threshold value of these two reference cells. Are equivalently averaged to generate the reference voltage Vref, so that the distribution of the reference voltage Vref can be suppressed to be small and the read margin can be increased, so that the data of the core cell can be correctly read.
[0051]
As described above, according to the embodiments of the semiconductor memory device according to the present invention, in reading data from the core cell, in addition to the internal reference cell in the core cell region, the external reference cell outside the core cell region is used in combination with the reference cell. The distribution of the voltage can be reduced, and the read margin can be increased to improve the data read accuracy.
[0052]
In the above, the semiconductor memory device to which the present invention is applied is not limited to a flash memory having a charge trapping layer in a gate insulating film or a nonvolatile semiconductor memory device, and the present invention uses a reference cell. The present invention can be widely applied to various semiconductor memory devices that read core cell data.
[0053]
(Supplementary Note 1) Core cell,
At least one internal reference cell provided in the region of the core cell, and at least one external reference cell provided outside the region of the core cell;
A reference voltage generation circuit that generates a reference voltage by using at least one of the internal reference cells and at least one of the external reference cells, and wherein the output of the reference voltage generation circuit is used to store the reference voltage in the core cell. A semiconductor memory device for reading data.
[0054]
(Supplementary Note 2) In the semiconductor memory device according to Supplementary Note 1,
The semiconductor memory device, wherein the reference voltage generation circuit generates a reference voltage by using two internal reference cells and one external reference cell together.
[0055]
(Supplementary Note 3) In the semiconductor memory device according to Supplementary Note 1,
The semiconductor memory device, wherein the reference voltage generation circuit generates a reference voltage by using one internal reference cell and one external reference cell together.
[0056]
(Supplementary Note 4) In the semiconductor memory device according to Supplementary Note 2 or 3,
The semiconductor memory device according to claim 1, wherein the internal reference cell is selected by an external address signal.
[0057]
(Supplementary Note 5) In the semiconductor memory device according to any one of Supplementary Notes 1 to 4,
The semiconductor memory device, wherein the reference voltage generation circuit includes a switch circuit that controls connection between the internal reference cell and the external reference cell, and a control circuit that controls the switch circuit.
[0058]
(Supplementary Note 6) The semiconductor memory device according to any one of Supplementary Notes 1 to 5, further comprising:
A semiconductor memory device, comprising: a sense amplifier that compares an output from the core cell with an output from the reference voltage generation circuit and reads data stored in the core cell.
[0059]
(Supplementary Note 7) A reading method of a semiconductor memory device provided with a reference cell in a core cell region,
At least one new reference cell is provided outside the core cell region, and a reference voltage is generated by using at least one of the reference cells in the core cell region and at least one of the reference cells outside the core cell region in combination. A method for reading a semiconductor memory device, comprising reading data stored in the core cell using a voltage.
[0060]
(Supplementary Note 8) In the reading method of the semiconductor memory device according to Supplementary Note 7, the generation of the reference voltage is performed using both two reference cells in the core cell region and one reference cell outside the core cell region. A method for reading a semiconductor memory device, comprising:
[0061]
(Supplementary Note 9) In the reading method of the semiconductor memory device according to Supplementary Note 7, the generation of the reference voltage may be performed by using one reference cell in the core cell region selected by an external address and one reference cell outside the core cell region. And a reading method for a semiconductor memory device.
[0062]
(Supplementary note 10) In the reading method of the semiconductor memory device according to Supplementary note 8 or 9,
The method according to claim 1, wherein the internal reference cell is selected by an external address signal.
[0063]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a semiconductor memory device capable of correctly reading data of a core cell with a large margin.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing an example of a conventional semiconductor memory device.
FIG. 2 is a diagram showing a threshold distribution of a virtual reference cell for generating a reference voltage in the conventional and the semiconductor memory devices of the present invention;
FIG. 3 is a block diagram schematically showing a first embodiment of the semiconductor memory device according to the present invention.
FIG. 4 is a block diagram schematically showing a second embodiment of the semiconductor memory device according to the present invention.
FIG. 5 is a block diagram schematically showing a third embodiment of the semiconductor memory device according to the present invention.
FIG. 6 is a block diagram schematically showing a fourth embodiment of the semiconductor memory device according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Core cell area 11 ... Core cell 12 ... First internal reference cell 13 ... Second internal reference cell 14 ... Internal reference cells 21-25 ... Cascode circuit 30 ... Sense amplifier 40 ... Reference voltage generation times 41 and 42 ... Selection circuit 43: control circuit 50: external reference cell

Claims (5)

A core cell,
At least one internal reference cell provided in the area of the core cell;
At least one external reference cell provided outside a region of the core cell;
A reference voltage generation circuit that generates a reference voltage by using at least one of the internal reference cells and at least one of the external reference cells, wherein the reference voltage generation circuit includes the internal reference cell and the external reference cell A semiconductor memory device, comprising: a switch circuit for controlling connection of the core cell; and a control circuit for controlling the switch circuit, wherein data stored in the core cell is read using an output of the reference voltage generation circuit. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the reference voltage generation circuit generates a reference voltage by using two internal reference cells and one external reference cell together. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the reference voltage generation circuit generates a reference voltage by using one internal reference cell and one external reference cell together. 4. The semiconductor memory device according to claim 2, wherein
The semiconductor memory device according to claim 1, wherein the internal reference cell is selected by an external address signal. The semiconductor memory device according to claim 1, further comprising:
A semiconductor memory device, comprising: a sense amplifier that compares an output from the core cell with an output from the reference voltage generation circuit and reads data stored in the core cell.

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