JP2004110574A - Reference voltage generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit for shortening the return time from a power-down mode to an ordinary operation mode. <P>SOLUTION: This reference voltage generating circuit is provided with a first switching means for switching the potential of a reference voltage generating terminal by charging and discharging of a capacitative element in response to a first control signal from the outside and a second switching means for switching the potential of the reference voltage generating terminal by conducting or non-conducting of a PMO transistor in response to a second control signal from the outside. The PMOS transistor of the second switching means is put in the conducting state, whereby the potential of the reference voltage generating terminal is set to the potential corresponding to the ordinary operation mode, and the potential of the reference voltage generating terminal is set to the potential corresponding to the low-consumption power mode by putting the transistor in the non-conducting state. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a reference voltage generation circuit used for a digital / analog converter, an operational amplifier, and the like of a semiconductor integrated circuit, and particularly to switching between a low power consumption mode (power down mode) and a normal operation mode of the digital / analog converter. About.
[0002]
[Prior art]
In general, a reference voltage generation circuit used in a conventional D / A converter or the like is a circuit that always supplies a constant reference voltage, and therefore a low power consumption mode (power down mode) of the D / A converter or the like. No special action is taken when canceling.
[0003]
Hereinafter, a conventional reference voltage generation circuit will be described with reference to FIG. FIG. 6 is a circuit diagram showing a configuration of a conventional reference voltage generation circuit.
As shown in FIG. 6, in the conventional reference voltage generation circuit, the source electrodes are connected to the power supply voltage AVDD, and the source electrodes are connected to the power supply voltage AVDD, similarly to the cascode-connected PMOS transistors 511 and 512. Cascode-connected PMOS transistors 514 and 515, a PMOS transistor 517 for powering down the reference voltage generation circuit, and a normal operation mode and a power down mode connected to the gate electrode of the PMOS transistor 570. A power-down control terminal NPOWD, which is an input terminal for a digital value to be controlled, a capacitor C51 for stabilizing a gate voltage connected to the capacitor C51, and current source elements 513 and 516 each having one end grounded. And is composed of The gate electrodes of the PMOS transistors 511 and 512 are connected to the gate electrodes of the PMOS transistors 514 and 515 to form a current mirror. Further, the gate electrodes of the PMOS transistor 511 and the PMOS transistor 512 are connected to each other. The drain electrode is connected. The drain electrode of the PMOS transistor 512 is connected to a current source element 513 having one end grounded, and the drain electrode of the PMOS transistor 515 is similarly connected to a current source element 516 having one end grounded. Further, a capacitor C51 is connected between the gate electrodes of the PMOS transistors 511 and 514 and the power supply voltage AVDD. One end of the PMOS transistor 517 is connected to the power supply voltage AVDD, and the other end is connected to the power supply voltage AVDD. One end is connected between the gate electrodes of the PMOS transistor 511 and the PMOS transistor 514. The PMOS transistor 517 is turned off when the digital value input from the power-down control terminal NPOWD is “H”, and is turned on when the digital value is “L”.
[0004]
With this configuration, the reference voltage VB51, that is, the gate voltages of the PMOS transistors 511 and 514, and the reference voltage VB52, that is, the gate voltages of the PMOS transistors 512 and 515 are determined.
[0005]
Hereinafter, the operation of releasing the power down mode in the conventional reference voltage generating circuit will be described.
[0006]
In the power-down mode, when a digital value “L” is input to the power-down control signal terminal NPOWD, the PMOS transistor 517 becomes conductive and current flows, so that the gates of the PMOS transistor 511 and the PMOS transistor 514 The reference voltage VB51, which is a voltage, rises, the gate-source voltage of each of the PMOS transistors 511, 514 decreases, and the PMOS transistors 511, 514 are turned off. As a result, the reference voltage generation circuit stops generating the reference voltage, and all the current stops.
[0007]
Then, when the digital value input to the power down control terminal NPOWD is changed from “L” value to “H” value in order to release the power down mode of the reference voltage generation circuit, the PMOS transistor 517 is turned off. Since the current cannot flow, the reference voltage VB51, that is, the gate voltages of the PMOSs 511 and 514, discharges the charge stored in the capacitor C51 and attempts to return to the normal voltage. Then, after discharging the charge stored in the capacitor C51, the reference voltage V51 becomes a normal voltage, and the reference voltage generation circuit returns to the normal operation mode.
[0008]
Further, a third transistor for controlling a reference current transistor and a constant current transistor is provided as a conventional current addition type digital / analog conversion circuit, and an output current flowing through the reference current transistor and the constant current transistor is provided. In some cases, power consumption is reduced during standby by selectively blocking (see Patent Document 1). Further, as a conventional reference voltage generating circuit, a voltage lower circuit composed of a reference voltage generating section, an operational amplifier for performing impedance conversion of a reference voltage generated by the reference voltage generating section and outputting the converted voltage, and an output from the voltage lower circuit. A smoothing capacitor for smoothing a reference voltage to be applied, and by switching the size of the output transistor of the operational amplifier to a small size at the time of standby, by passing a small current to the smoothing capacitor and holding the charge of the capacitor, There is one that shortens the time required to return from the standby state (see Patent Document 2).
[0009]
[Patent Document 1]
JP-A-5-206860
[Patent Document 2]
JP-A-11-232406
[0010]
[Problems to be solved by the invention]
However, in the configuration of the conventional reference voltage generation circuit described above, for example, the reference voltage generation circuit shown in FIG. 6, in order for the reference voltages VB51 and VB52 in the power down mode to return to the reference voltage values in the normal operation mode, At least in the power down mode, the electric charge stored in the capacitor C51 needs to be completely discharged, and the return time from when the reference voltage generation circuit releases the power down mode to when the reference voltage generating circuit returns to the normal operation mode is: This depends on the capacitance value of the capacitance element C51. The capacitance element used in such a reference voltage generation circuit generally has a considerably large capacitance value in order to stabilize the reference voltage VB against noise and the like.
[0011]
That is, in the configuration of the conventional reference voltage generating circuit, it takes time to completely discharge the electric charge stored in the capacitor C51, and the return time from the power-down mode to the normal operation mode becomes longer. As a result, the conventional reference voltage generating circuit has a problem that it is unsuitable for a system such as data communication that needs to repeat the power down mode and the normal operation mode frequently and in a short time.
[0012]
The present invention has been made in view of the above problems, and has as its object to provide a reference voltage generation circuit that can reduce the time required to return from the power down mode to the normal operation mode.
[0013]
[Means for Solving the Problems]
In order to solve the above problem, a reference voltage generating circuit according to claim 1 of the present invention has a reference voltage generating terminal for generating a reference voltage, and the potential of the reference voltage generating terminal is controlled by an external control signal. A reference voltage generation circuit including a plurality of switching means for switching, wherein one of the plurality of switching means has a capacitor connected between a predetermined voltage and a first node, A first switching unit that switches the potential of the reference voltage generation terminal by charging and discharging the capacitance element according to the first control signal, wherein another one of the plurality of switching units includes the predetermined voltage; A second switching unit includes a switching element connected between the switching node and a second node, and switches the potential of the reference voltage generation terminal by turning on and off the switching element according to a second control signal.
[0014]
The reference voltage generating circuit according to a second aspect of the present invention is the reference voltage generating circuit according to the first aspect, wherein the first switching means is connected to the capacitive element, A current path for setting a terminal to a potential corresponding to the terminal voltage of the capacitor, and charging and discharging the capacitor by the first control signal to set the potential of the reference voltage generation terminal to a normal operation mode Switching to the first potential or a second potential corresponding to the low power consumption mode. In the case of the normal operation mode, the second switching means is configured to switch the switch element by the second control signal. Is turned off, the potential of the reference voltage generation terminal is fixed to the first potential set from the current path of the first switching means. In the case of the low power consumption mode, the second potential is set to the second potential. The switching means is as described above. The second control signal, by turning on the switch element, the potential of the reference voltage generating terminal is for securing to the second potential.
[0015]
According to a third aspect of the present invention, in the reference voltage generating circuit according to the second aspect, the second switching means includes a transistor and a resistor.
[0016]
Further, the reference voltage generating circuit according to claim 4 of the present invention has a reference voltage generating terminal for generating a reference voltage, and a plurality of switching means for switching the potential of the reference voltage generating terminal by an external control signal. Wherein one of the plurality of switching means has a capacitive element connected between a power supply and a first node, and a capacitance based on a first control signal. A first switching unit that switches a potential of the reference voltage generation terminal by charging / discharging an element; another one of the plurality of switching units is connected between a power supply and the first node; A first switch element, a second switch element connected between the reference voltage generating terminal, and one end of the capacitor element on the first node side, and a second control ON / OFF of the first and second switch elements by a signal By a second switching means for switching the potential of the reference voltage generating terminal.
[0017]
The reference voltage generating circuit according to a fifth aspect of the present invention is the reference voltage generating circuit according to the fourth aspect, wherein the first switching means is connected to the capacitive element, A current path for setting a terminal to a potential corresponding to the terminal voltage of the capacitor, and charging and discharging the capacitor by the first control signal to set the potential of the reference voltage generation terminal to a normal operation mode Switching to the first potential or the second potential corresponding to the low power consumption mode. In the case of the normal operation mode, the second switching means operates in response to the second control signal in response to the first control signal. By turning off the switch element and turning on the second switch element, the potential of the reference voltage generating terminal is fixed at the first potential set by the current path of the first switching means. And low consumption above In the case of the power mode, the second switching means turns on the first switch element and turns off the second switch element in accordance with the second control signal, whereby the reference voltage generation terminal Is fixed to the second potential.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
In the first embodiment, a capacitor is charged by setting the potential of a reference voltage generation terminal for generating a reference voltage to a first potential corresponding to the normal operation mode and a second potential corresponding to the power down mode. In addition to the first switching means for switching by discharging, a switching element, which is a PMOS transistor whose opening and closing are controlled by an external control signal, is independent of the charging and discharging of the capacitance element in the first switching means. And a second switching means capable of switching the potential of the reference voltage generating terminal.
[0019]
First, the configuration of the reference voltage generation circuit according to the first embodiment will be described with reference to FIG.
[0020]
The reference voltage control device 10 according to the first embodiment shown in FIG. 1 includes PMOS transistors 111, 112, 114, 115, 116, 118 to 122 and current source elements 113 and 117 each having one end grounded. , 123, a capacitive element C11, and first and second power-down control terminals NPOWD11 and NPOWD12. The source electrodes of the cascode-connected PMOS transistors 111 and 112 are connected to the power supply voltage AVDD, and the drain electrode of the PMOS transistor 112 is connected to one end of the current source element 113. Further, the gate electrodes of the PMOS transistors 111 and 112 are respectively connected to the gate electrodes of the cascode-connected PMOS transistors 118 and 119 to form a current mirror. The gate electrode and the drain electrode of the PMOS transistor 119 are connected, and these electrodes are connected to one end of the current source element 123.
[0021]
The PMOS transistor 114 is connected between the gate electrodes of the PMOS transistor 111 and the PMOS transistor 118 and the power supply voltage AVDD, and forms a current mirror with the PMOS transistor 116.
The PMOS transistor 116 has its gate electrode and drain electrode connected, its drain electrode connected to the current source element 117, and its source electrode connected to the power supply voltage AVDD.
[0022]
The source electrode of the PMOS transistor 115 is connected to the drain electrode of the PMOS transistor 114, the gate electrode is connected to the drain electrode of the PMOS transistor 112, and the drain electrode is grounded.
[0023]
In the first embodiment, two power-down control terminals are provided. First, the first power-down control terminal NPOWD11 is connected to the gate electrode of the PMOS transistor 120, and the drain electrode of the PMOS transistor 120 is Is connected between the gate electrodes of the PMOS transistor 116 and the PMOS transistor 114, and the source electrode thereof is connected to the power supply voltage AVDD. The capacitor C11 for stabilizing the connected gate-to-gate voltage is connected between the reference voltage VB11, that is, between the gate electrodes of the PMOS transistor 114 and the PMOS transistor 116, and the power supply voltage AVDD.
[0024]
On the other hand, the second power-down control terminal NPOWD12 is connected between the gate electrodes of the PMOS transistor 121 and the PMOS transistor 122, and the drain electrode of the PMOS transistor 122 is connected between the gate electrode of the PMOS transistor 115 and the drain electrode of the PMOS transistor 112. The source electrode is connected to the power supply voltage AVDD, and the drain electrode of the PMOS transistor 121 is connected to the reference voltage VB11, that is, between the gate electrodes of the PMOS transistor 111 and the PMOS transistor 118. Are connected to the power supply voltage AVDD. The PMOS transistors 120, 121, and 122 connected to the first and second power-down control terminals NPOWD11 and NPOWD12 are input from the first and second power-down control terminals NPOWD11 and NPOWD12 as in the related art. When the digital value to be output is "H", the device is turned off, and when the digital value is "L", the device is turned on.
[0025]
Hereinafter, the operation of the thus configured reference voltage generating circuit of the first embodiment in which the normal operation mode is switched to the power down mode, the power down mode is released, and the normal operation mode is set will be described.
First, in the case of the normal operation mode, a digital value “H” is input to the first and second power-down mode control terminals NPOWD11 and NPOWD12, whereby the PMOS transistors 120, 121 and 122 are turned off. , Reference voltages VB11 and VB12 supply a normal voltage (first potential).
[0026]
Then, when switching from the normal operation mode to the power down mode, in the first embodiment, only the digital value input to the second power down control terminal NPOWD12 is switched from “H” to “L”. . As a result, the PMOS transistors 121 and 122 are rendered conductive and current flows, so that the gate voltage of the PMOS transistor 111 and the gate voltage of the PMOS transistor 118 rise to near the power supply voltage ADVV (second potential), and further. Similarly, the drain voltage of the PMOS transistor 112 and the gate voltage of the PMOS transistor 115 also rise to the vicinity of the power supply voltage ADVV.
[0027]
As a result, no current flows through the path of the PMOS transistor 111, that is, the path of the PMOS transistors 111 and 112, the current source element 113, and the path of the PMOS transistor 118, that is, the PMOS transistors 118 and 119 and the current source element 123. The power consumption of the voltage generation circuit is reduced.
[0028]
Then, when the power down mode is released, the digital value input to the second power down control terminal NPOWD12 is switched from the “L” value to the “H” value. As a result, the PMOS transistors 121 and 122 are turned off again so that no current flows, and the gate voltages of the PMOS transistors 111 and 118 operate to return the potential of the reference voltage generation terminal to a normal voltage. .
[0029]
In this return operation, the PMOS transistors 111 and 118 need to discharge all the electric charges stored in the parasitic capacitance such as the gate capacitance of the transistors. However, since these gate capacitance values are small, the time required for the recovery is short.
[0030]
As described above, according to the first embodiment, in the reference voltage generating circuit, the first switching means capable of switching the potentials of the reference voltages VB11 and VB12 by discharging the capacitive element C11 is provided independently of the first switching means. A second switching means capable of switching the potential of the reference voltages VB11 and VB12 by opening and closing a switch element controlled in accordance with a digital value input to the second power-down control terminal NPOWD12; Since the switching of the reference voltage potentials VB11 and VB12 is controlled by switching only the digital value applied to the terminal NPOWD12, when the power-down mode is released, the charge stored in the capacitor C11 can be discharged without being discharged. The reference voltage potentials VB11 and VB12 can be switched, and as a result, the return time from the power down mode to the normal operation mode can be reduced. It can be obtained have a reference voltage generating circuit.
[0031]
Further, as shown in FIG. 2, resistance elements R12 and R11 are provided between the source electrode of the PMOS transistor 112 and the power supply voltage AVDD, and between the source electrode of the PMOS transistor 116 and the power supply voltage AVDD, respectively. By doing so, the current from the power supply voltage AVDD does not suddenly increase in the PMOS transistors 116 and 121, so that ringing is less likely to occur, and as a result, the rise of the circuit becomes faster and the recovery time can be further reduced. Has the effect of
[0032]
In the first embodiment, an example has been described in which two power-down control terminals NPOWD for inputting digital values for switching between the power-down mode and the normal operation mode are provided. May be any number.
[0033]
(Embodiment 2)
In the second embodiment, similarly to the first embodiment, in addition to the first switching means for switching the potential of the reference voltage generation terminal by charging / discharging of the capacitive element, a PMOS whose opening and closing are controlled by an external control signal is provided. A second switching means capable of switching the reference voltage potential is provided by a switching element, which is a transistor, independently of charging and discharging of the capacitance element in the first switching means.
[0034]
First, the configuration of the reference voltage generation circuit according to the second embodiment will be described with reference to FIG.
The reference voltage generation circuit according to the second embodiment shown in FIG. 3 includes PMOS transistors 211, 212, 214 to 217, 220, 221, 223 to 225, NMOS transistors 218, 219, 222, and one end thereof grounded. Current source elements 213, 218, 229, and 231, a capacitive element C21, and first and second power-down control terminals NPOWD21 and NPOWD22.
[0035]
Specifically, the PMOS transistor 211 is cascode-connected to the PMOS transistor 212, the source electrode thereof is connected to the power supply voltage AVDD, and the drain electrode of the PMOS transistor 212 is connected to the gate electrode of the PMOS transistor 211. It is grounded via the current source element 213. Further, the PMOS transistors 211 and 212 form a current mirror with the cascode-connected PMOS transistors 214 and 215. The drain electrode of the PMOS transistor 215 is connected to its gate electrode. It is grounded via the source element 226. The PMOS transistor 227 has one end connected to the power supply voltage AVDD and the other end connected to the gate electrodes of the PMOS transistors 211 and 214.
[0036]
The PMOS transistors 214 and 215 also form a current mirror with the cascode-connected PMOS transistors 216 and 217, and the drain electrode of the NMOS transistor 218 is connected to the drain electrode of the PMOS transistor 217. 218 constitutes a current mirror with the NMOS transistor 222, and its source electrode is grounded.
[0037]
The PMOS transistor 220 is cascode-connected to the PMOS transistor 221, the source electrode is connected to the power supply voltage AVDD, and the drain electrode of the PMOS transistor 221 is connected to the drain electrode of the NMOS transistor 222. Further, the PMOS transistors 220 and 221 form a current mirror with the PMOS transistors 224 and 225. The drain electrode of the PMOS transistor 225 is connected to its gate electrode and grounded via the current source element 231. . The current source element 229 has one end connected to the power supply voltage AVDD, the other end connected between the gate electrodes of the PMOS transistor 220 and the PMOS transistor 224, and grounded via the PMOS transistor 223 to form a source follower. . The gate electrode of the PMOS transistor 223 is connected to the drain electrode of the PMOS transistor 221.
[0038]
The capacitor C21 is connected between the gate electrodes of the PMOS transistors 211 and 214 and the power supply voltage AVDD, and stabilizes the gate voltage connected to the capacitor C21.
[0039]
In the second embodiment, two power-down control terminals are provided. First, the first power-down control terminal NPOWD21 is connected to the gate electrode of the PMOS transistor 227, and the drain electrode of the PMOS transistor 227 is , PMOS transistors 211, 214, and 216.
[0040]
The other second power-down control terminal NPOWD12 is connected to the gate electrodes of the PMOS transistors 228 and 230, and the source electrodes of the PMOS transistors 228 and 230 are connected to the power supply voltage AVDD and the drain of the PMOS transistor 228 is connected. The electrode is connected to the gate electrode of the PMOS transistor 223, and the drain electrode of the PMOS transistor 230 is connected to the gate electrodes of the PMOS transistor 220 and the PMOS transistor 224. The PMOS transistors 227, 228, and 229 connected to the first and second power-down control terminals NPOWD21 and NPOWD22 are input from the first and second power-down control terminals NPOWD11 and NPOWD12 as in the related art. When the digital value to be output is "H", the device is turned off, and when the digital value is "L", the device is turned on.
[0041]
Hereinafter, the operation of the thus configured reference voltage generating circuit of the second embodiment will be described in which the normal operation mode is switched to the power down mode, and the power down mode is released to return to the normal operation mode.
First, in the case of the normal operation mode, a digital value "H" is input to the first and second power-down mode control terminals NPOWD21 and NPOWD22, thereby turning off the PMOS transistors 228 and 229. The voltages VB21 and VB22 supply a normal voltage (first potential).
[0042]
When switching from the normal operation mode to the power down mode, in the second embodiment, only the digital value input to the second power down mode control terminal NPOWD22 is switched to "L". As a result, the PMOS transistors 228 and 229 become conductive and a current flows. Therefore, the reference voltages VB21 and VB22 are voltages at which no current flows in a circuit to which the reference voltage VB is connected, in this case, around the power supply voltage ADVV ( (The second potential).
[0043]
Then, no current flows through the path of the PMOS transistor 220, that is, the path of the PMOS transistors 220 and 221, the NMOS transistor 222, and the PMOS transistor 224, that is, the PMOS transistors 224 and 225 and the current source element 231. Power consumption is reduced.
[0044]
Then, when the power down mode is released, the digital value input to the second power down control terminal NPOWD12 is switched from the “L” value to the “H” value. As a result, the PMOS transistors 228 and 230 become non-conductive, and operate to return the reference voltages VB21 and VB22 to normal voltages.
[0045]
In this return operation, the PMOS transistors 220 and 224 need to discharge all the electric charges stored in the parasitic capacitance such as the gate capacitance. However, since these gate capacitance values are small, the time required for the recovery is short.
[0046]
As described above, according to the second embodiment, in the reference voltage generation circuit, independent of the first switching means capable of switching the potentials of the reference voltages VB21 and VB22 by discharging the capacitive element C21, A second switching means capable of switching the potentials of the reference voltages VB21 and 22 by opening and closing a switch element controlled in accordance with a digital value input to the second power-down control terminal NPOWD22; Since the reference voltage potentials VB21 and VB22 are controlled by switching only the digital value applied to the terminal NPOWD22, the charge stored in the capacitor C21 does not have to be discharged when the power-down mode is released. As a result, a reference voltage generating circuit having a short recovery time from the power down mode to the normal operation mode can be obtained.
[0047]
Further, as shown in FIG. 4, if the resistor R31 is provided instead of the current source element 229 of FIG. 3, the current does not suddenly increase from the power supply voltage AVDD, and ringing hardly occurs. As a result, there is an effect that the rise of the circuit becomes faster and the recovery time can be further reduced.
[0048]
(Embodiment 3)
In the third embodiment, similarly to the first embodiment, in addition to the first switching means for switching the potential of the reference voltage generation terminal by charging / discharging of the capacitor, a PMOS whose opening and closing are controlled by an external control signal is provided. A second switching means capable of switching the reference voltage potential is provided by a first switching element and a second switching element, which are transistors, independently of charging and discharging of the capacitance element in the first switching means. It is like that.
[0049]
First, the configuration of the reference voltage generation circuit according to the third embodiment will be described with reference to FIG.
As shown in FIG. 5, the reference voltage generating circuit according to the third embodiment includes PMOS transistors 411, 412, 414 to 418, NMOS transistors 419 and 420, and current source elements 413 and 416 whose one ends are grounded. , A capacitive element C41, switch elements 426, 427, delay elements 423, 424, 425, and first and second power-down control terminals NPOWD41, NPOWD42.
[0050]
More specifically, the PMOS transistor 411 is cascode-connected to the PMOS transistor 412, the source electrode thereof is connected to the power supply voltage AVDD, and the drain electrode of the PMOS transistor 412 is connected to the gate electrode of the PMOS transistor 411. , And a current source element 413. Further, the PMOS transistors 411 and 412 form a current mirror with the cascode-connected PMOS transistors 414 and 415, and a drain electrode of the PMOS transistor 415 is connected to its gate electrode. It is grounded via the current source element 416. The PMOS transistor 417 has one end connected to the power supply voltage AVDD and the other end connected to the gate electrodes of the PMOS transistors 411 and 414.
[0051]
Switching elements 426 and 427 are inserted between the reference voltages VB41 and VB42 and the PMOS transistors 411 and 412, and the capacitance element C41 for stabilizing the connected gate voltage is connected to the PMOS transistor 411 and 414 is connected between the gate electrode and the power supply voltage AVDD.
[0052]
In the third embodiment, two power-down control terminals are provided. First, the first power-down control terminal NPOWD41 is connected to the gate electrode of the PMOS transistor 417, and the source electrode of the PMOS transistor 417 is , The power supply voltage AVDD, and the drain electrode thereof are connected to the gate electrodes of the PMOS transistors 411 and 414.
[0053]
The other second power-down control terminal NPOWD42 is connected to the gate electrode of the NMOS transistor 420 and the delay elements 423, 424, and 425. The source electrode of the NMOS transistor 420 is grounded, the drain electrode is connected to the source electrode of another NMOS transistor 419, and the drain electrode of the PMOS transistor 419 is connected to the reference voltage VB42. Further, outputs of the delay elements 423 and 425 are used for timing control of switching of the switch elements 426 and 427, and an output of the delay element 424 is connected to a gate of the NMOS transistor 419. The PMOS transistor 417 connected to the first power-down control terminal NPOWD41 is turned off when the digital value input from the first power-down control terminal NPOWD41 is "H", as in the related art. When the digital value is “L”, the switch is turned on. The switch elements 426 and 427 connected to the second power-down control terminal NPOWD42 via a delay element are It becomes non-conductive when the digital value is "L" and becomes conductive when the digital value is "H".
[0054]
The operation of the thus configured reference voltage generating circuit according to the third embodiment when switching from the normal operation mode to the power down mode, and then canceling the power down mode to return to the normal operation mode will be described.
First, in the case of the normal operation mode, a digital value “H” is input to the first and second power-down mode control terminals NPOWD41 and NPOWD42, whereby the PMOS transistor 417 is turned off and the switch element 426 Since the transistor 427 becomes conductive, the gate voltages VBA of the PMOS 411 and the PMOS 414 and the gate voltage VBB of the PMOS 412 and the PMOS 415 are output as the reference voltages VB41 and VB42.
[0055]
When switching from the normal operation mode to the power down mode, in the third embodiment, only the digital value input to the second power down control terminal NPOWD42 is switched to "L". As a result, the switching elements 426 and 427 become non-conductive and the PMOS transistor 418 becomes conductive and current flows. Therefore, the reference voltages VB41 and 42 are such that no current flows to the circuit to which the reference voltage VB is connected. The voltage, here, rises to around the power supply voltage ADVV (second potential).
[0056]
Then, when the power down mode is released, the digital value input to the second power down control terminal NPOWD 42 is switched from the “L” value to the “H” value. As a result, the switching elements 426 and 427 are turned on and the PMOS transistor 418 is turned off, so that the reference voltages VB41 and 42 are the gate voltages VBA of the PMOS transistors 411 and 414 and the gate voltages VBB of the PMOS transistors 412 and 415. It becomes.
[0057]
As described above, according to the third embodiment, in the reference voltage generation circuit, independent of the first switching means capable of switching the potentials of the reference voltages VB41 and VB42 by discharging the capacitance element C41, A second switching means capable of switching the potentials of the reference voltages VB41 and VB42 by opening and closing the first and second switch elements controlled according to the digital value inputted to the power down control terminal NPOWD42 of the second embodiment; The switching of the reference voltage potentials VB41 and VB42 is controlled by switching only the digital value applied to the second power-down control terminal NPOWD22. Therefore, when the power-down mode is released, the charge stored in the capacitor C41 is removed. It is not necessary to discharge, and as a result, it is possible to obtain a reference voltage generating circuit having a short recovery time from the power down mode to the normal operation mode. .
[0058]
【The invention's effect】
As described above, according to the reference voltage generation circuit of the first aspect of the present invention, the reference voltage generation circuit has the reference voltage generation terminal for generating the reference voltage, and the potential of the reference voltage generation terminal is controlled by an external control signal. A reference voltage generation circuit including a plurality of switching means for switching, wherein one of the plurality of switching means has a capacitor connected between a predetermined voltage and a first node, A first switching unit that switches the potential of the reference voltage generation terminal by charging and discharging the capacitance element according to the first control signal, wherein another one of the plurality of switching units includes the predetermined voltage; A second switching means for switching the potential of the reference voltage generating terminal by turning on and off the switching element by a second control signal; Of the reference voltage generation circuit It is possible to switch between the low power consumption mode and the normal operation mode by the second switching means independent of the charging and discharging of the capacitance element for stabilizing the reference voltage. Even when the capacitance of the capacitance element is large, The return time from the low power consumption mode to the normal operation mode can be shortened.
[0059]
According to the reference voltage generating circuit of the present invention, in the reference voltage generating circuit of the first aspect, the first switching means is connected to the capacitive element, A current path for setting a terminal of the circuit to a potential corresponding to a terminal voltage of the capacitor; and charging / discharging the capacitor by the first control signal to set the potential of the reference voltage generating terminal to a normal operation mode. Switching to the corresponding first potential or the second potential corresponding to the low power consumption mode. In the case of the normal operation mode, the second switching means operates in response to the second control signal and By turning off the switch element, the potential of the reference voltage generating terminal is fixed at the first potential set from the current path of the first switching means. The switching means of 2 By turning on the switch element in accordance with the second control signal, the potential of the reference voltage generation terminal is fixed at the second potential. The second switching means independent of the charging and discharging of the capacitive element for stabilizing the power consumption makes it possible to switch between the low power consumption mode and the normal operation mode. The return time from the power mode to the normal operation mode can be reduced.
[0060]
According to the reference voltage generating circuit of the third aspect of the present invention, in the reference voltage generating circuit of the second aspect, the second switching means includes a transistor and a resistor. Can be suppressed and the rise of the circuit operation can be accelerated, whereby the return time from the low power consumption mode to the normal operation mode can be further reduced.
[0061]
Further, according to the reference voltage generation circuit according to claim 4 of the present invention, the reference voltage generation circuit has a reference voltage generation terminal for generating a reference voltage, and a plurality of switching the potential of the reference voltage generation terminal by an external control signal. A reference voltage generating circuit including a switching unit, wherein one of the plurality of switching units has a capacitor connected between a power supply and a first node, and a first control signal Is a first switching means for switching the potential of the reference voltage generating terminal by charging and discharging of the capacitive element, and another one of the plurality of switching means is provided between a power supply and the first node. And a second switch element connected between the reference voltage generation terminal and one end of the capacitor element on the first node side. Of the first and second switch elements by the control signal of Since the second switching means switches the potential of the reference voltage generating terminal by turning on and off, the second switching means independent of charging and discharging of the capacitance element for stabilizing the reference voltage of the reference voltage generating circuit is provided. The means makes it possible to switch between the low power consumption mode and the normal operation mode, and the return time from the low power consumption mode to the normal operation mode can be reduced even when the capacitance of the capacitor is large.
[0062]
According to the reference voltage generating circuit of the present invention, in the reference voltage generating circuit of the present invention, the first switching means is connected to the capacitive element, A current path for setting a terminal of the circuit to a potential corresponding to a terminal voltage of the capacitor; and charging / discharging the capacitor by the first control signal to set the potential of the reference voltage generating terminal to a normal operation mode. Switching to the corresponding first potential or the second potential corresponding to the low power consumption mode. In the case of the normal operation mode, the second switching means operates in response to the second control signal and By turning off the first switch element and turning on the second switch element, the potential of the reference voltage generating terminal is changed to the first potential set by the current path of the first switching means. Fixed to the above In the case of the power consumption mode, the second switching means turns on the first switch element and turns off the second switch element in accordance with the second control signal, thereby generating the reference voltage. Since the potential of the terminal is fixed at the second potential, low potential is provided by the second switching means independent of charging and discharging of the capacitance element for stabilizing the reference voltage of the reference voltage generating circuit. It is possible to switch between the power consumption mode and the normal operation mode, and even when the capacitance of the capacitor is large, the return time from the low power consumption mode to the normal operation mode can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a reference voltage generation circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing another configuration of the reference voltage generation circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of a reference voltage generation circuit according to a second embodiment of the present invention.
FIG. 4 is a diagram showing another configuration of the reference voltage generation circuit according to the second embodiment of the present invention.
FIG. 5 is a diagram showing a configuration of a reference voltage generation circuit according to a fourth embodiment of the present invention.
FIG. 6 is a diagram showing a configuration of a conventional reference voltage generation circuit.
[Explanation of symbols]
111, 112, 114, 115, 116, 118, 119, 120, 121, 122, 211, 212, 214, 215, 216, 217, 220, 221, 223, 224, 225, 311, 312, 314, 315, 317,320,321,323,324,325,411,412,414,415,416,417,418,511,512,514,517 PMOS transistors
218, 219, 222, 318, 319, 322, 419, 420 NMOS transistors
113,117,123,213,216,229,231,313,326,331,413,416,513,516 Current source element
423, 424, 425 Delay element
426,427 switch element
C11, C21, C31, C41, C51 Capacitive element
R11, R12, R13 Resistive element
NPOWD11, NPOWD12, NPOWD21, NPOWD22, NPOWD31, NPOWD32, NPOWD41, NPOWD42, NPOWD Power down control terminal

Claims (5)

A reference voltage generation circuit having a reference voltage generation terminal for generating a reference voltage, and including a plurality of switching means for switching the potential of the reference voltage generation terminal by an external control signal,
One of the plurality of switching means has a capacitance element connected between a predetermined voltage and a first node, and charges and discharges the capacitance element according to a first control signal, whereby the reference voltage A first switching means for switching the potential of the generation terminal,
Another one of the plurality of switching means has a switch element connected between the predetermined voltage and a second node, and is turned on and off by a second control signal. A second switching unit for switching the potential of the reference voltage generation terminal;
A reference voltage generating circuit characterized by the above-mentioned. The reference voltage generating circuit according to claim 1,
The first switching means has a current path to which the capacitance element is connected and which sets a terminal of the reference voltage generation circuit to a potential corresponding to a terminal voltage of the capacitance element, and a capacitance based on the first control signal. Switching the potential of the reference voltage generation terminal to a first potential corresponding to a normal operation mode or a second potential corresponding to a low power consumption mode by charging and discharging the element;
In the case of the normal operation mode, the second switching means turns off the switching element according to the second control signal, thereby changing the potential of the reference voltage generating terminal to the current of the first switching means. Fixed to the first potential set from the path,
In the case of the low power consumption mode, the second switching unit fixes the potential of the reference voltage generation terminal to the second potential by turning on the switch element by the second control signal. To do,
A reference voltage generating circuit characterized by the above-mentioned. The reference voltage generating circuit according to claim 2,
The second switching means includes a transistor and a resistor.
A reference voltage generating circuit characterized by the above-mentioned. A reference voltage generation circuit having a reference voltage generation terminal for generating a reference voltage, and including a plurality of switching means for switching the potential of the reference voltage generation terminal by an external control signal,
One of the plurality of switching means has a capacitive element connected between a power supply and a first node, and the reference voltage generating terminal is provided by charging and discharging the capacitive element by a first control signal. The first switching means for switching the potential of
Another one of the plurality of switching means is a first switch element connected between a power supply and the first node, the reference voltage generation terminal, and the first of the capacitance elements. A second switch element connected between one end of the reference voltage generation terminal and a second switch element connected between the first and second switch elements by a second control signal. Is a second switching means for switching
A reference voltage generating circuit characterized by the above-mentioned. The reference voltage generating circuit according to claim 4,
The first switching means has a current path to which the capacitance element is connected and which sets a terminal of the reference voltage generation circuit to a potential corresponding to a terminal voltage of the capacitance element, and a capacitance based on the first control signal. Switching the potential of the reference voltage generation terminal to a first potential corresponding to a normal operation mode or a second potential corresponding to a low power consumption mode by charging and discharging the element;
In the case of the normal operation mode, the second switching means turns off the first switch element and turns on the second switch element in accordance with the second control signal, thereby setting the reference voltage. Fixing the potential of the generating terminal to the first potential set from the current path of the first switching means,
In the case of the low power consumption mode, the second switching means turns on the first switch element and turns off the second switch element in accordance with the second control signal, thereby setting the reference value. And fixing the potential of the voltage generating terminal to the second potential.
A reference voltage generating circuit characterized by the above-mentioned.

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