JP2004094973A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor wherein, when an instruction comprising a branch and at least one non-branch processing unit is executed, pipeline interlock is prevented from occurring even if the branch address of the instruction is set by instruction misalignment, and thereby the execution time of the instruction is not extended so that processing performance is not degraded. <P>SOLUTION: An instruction reading part 60 reads an instruction based on a read address. When a read instruction comprises a branch and one or more non-branch processing units, an instruction decoding part 30 issues a command for processing the processing unit of the branch prior to any of the non-branch processing units. This is effective in preventing pipeline interlock caused by instruction misalignment of the branch address from occurring, and thereby preventing extension of the execution time of the instruction to prevent degradation of processing performance. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a processor which is used as a CPU of an information processing apparatus and employs a pipeline control system including at least three stages of an instruction reading stage, an instruction decoding stage, and an instruction execution stage.

With the recent development of electronic technology, information processing devices such as microprocessors have become widespread and used in all fields.
Conventional processors are mainly classified into a CISC processor (Complex Instruction Set Computer), which is characterized by a wide variety of instructions, and a RISC processor (Reduced Instruction Set Computer), which is characterized by a limited number of instructions and characterized by high speed. Can be different. For example, TRON and MC68040 are the former, and SPARC and MIPS are the latter.

In both types of processors, the apparent execution time of instructions is reduced by adopting a pipeline structure. The pipeline is a processing method in which at least a processing stage of an instruction is read, decoded, and executed, and different stages of a plurality of instructions are executed in parallel. Unlike the RISC processor, many CISC processors take a variable-length instruction format. In the variable-length instruction format, the word length of the instruction differs depending on the type of the instruction, and generally, the size of the program can be reduced as compared with the fixed-length instruction format.

(5) On the other hand, since instructions are not fixed at word (16-bit) boundaries or double-word (32-bit) boundaries in instruction reading, many instructions are arranged across boundaries. Therefore, there are cases where the instruction to be decoded is not read to the end even if the instruction is prefetched. In this case, it is necessary to temporarily stop the parallel processing by the pipeline.

This temporary stop of the pipeline is called pipeline interlock, and the state where the instruction causing the temporary stop is placed across the boundary is called instruction misalignment.
As a conventional processor, for example, there is a processor disclosed in Japanese Patent Application Laid-Open No. 5-197546 (title of the invention: "Microcomputer and division circuit"). In this conventional processor, as described in page 27, paragraph 88, the JSR (Jump SubRoutine: subroutine call / procedure call) instruction performs branch processing after saving the contents of the program counter PC.

This conventional processor has a pipeline structure including three stages of an instruction read stage, a decoding / address calculation stage, and an operation execution stage, and has a 4-byte instruction buffer for storing an instruction read in the instruction read stage, and an instruction operation. And a control storage for storing a microinstruction for realizing a processing unit obtained by subdividing the above.
In the instruction reading stage, if the read address is an even address, two bytes are read in one machine cycle, and if the read address is an odd address, one byte is read and stored in the instruction buffer.

In the decoding / address calculation stage, a microinstruction corresponding to the instruction at the bottom of the instruction buffer (the first instruction) is read from the control storage, and a control signal indicated by the microinstruction is output. If the instruction decoded in the decoding / address calculation stage is composed of a plurality of microinstructions, a control signal indicating one microinstruction is output every machine cycle.
In the operation execution stage, the instruction of one processing unit output from the control storage is executed in one machine cycle.

FIG. 5 is a diagram showing the operation timing of the conventional processor. This figure shows the instructions processed in each stage of the pipeline, the contents of the instruction buffer, and the output contents of each processing unit output from the control storage at each timing called a machine cycle. The programs illustrated in the figure are as follows.
Instruction 1: Address ADD D0, D1
(This is a 1-byte instruction that adds the value of the D0 register and the value of the D1 register and stores the result in the D1 register, and consists of a microinstruction in one processing unit.)
Instruction 2: Address 101 JSR @ (disp16, PC)
(This is a 3-byte instruction that branches to a subroutine at an address obtained by adding a 16-bit deviation to the value of the program counter, and consists of micro-instructions in three processing units. The branch destination is address 201.)
Instruction 3: Address 201 MOV @ (disp8, A0), D0
(This is a 2-byte instruction that loads data at an address obtained by adding an 8-bit deviation to the value of the A0 register into the D0 register, and consists of a micro instruction in one processing unit.)
In the above program example, the 3-byte length JSR instruction (instruction 2) and the 3-byte length MOV instruction (instruction 3) are arranged from odd addresses and are misaligned.

FIG. 9 is an explanatory diagram showing the contents of operations executed by the three processing units of the instruction 2 (JSR @ (disp16, PC)). As shown in the figure, the JSR instruction includes a processing unit of stack pointer subtraction, return destination store, and branch execution. SP indicates a stack pointer, PC indicates a program counter, and disp16 indicates a 16-bit address deviation. The operation of each processing unit is executed at timings t4, t5, and t6 in FIG.

The operation of the conventional processor will be described with reference to FIG.
(Timing t1)
At the instruction reading stage, a 2-byte instruction code is read from address 100.
(Timing t2)
The instruction codes at addresses 100 and 101 read at the timing t1 are stored in the instruction buffer, and the instruction 1 at address 100 is taken out from the bottom of the instruction buffer and decoded at the decoding / address calculation stage. Since the instruction 1 is 1 byte, the end of the instruction exists in the instruction buffer. In the instruction read stage, a read address incremented by 2 is calculated, and a 2-byte instruction code is read from address 102.

(Timing t3)
An instruction for addition relating to instruction 1 is output from the decoding / address calculation stage, and is executed in the operation execution stage. The processing unit for the instruction 1 is unique, and the execution completes the execution of the instruction 1. The instruction codes at addresses 102 and 103 read at the previous timing are stored in the instruction buffer, and the instruction 2 at address 101 is taken out from the bottom of the instruction buffer, and the decoding and address calculation at the decoding / address calculation stage are performed. Do. Instruction 2 has 3 bytes, but the end of the instruction exists in the instruction buffer. The instruction reading stage does not read the instruction because there is no space of 2 bytes or more in the instruction buffer.

(Timing t4)
An instruction for stack pointer decrement, which is the first processing unit for the instruction 2, is output from the decoding / address calculation stage, and is executed in the operation execution stage. Instruction 2 is composed of three processing units. In the instruction read stage, a read address incremented by 2 is calculated, and a 2-byte instruction code is read from address 104.

(Timing t5)
From the decoding / address calculation stage, an instruction to store the return address to the stack, which is the second processing unit for the instruction 2, is output, and this is executed in the operation execution stage. The instruction codes at addresses 104 and 105 read at the previous timing are stored in the instruction buffer. In the instruction read stage, a read address incremented by 2 is calculated, and a 2-byte instruction code is read from address 106.

(Timing t6)
The instruction for branching, which is the third processing unit for instruction 2, is output from the decoding / address calculation stage, and is executed in the operation execution stage. In accordance with this branch instruction, all instructions in the instruction buffer are flushed, and the instruction read stage receives the branch destination address calculated earlier in the decoding / address calculation stage, and reads a 1-byte instruction code from address 201. Since the received address is an odd address, only one byte is read. Instruction 2 is completed by this execution.

(Timing t7)
The instruction code at the address 201 read at the previous timing is stored in the instruction buffer, and the instruction 3 at the address 201 is taken out from the bottom of the instruction buffer to be decoded at the decoding / address calculation stage. Since the end of the instruction does not exist in the instruction buffer, it cannot be decoded. Therefore, the operation in the decoding / address calculation stage is stopped (pipeline interlock). In the instruction read stage, since the previous read address is an odd number, a read address incremented by 1 is calculated, and a 2-byte instruction code is read from address 202.

(Timing t8)
Since the operation at the decoding / address calculation stage has been stopped at the previous timing, the operation at the operation execution stage is stopped at this timing (pipeline interlock). The instruction codes at addresses 202 and 203 read at the previous timing are stored in the instruction buffer, and the instruction 3 at address 201 is taken out from the bottom of the instruction buffer, and the decoding and load calculation is performed in the decoding / address calculation stage. . Since the instruction 3 is 2 bytes, the end of the instruction is present in the instruction buffer for the first time at this timing. The instruction reading stage does not read the instruction because there is no space of 2 bytes or more in the instruction buffer.

(Timing t9)
A load instruction relating to the instruction 3 is output from the decoding / address calculation stage, and is executed in the operation execution stage. There is only one processing unit for the instruction 3, and the execution completes the execution of the instruction 3. In the instruction read stage, a read address incremented by 2 is calculated, and a 2-byte instruction code is read from address 204.

However, according to the above-described conventional processor, when a branch instruction including a plurality of processing units (micro instructions) is misaligned in the variable-length instruction format, the processing unit for branching is executed in the last machine cycle. Therefore, there is a problem that a pipeline interlock occurs, the entire instruction execution time is extended, and the processing performance is deteriorated.
More specifically, referring to FIG. 5, at time t7, the instruction 3 is taken out from the bottom of the instruction buffer and is to be decoded. However, it cannot be decoded because the last one byte of the 2-byte instruction 3 does not exist in the instruction buffer. The situation happens. This is because the 2-byte instruction 3 is located at an odd address and the instruction at the branch destination is being read at the immediately preceding timing t6. Further, there is a problem in that prefetching of instructions that are clearly executed and not flushed at timings t4 and t5 is performed, and unnecessary power is wasted in reading these instructions.

In view of such a problem, the present invention does not cause pipeline interlock due to the absence of an instruction when executing an instruction including a branch and at least one processing unit that is not a branch even if the branch destination of the instruction is an instruction misalignment. Accordingly, an object of the present invention is to provide a processor in which the execution time of an instruction does not extend and the processing performance does not deteriorate.

In order to solve the above problem, a processor according to claim 1 of the present invention is a processor that prefetches an instruction,
Fetch address holding means for holding an address of an instruction to be prefetched;
For the control processing relating to the execution of the branch instruction including the processing unit of the branch having the content of rewriting the address of the fetch address holding means and the other processing unit, the execution of the processing unit of the branch is controlled first, Control means for controlling the execution of other processing units, wherein the processing unit of the branch and the other processing units are executed in the same pipeline stage.

The processor according to claim 2 is the processor according to claim 1,
The control processing includes execution control of a subroutine call instruction,
The control means writes the branch destination address obtained based on the operand of the subroutine call instruction to the fetch address holding means in the control of the branch processing unit, and in the other processing unit, stores the return destination address in the area where the return destination address is to be saved. It is configured to control the address calculation and the saving of the return address.

The processor according to claim 3 is the processor according to claim 2,
The control processing includes a transition control to an interrupt processing routine,
In the control of the processing unit of the branch, the control unit writes a start address of a predetermined interrupt processing routine into a fetch address holding unit, and calculates an address of an area where a return address is to be saved in another processing unit and calculates a return destination. It is configured to control saving of addresses.

According to a fourth aspect of the present invention, in the processor according to any one of the first to third aspects, the control processing includes a return instruction instructing return from a subroutine and a return instruction instructing return from an interrupt processing routine. Including
The control means is configured to write a return address to a fetch address holding means in controlling the processing unit of the branch.

The processor according to claim 5 is the processor according to claim 3, wherein the control unit includes:
A control storage unit that stores a plurality of micro-instructions for realizing the operation of the control process,
A micro-instruction issuing unit for sequentially reading micro-instructions corresponding to each processing unit from the control storage and issuing a control signal designated by the micro-instruction to the inside of the processor;
The microinstruction issuing unit includes:
For a subroutine call instruction, a microinstruction instructing to store the address specified in the instruction in the fetch address holding means, and a microinstruction instructing to calculate the address of the area where the return address is to be saved And a microinstruction for instructing to save the return address, in this order,
For control of transition to the interrupt processing routine, a microinstruction instructing to store a predetermined interrupt processing start address in the fetch address holding means and a microinstruction instructing calculation of an address of an area where a return address is to be saved are provided. An instruction and a microinstruction instructing to save the return address are issued in this order.

The processor according to claim 6 is the processor according to claim 3, wherein the control unit includes:
An address calculation unit for pre-decoding a subroutine call instruction and calculating a branch destination address of the instruction;
A control storage unit that stores a plurality of microinstructions that implements the control processing;
A micro-instruction issuing unit for sequentially reading micro-instructions corresponding to the respective processing units from the control storage, and issuing the micro-instructions inside the processor;
The microinstruction issuing unit includes:
In response to a subroutine call instruction, a microinstruction for storing an address obtained by the address calculation unit in the fetch address holding unit and instructing a store buffer holding data to be stored in a memory to hold a return address. A microinstruction for instructing to update the stack pointer pointing to the save area and to store the updated contents of the stack pointer in the operand address buffer to hold the operand address, and to store the contents of the store buffer in the operand address buffer. Issue a microinstruction instructing to store in the save area pointed to in this order,
For the control of transition to the interrupt processing routine, a microinstruction for storing the start address of the predetermined interrupt processing in the fetch address holding means and for holding the return address in the store buffer, and updating the stack pointer , And a microinstruction instructing to store the updated contents of the stack pointer in the operand address buffer, and a microinstruction instructing to store the contents of the store buffer in the save area pointed to by the operand address buffer. Issue.

According to the processor of the first aspect of the present invention, at least two times of instruction reading are performed at the timing when the branch destination instruction becomes decodable, so that even if the branch destination is instruction misalignment, the pipeline due to the absence of an instruction. Since no interlock occurs, there is an effect that the execution time of the instruction is not extended and the processing performance is not degraded.
According to the processor of the second aspect, the same effect as that of the first aspect is obtained particularly for a subroutine call instruction.

According to the processor of the third aspect, the same effect as that of the second aspect is obtained particularly for control of transition to an interrupt processing routine.
According to the processor of the fourth aspect, in addition to the effects of the first to third aspects, a return instruction instructing return from a subroutine and a return instruction instructing return from an interrupt processing routine are provided. It has the same effect as any one of 1 to 3.

According to the processor of the fifth aspect, in addition to the effect of the third aspect, the execution time of the instruction is not extended due to the control by the microprogram, particularly for the control of shifting to the subroutine call instruction and the interrupt processing routine, and the processing performance is deteriorated. It has the effect of not doing it.
According to the processor of the sixth aspect, in addition to the effect of the third aspect, by controlling the address calculation independently of the control by the microprogram, it is possible to instruct the subroutine call instruction and the transition control to the interrupt processing routine. Has the effect that the execution time does not increase and the processing performance does not deteriorate.

2. The processor of claim 1, wherein the processor performs prefetching of instructions.
Fetch address holding means for holding an address of an instruction to be prefetched;
For the control processing relating to the execution of the branch instruction including the processing unit of the branch having the content of rewriting the address of the fetch address holding means and the other processing unit, the execution of the processing unit of the branch is controlled first, Control means for controlling execution of other processing units. As a result, even if the branch destination is an instruction misalignment, pipeline interlock due to the absence of an instruction does not occur.

The processor according to claim 2, wherein the control processing of the processor according to claim 1 includes execution control of a subroutine call instruction,
The control means writes the branch destination address obtained based on the operand of the subroutine call instruction to the fetch address holding means in the control of the branch processing unit, and in the other processing unit, stores the return destination address in the area where the return destination address is to be saved. Controls address calculation and return address saving.

4. The processor according to claim 3, wherein the control processing of the processor according to claim 2 includes control for shifting to an interrupt processing routine.
In the control of the processing unit of the branch, the control unit writes a start address of a predetermined interrupt processing routine into a fetch address holding unit, and calculates an address of an area where a return address is to be saved in another processing unit and calculates a return destination. Controls evacuation of addresses.

In the processor according to the fourth aspect, the control processing of the processor according to the first to third aspects includes a return instruction instructing return from a subroutine and a return instruction instructing return from an interrupt processing routine,
The control unit writes a return address to a fetch address holding unit in the control of the processing unit of the branch.

The processor according to claim 5, wherein the control means of the processor according to claim 3 comprises:
A control storage unit that stores a plurality of micro-instructions for realizing the operation of the control process,
A micro-instruction issuing unit for sequentially reading micro-instructions corresponding to each processing unit from the control storage and issuing a control signal designated by the micro-instruction to the inside of the processor;
The microinstruction issuing unit includes:
For a subroutine call instruction, a microinstruction instructing to store the address specified in the instruction in the fetch address holding means, and a microinstruction instructing to calculate the address of the area where the return address is to be saved And a microinstruction for instructing to save the return address, in this order,
For control of transition to the interrupt processing routine, a microinstruction instructing to store a predetermined interrupt processing start address in the fetch address holding means and a microinstruction instructing calculation of an address of an area where a return address is to be saved are provided. An instruction and a microinstruction instructing to save the return address are issued in this order.

The processor according to claim 6, wherein the control means of the processor according to claim 3 comprises:
An address calculation unit for pre-decoding a subroutine call instruction and calculating a branch destination address of the instruction;
A control storage unit that stores a plurality of microinstructions that implements the control processing;
A micro-instruction issuing unit for sequentially reading micro-instructions corresponding to the respective processing units from the control storage, and issuing the micro-instructions inside the processor;
The microinstruction issuing unit includes:
In response to a subroutine call instruction, a microinstruction for storing an address obtained by the address calculation unit in the fetch address holding unit and instructing a store buffer holding data to be stored in a memory to hold a return address. A microinstruction for instructing to update the stack pointer pointing to the save area and to store the updated contents of the stack pointer in the operand address buffer to hold the operand address, and to store the contents of the store buffer in the operand address buffer. Issue a microinstruction instructing to store in the save area pointed to in this order,
For the control of transition to the interrupt processing routine, a microinstruction for storing the start address of the predetermined interrupt processing in the fetch address holding means and for holding the return address in the store buffer, and updating the stack pointer , And a microinstruction instructing to store the updated contents of the stack pointer in the operand address buffer, and a microinstruction instructing to store the contents of the store buffer in the save area pointed to by the operand address buffer. Issue.

FIG. 1 is a block diagram showing a schematic configuration of a processor according to an embodiment of the present invention. As shown in FIG. 1, the processor 10 includes a decoding unit 30 having an instruction buffer 32 and a control memory 33, a register unit 40, an operation execution unit 50, an instruction reading unit 60, and a bus interface unit 70. The respective processes in the decoding unit 30 and the operation execution unit 50 are simultaneously executed as a pipeline.

The input / output bus 711 is an input / output bus for exchanging data between the processor 10 and the outside world, and is connected to an external memory (not shown) for storing programs and data.
The bus interface unit 70 controls the input / output bus 711.
The instruction reading unit 60 reads an instruction from an external memory via the bus interface unit 70. At this time, the instruction reading unit 60 receives an address from the decoding unit 30 or the arithmetic execution unit 50 only when the read address becomes discontinuous due to execution of a branch instruction or the like, and when the read address is continuous, an internal increment circuit has Calculate the read address and read the instruction. The read instruction reads two bytes in one machine cycle if the read address is an even address, and reads one byte if the read address is an odd address, and stores it in the 4-byte instruction buffer 32.

The decoding unit 30 decodes the instruction received from the instruction reading unit 60 and controls execution of the instruction. When the instruction involves memory access, the arithmetic execution unit 50 is caused to calculate the operand address, and when the instruction involves a branch, the branch execution address is calculated. The decryption unit 30 has a control memory 33 therein and issues one processing instruction when the decrypted instruction is composed of one processing unit, and issues one processing unit per machine cycle when the decrypted instruction is composed of a plurality of processing units. The processing instructions are issued one by one.

The register block 40 has a plurality of registers specified by the operand of the instruction.
The arithmetic execution unit 50 has an arithmetic unit for performing an arithmetic and logic operation therein, and executes an instruction of one processing unit output from the control storage 33 in one machine cycle.
FIG. 2A is an explanatory diagram showing the configuration of the control storage 33. The control memory 33 stores processing units (micro instructions) corresponding to all machine language instructions, and FIG.

Reference numeral 211 denotes a storage area for storing the contents of a microinstruction to be referred to and issued when the instruction 1 (addition instruction) is decoded, and represents an addition instruction. In the instruction 1, only the contents of the control storage area 211 are issued in one machine cycle.
Reference numerals 221 to 223 denote control storage areas for storing microinstructions to be referred and issued when the instruction 2 (JSR instruction) is decoded, and realize branch, decrement of the stack pointer, and storage of the return address to the stack, respectively. Indicates the processing unit to be used. In the instruction 2, the contents of the control storage areas 221 to 223 are sequentially issued over three machine cycles.

A control storage area 231 stores the contents of processing to be referred to and issued when the instruction 3 (MOV instruction) is decrypted, and indicates a load instruction. In the instruction 3, only the contents of the control storage area 231 are issued in one machine cycle.
FIG. 3 is a block diagram showing a more detailed configuration of the processor shown in FIG.
In FIG. 1, a processor 10 includes an instruction decoding unit 30, a register unit 40, an operation execution unit 50, an instruction reading unit 60, and a bus interface unit 70, a bus (hereinafter abbreviated as ABUS) 20, a first data bus (B1BUS). 21, a second data bus (abbreviated as B2BUS) 22, an instruction address bus (abbreviated as NIADDR) 701, an instruction bus (abbreviated as IBUS) 702, an operand address bus (abbreviated as OADDR) 703, and a store data bus (STBUS). 704) and a load data bus (abbreviated as LDBUS) 705 as shown in the figure.

The instruction decoding unit 30 stores and decodes pre-read instructions and controls the entire microcomputer, so that an interrupt control unit 31, an instruction buffer (abbreviated as IB) 32, a control storage 33, a selector 34, an instruction register 35, and a status register 36 are provided. , A predecoder 37, and a microinstruction register 38.
The interrupt control unit 31 controls the operation sequence of the microcomputer when receiving an interrupt.

The instruction buffer 32 stores the instruction read from the memory by the instruction reading unit 60 prior to the execution of the instruction. This embodiment has a capacity to store 4 bytes of instructions.
The selector 34 selects one of an instruction input from the instruction buffer 32 and an instruction input from the instruction bus.
The instruction register 35 holds an instruction output from the selector 34.

The status register 36 holds various status flags required for decoding the instruction.
The control memory 33 decodes the instruction in the instruction register 35 with reference to the contents of the status register 36. In this embodiment, control logic by a microprogram is implemented using a programmable logic array (PLA), and microinstructions for realizing the instructions in the instruction register 35 are sequentially output.

The predecoder 37 receives the contents of the instruction register 35 and the contents of the status register 36, and outputs a control signal for executing a load instruction and a conditional branch instruction that operate mainly in one cycle. This operation is performed in the instruction decoding stage prior to the instruction execution stage. In particular, for branch instructions such as a subroutine call instruction and an interrupt processing request instruction, control is performed to store the branch destination address specified in the instruction in the PCB 64 and the IAB 72. When it is specified by a displacement (deviation) to the branch destination address, the arithmetic execution unit 50 executes the calculation of the branch destination address, and stores the calculation result in the PCB 64 and the IAB 72.

The microinstruction register 38 holds a control instruction, which is a decoding result of the control storage 33.
The register section 40 includes a data register group 41, an address register group 42, and a selector 43 for holding data and addresses. The data register group 41 includes four 16-bit registers DR3 to DR0 that mainly hold data. The address register group 42 includes four 16-bit registers AR3 to AR0 that mainly hold addresses. AR3 functions as a stack pointer.

The selector 43 selectively outputs to the data register group 41 and the address register group 42 from the ABUS 20 and the LDBUS 705.
The arithmetic execution unit 50 includes an arithmetic unit 51, a program status word 52, an operand address register 53, a selector 54, a selector 55, a temporary register 56, a selector 57, a selector 58, and a shifter 59 for calculating an address and performing data operation. It is configured.

The arithmetic unit 51 performs 16-bit data operation and address calculation.
The program status word 52 is a 16-bit register that holds a flag and the like of the operation result.
Operand address register 53 stores an address for accessing the memory.
The selectors 54 and 55 select an operand to be input to the arithmetic unit 51.

The temporary register 56 temporarily holds the output of the arithmetic unit 51.
The selector 57 selects one of the temporary register 56 and the operand address register 53 and outputs it to the operand address buffer 74.
The selector 58 selects one of the ABUS 20 and the shifter 59.
The shifter 59 receives the output of the selector 58 and performs a shift operation together with the arithmetic unit 51.

The instruction reading section 60 includes a first prefetch counter (abbreviated as PFC) 61, a second prefetch counter (abbreviated as PFCP) 62, a selector 63, a program counter buffer (abbreviated as PCB) 64, It comprises an incrementer (abbreviated as INC) 65 and a selector 66.
The PCB 64 holds a read address of an instruction output from the selector 66.

The INC 65 increments the content of the PCB 64 by +1 or +2 and outputs the incremented value to the IAB 72 via the PFC 61 and the selector 66 as a prefetch address of the instruction.
The PFC 61 holds the address incremented by the INC 65.
The PFCP 62 holds the address immediately before the PFC 61.
The selector 63 selects one of the PFC 61 and the PFCP 62 and outputs it to the ABUS 20 and the B1BUS 21.

The selector 66 selects the output of the PFC 61 when the instruction of the continuous address is read, and selects and outputs the address from the temporary register 56 or the operand address register 53 when branching.
The bus interface unit 70 controls connection of the bus when reading instructions and data from an external memory (not shown), and includes an interface unit 71, an instruction address buffer 72, an instruction buffer 73, an operand address buffer 74, a store buffer 75, and a load. It comprises a buffer 76, a bus switch 77, a RAM 78 and a ROM 79.

The interface unit 71 controls connection between the bus of the CPU 6 and the outside.
An instruction address buffer (abbreviated as IAB) 72, an instruction buffer 73, an operand address buffer 74, a store buffer 75, and a load buffer 76 are buffers for holding an instruction address, an instruction, an operand address, store data, and load data, respectively. .
The bus switch 77 connects and disconnects the buses 706 to 709.

The RAM 78 and the ROM 79 store data and instructions, respectively. In this embodiment, since the external memory is assumed, the RAM 78 and the ROM 79 may be ignored.
FIG. 2B is an explanatory diagram showing a detailed operation of a processing unit for realizing the machine language instruction JSR @ (disp16, PC) by the predecoder 37, the control memory 33, and the microinstruction register 38. As shown in FIG. 2A, the JSR @ (disp16, PC) instruction includes three processing units: branch, stack pointer subtraction, and return store.

The branch is performed by a control operation (PFCP or PFC + disp16 + 0 or 1 → PCB, IAB) by the predecoder 37 and a control operation (PFCP or PFC + 0 or 1 → STB) by the control memory 33 and the microinstruction register 38. Is achieved. The branch destination address (PFCP or PFC + disp16 or 0/1) is calculated under the control of the former predecoder 37, and the calculation result is written to the PCB 64 and the IAB 72. The branch destination address is obtained by adding either the PFC 61 or the PFCP 62, the 16-bit displacement, and 0 or 1. The selection between the PFC 61 and the PFCP 62 and the selection between 0 and 1 are selected according to the remaining amount of the instruction buffer 32. As a result of the calculation result being written into the PCB 64 and the IAB 72, instructions are sequentially fetched from the branch destination address. The return address is held in the store buffer 75 by the latter control operation. This is preparation for the return destination store, and the return destination address is stored. This control is realized by issuing a control signal designated by the microinstruction in the control storage area 221 from the microinstruction register 38.

処理 The processing unit for stack pointer subtraction is processing (AR3-4 → AR3, OAB) that changes the value of the stack pointer to an unused area of the stack (save area). In this embodiment, since the address register AR3 is a stack pointer, AR3 is subtracted by 4. At the same time, the subtraction result is also stored in the OAB 74 as preparation for the return store. This control is realized by a microinstruction of the stack pointer subtraction in the control storage area 222.

処理 The processing unit of the return store is processing for saving the return address in an unused area of the stack indicated by the stack pointer. At this point, since the value of the subtracted stack pointer has already been stored in the OAB 74 and the return address has been stored in the STB 75, control for storing the contents of the STB 75 in the memory area pointed to by the OAB 74 is performed. This control is realized by a microinstruction of the return destination store in the control storage area 223.

The operation of the processor of the present embodiment configured as described above will be described below. In order to clarify the difference from the related art, the description will be made using the same program example used in the description of the related art. An example program is shown below.
Instruction 1: Address ADD D0, D1
(This is a 1-byte instruction that adds the value of the D0 register and the value of the D1 register and stores the result in the D1 register, and consists of a microinstruction in one processing unit.)
Instruction 2: Address 101 JSR @ (disp16, PC)
(This is a 3-byte instruction that branches to a subroutine at an address obtained by adding a 16-bit deviation to the value of the program counter, and consists of micro-instructions in three processing units. The branch destination is address 201.)
Instruction 3: Address 201 MOV @ (disp8, A0), D0
(This is a 2-byte instruction that loads data at an address obtained by adding an 8-bit deviation to the value of the A0 register into the D0 register, and consists of a micro instruction in one processing unit.)
FIG. 7 shows an operation timing chart of the processor in the embodiment. The figure shows the instructions processed by the instruction reading unit 60, the decoding unit 30, and the operation executing unit 50, the contents of the instruction buffer 32, and the output contents of the control storage 33 at each timing called a machine cycle. The description will be given for each timing in order of elapse of time.

(Timing t1)
The instruction reading section 60 reads a 2-byte instruction code from address 100. It is assumed that this read address is received at this timing from the decoding unit 30 or the operation execution unit 50 for a branch (not shown) and other reasons. It is also assumed that the instruction buffer 32 is empty.
(Timing t2)
The instruction codes at addresses 100 and 101 read at the previous timing are stored in the instruction buffer 32, and the instruction 1 at address 100 is taken out from the bottom of the instruction buffer 32 and decoded by the decoding unit 30. Since the instruction 1 is one byte, the end of the instruction exists in the instruction buffer 32. The instruction reading unit 60 calculates a read address incremented by 2 and reads a 2-byte instruction code from address 102.

(Timing t3)
An instruction for addition relating to the instruction 1 is output from the control storage area 211 of the decoding unit 30 and is executed by the arithmetic execution unit 50. With this execution, the execution of the instruction 1 is completed. The instruction codes at addresses 102 and 103 read at the previous timing are stored in the instruction buffer 32, and the instruction 2 at address 101 is taken out from the bottom of the instruction buffer 32, and the decoding unit 30 decodes and calculates the address of the branch destination. Do. The instruction 2 is 3 bytes, but the end of the instruction exists in the instruction buffer 32. The instruction reading unit 60 does not read the instruction because the instruction buffer 32 has no space of 2 bytes or more.

(Timing t4)
A branch instruction, which is the first processing unit for the instruction 2, is output from the control storage area 221 of the decoding unit 30 and is executed by the arithmetic execution unit 50 as shown in FIG. In accordance with this branch instruction, all instructions in the instruction buffer 32 are flushed, and the instruction reading unit 60 receives the branch destination address calculated by the decoding unit 30 at the previous timing, and reads the 1-byte instruction code from address 201. put out. Since the received address is an odd address, only one byte is read.

(Timing t5)
An instruction for stack pointer decrement, which is the second processing unit for the instruction 2, is output from the control storage area 222 of the decoding unit 30, and is executed by the arithmetic execution unit 50 as shown in FIG. The instruction code at the address 201 read at the previous timing is stored in the instruction buffer 32. The instruction read unit 60 calculates the read address incremented by 1 since the previous read address is an odd number, and reads a 2-byte instruction code from address 202.

(Timing t6)
An instruction to store the return address to the stack, which is the third processing unit for the instruction 2, is output from the control storage area 223 of the decoding unit 30 and is executed by the arithmetic execution unit 50 as shown in FIG. The instruction codes at addresses 202 and 203 read at the previous timing are stored in the instruction buffer 32. The instruction reading unit 60 does not read the instruction because the instruction buffer 32 has no space of 2 bytes or more. Instruction 2 is completed by this execution.

(Timing t7)
The instruction 3 at address 201 is taken out from the bottom of the instruction buffer 32, and the decoding unit 30 calculates the addresses for decoding and loading. Although the instruction 3 is 2 bytes, the end of the instruction already exists in the instruction buffer 32 at this timing, and the pipeline interlock does not occur. The instruction reading unit 60 does not read the instruction because the instruction buffer 32 has no space of 2 bytes or more.

(Timing t8)
A load instruction relating to the instruction 3 is output from the control storage area 231 of the decryption unit 30 and is executed by the arithmetic execution unit 50. With this execution, the execution of the instruction 3 is completed. The instruction reading unit 60 calculates a read address incremented by 2 and reads a 2-byte instruction code from address 204.

As described above, according to the present embodiment, when a branch instruction to a subroutine is executed, a branch instruction is first output from the control memory 33 of the decoding unit 30 prior to another instruction. In parallel with the execution of the stack pointer decrement and the store of the return address to the stack, the instruction read unit 60 can read the instruction of the branch destination twice, and even if the instruction of the branch destination is misaligned, At the time of decoding the instruction, the instruction of the branch destination of 3 bytes is stored in the instruction buffer 32, so that the pipeline interlock due to the absence of the instruction in the instruction buffer 32 can be avoided.

In this embodiment, a case of a branch instruction to a subroutine is described, but any instruction can be applied as long as the instruction includes a branch processing unit and at least one non-branch processing unit. For example, in the branch processing to the interrupt processing routine, the control storage 33 may be configured to issue a branch instruction before decrementing the stack pointer and storing the return address to the stack and the status word. In the case of a return instruction from a subroutine or a return instruction from an interrupt processing routine, the control memory 33 is configured to issue a branch instruction prior to loading of a return address and a status word from the stack and incrementing the stack pointer. do it.

In the embodiment, the capacity of the instruction buffer 32 is 4 bytes, but may be 5 bytes or more. In this case, at the time of decoding the branch destination instruction of the branch instruction to the subroutine, the branch destination instruction of at least 5 bytes is stored in the instruction buffer 32, which is more effective. Alternatively, the capacity of the instruction buffer 32 may be 3 bytes.
Further, in the embodiment, the instruction read out in one machine cycle by the instruction reading unit 60 has a maximum of 2 bytes, but this may be 4 bytes or more. As the length of an instruction word read in one machine cycle increases, the probability of instruction misalignment across read address boundaries decreases. However, no matter how long the word length is, instruction misalignment does not disappear.

The present invention relates to a technique capable of suitably preventing the occurrence of pipeline interlock due to the absence of an instruction even when the instruction branch destination is an instruction misalignment, and is suitable for a processor having a pipeline structure regardless of a CISC processor or a RISC processor. Available to

FIG. 1 is a block diagram illustrating a schematic configuration of a processor according to an embodiment of the present invention. FIG. 3A is a configuration diagram of a control storage 33 in the embodiment. (B) is a diagram showing an operation of the control storage 33 in the embodiment. FIG. 2 is a block diagram illustrating a detailed configuration of a processor in the embodiment. FIG. 4 is an operation timing chart of the processor in the embodiment. FIG. 11 is an operation timing chart of a processor according to the related art. FIG. 9 is a configuration diagram of a control storage according to the related art.

Explanation of reference numerals

REFERENCE SIGNS LIST 10 processor 11 input / output bus 12 bus interface circuit 13 instruction readout circuit 14 decoding / address calculation circuit 15 operation execution circuit 131 instruction buffer 141 control storage 211 to 231 control storage area

Claims (6)

A processor for prefetching instructions,
Fetch address holding means for holding an address of an instruction to be prefetched;
For the control processing relating to the execution of the branch instruction including the processing unit of the branch having the content of rewriting the address of the fetch address holding means and the other processing unit, the execution of the processing unit of the branch is controlled first, Control means for controlling execution of another processing unit, wherein the branch processing unit and the other processing unit are executed in the same pipeline stage. The control processing includes execution control of a subroutine call instruction,
The control means writes the branch destination address obtained based on the operand of the subroutine call instruction to the fetch address holding means in the control of the branch processing unit, and in the other processing unit, stores the return destination address in the area where the return destination address is to be saved. The processor according to claim 1, wherein the processor controls address calculation and saving of a return address. The control processing includes a transition control to an interrupt processing routine,
In the control of the processing unit of the branch, the control unit writes a start address of a predetermined interrupt processing routine into a fetch address holding unit, and calculates an address of an area where a return address is to be saved in another processing unit and calculates a return destination. The processor according to claim 2, wherein the processor controls address saving. The control processing includes a return instruction for instructing return from the subroutine, and a return instruction for instructing return from the interrupt processing routine,
4. The processor according to claim 1, wherein the control unit writes a return address to a fetch address holding unit in controlling the branch processing unit. 5. The control means includes:
A control storage unit that stores a plurality of micro-instructions for realizing the operation of the control process,
A micro-instruction issuing unit for sequentially reading micro-instructions corresponding to each processing unit from the control storage and issuing a control signal designated by the micro-instruction to the inside of the processor;
The microinstruction issuing unit includes:
For a subroutine call instruction, a microinstruction instructing to store the address specified in the instruction in the fetch address holding means, and a microinstruction instructing to calculate the address of the area where the return address is to be saved And a microinstruction for instructing to save the return address, in this order,
For control of transition to the interrupt processing routine, a microinstruction instructing to store a predetermined interrupt processing start address in the fetch address holding means and a microinstruction instructing calculation of an address of an area where a return address is to be saved are provided. The processor according to claim 3, wherein the instruction and the microinstruction for instructing to save the return address are issued in this order. The control means includes:
An address calculation unit for pre-decoding a subroutine call instruction and calculating a branch destination address of the instruction;
A control storage unit that stores a plurality of microinstructions that implements the control processing;
A micro-instruction issuing unit for sequentially reading micro-instructions corresponding to the respective processing units from the control storage, and issuing the micro-instructions inside the processor;
The microinstruction issuing unit includes:
In response to a subroutine call instruction, a microinstruction for storing an address obtained by the address calculation unit in the fetch address holding unit and instructing a store buffer holding data to be stored in a memory to hold a return address. A microinstruction for instructing to update the stack pointer pointing to the save area and to store the updated contents of the stack pointer in the operand address buffer to hold the operand address, and to store the contents of the store buffer in the operand address buffer. Issue a microinstruction instructing to store in the save area pointed to in this order,
For the control of transition to the interrupt processing routine, a microinstruction for storing the start address of the predetermined interrupt processing in the fetch address holding means and for holding the return address in the store buffer, and updating the stack pointer , And a microinstruction instructing to store the updated contents of the stack pointer in the operand address buffer, and a microinstruction instructing to store the contents of the store buffer in the save area pointed to by the operand address buffer. The processor according to claim 3, wherein the processor issues the command.

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