JP2004094239A - Clock converter, clock conversion method, video display and its memory address setting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a one-line memory capable of holding data in horizontal one line period is required and circuit scale becomes large in the case of performing compression/magnification processing of a digital signal in a horizontal direction. <P>SOLUTION: This clock converter is constituted of a memory 107 by which writing and reading are independently operated, a first counter circuit part 10 which controls a writing address, a delay adjustment circuit 103 capable of adjusting delay time of a reading starting reference signal from a writing starting reference signal and a second counter circuit part 11 which controls a reading address from the reading starting reference signal and constituted so that delay adjustment of a writing starting position and a reading starting position is performed while reducing capacity of the memory 107 by writing data within horizontal synchronization period by dividing it into a plurality of times. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a clock conversion device and a clock conversion method used when a digital signal processed by a first clock is converted into a second clock process using a memory, and a video display having the clock conversion device. The present invention relates to an apparatus and a memory address setting method thereof.

In recent years, video signal processing using digital signal processing technology has been frequently used in television receivers in order to realize higher image quality and higher functionality of video signals. Also, when performing digital video signal processing, digital data is transferred between different clocks, or the input video signal is horizontally compressed or enlarged in order to change the image size. In order to realize the above, a clock converter capable of transferring digital data between different types of clocks has been regarded as important.

Regarding the scaling processing of an input video signal, for example, in a “sampling frequency conversion circuit” disclosed in Patent Document 1, a one-line memory capable of operating writing and reading with clocks of different frequencies, and a digital video signal horizontally The processing for scaling in the horizontal direction has been performed by using an interpolation arithmetic circuit for reducing or expanding in the direction.

That is, in this conventional clock converter, when the interpolation coefficient obtained by combining the frequency conversion ratio and the enlargement or reduction ratio is less than “1”, the reduction interpolation processing is first performed using the interpolation coefficient, and then the line memory is stored in the line memory. When the interpolation coefficient written and read, and conversely, the combined interpolation coefficient is “1” or more, the operation of reading from the line memory and then performing the expansion interpolation processing with the interpolation coefficient is performed. The horizontal clock processing and the sampling frequency conversion are performed at the same time by using the post-clock, and the deterioration of the horizontal resolution is reduced in the digital video signal processing that requires the sampling frequency conversion and the horizontal expansion or reduction processing of the image. Can be suppressed.
JP-A-8-223479 (page 4, FIG. 1)

However, the conventional clock converter requires a one-line memory capable of holding data for one horizontal line period when the digital signal is compressed and expanded in the horizontal direction, and has a problem that the circuit scale becomes large.

In addition, the memory size of one line period differs between the broadcasting systems such as NTSC, PAL, and SECAM due to differences in the processing clock frequency and the horizontal frequency. There is a problem that it is necessary to adjust to a large one, and the circuit scale becomes large accordingly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described conventional problems, and requires a memory for one horizontal line when performing horizontal compression / expansion processing or when transferring digital signals between different clocks. It is another object of the present invention to provide a clock conversion device and a clock conversion method that can significantly reduce the required memory size.

Further, the present invention does not require a memory for one horizontal line when a digital signal is transferred between different types of clocks by using the above-described clock converter, and greatly reduces the required memory size. It is an object of the present invention to provide a video display device and a memory address setting method thereof.

In order to achieve this object, a clock converter according to claim 1 of the present invention is a clock converter that converts data synchronized with a first clock into data synchronized with a second clock. A memory having an address smaller than the address required to store the minute data and capable of executing the write operation and the read operation independently of each other by the write clock and the read clock; A first counter circuit section that creates a write address of the memory and a second clock that counts the second clock so that data for the period can be written to the memory in a plurality of times. A read address of the memory is created so that data of a predetermined period written in the memory can be read out. It is obtained by a second counter circuit unit.

According to the configuration, by writing data for a predetermined period such as within a horizontal synchronization period into a memory having a smaller capacity a plurality of times, the write data and the read data of the memory can be reduced while the memory capacity is reduced. The data is converted from the first clock to the second clock without overtaking or overtaking.

A clock converter according to a second aspect of the present invention is a clock converter for converting data synchronized with a first clock to data synchronized with a second clock, wherein an address required to store data for a predetermined period is stored. A memory having a smaller number of addresses and capable of executing a write operation and a read operation independently of each other by a write clock and a read clock, and the input of a write start reference signal indicating a write start reference timing of the memory. A first counter circuit unit for creating a write address of the memory so as to start counting one clock and to write data for a predetermined period into a plurality of times into the memory; The second clock is counted from a read start reference signal indicating a read start reference timing. To allow reading of the data for a predetermined period which is written in the memory a plurality of times, in which a second counter circuit for creating a read address of the memory.

With the above configuration, by writing data for a predetermined period such as within a horizontal synchronization period into a memory having a smaller capacity a plurality of times and using the write start reference signal as a reference timing, the memory capacity can be reduced while the memory is written. The data is converted from the first clock to the second clock without causing the data and the read data to overtake or overtake the data.

A clock converter according to a third aspect of the present invention is a clock converter that converts data synchronized with a first clock into data synchronized with a second clock, and includes an address required for storing data for a predetermined period. A memory having a smaller number of addresses and capable of executing a write operation and a read operation independently of each other by a write clock and a read clock, and the input of a write start reference signal indicating a write start reference timing of the memory. A first counter circuit unit for creating a write address of the memory so as to start counting one clock and to write data for a predetermined period into a plurality of times into the memory; The second clock is counted from a read start reference signal indicating a read start reference timing. A second counter circuit section for creating a read address of the memory so as to enable reading of data for a predetermined period written to the memory in a plurality of times; A delay adjustment circuit that generates a read start reference signal and that can adjust a delay time.

According to the above configuration, the data of different addresses are repeatedly rewritten to the same address for a predetermined period such as within a horizontal synchronization period a plurality of times to reduce the memory capacity and adjust the delay between the write start position and the read start position while reducing the memory capacity. The data is converted from the first clock to the second clock without causing the overwriting or overtaking of the write data and the read data.

A clock converter according to a fourth aspect of the present invention is a clock converter for converting data synchronized with a first clock into data synchronized with a second clock, wherein an address required for storing data for a predetermined period is stored. A memory having a smaller number of addresses and capable of executing a write operation and a read operation independently of each other by a write clock and a read clock, and the input of a write start reference signal indicating a write start reference timing of the memory. 1 count of one clock is started, and increase or decrease is repeated within a predetermined address range of the memory so that data for a predetermined period can be written into the memory in a plurality of times. A first counter circuit for generating a write address, and a read start reference time for the memory; The second clock is counted from a read start reference signal indicating the read operation, and a predetermined address range of the memory is read so as to enable reading of data for a predetermined period written in the memory in a plurality of times. A second counter circuit section for creating a read address of the memory, which repeats an increase or decrease within the delay circuit, and a delay adjustment circuit capable of delaying the write start reference signal and generating the read start reference signal, and adjusting a delay time. It is provided with.

According to the configuration, by writing data for a predetermined period such as a horizontal synchronization period by repeatedly increasing or decreasing the address within a predetermined range of the memory, a plurality of data having different addresses are stored in the same address. Times to repeatedly adjust the delay between the write start position and the read start position while reducing the memory capacity, so that the write data and the read data of the memory do not overtake or overtake the first data. Data is converted from a clock to a second clock.

A clock converter according to a fifth aspect of the present invention is a clock converter that converts data synchronized with a first clock into data synchronized with a second clock, and is required for storing data within a predetermined period. A memory having fewer addresses than the address and capable of performing a write operation and a read operation independently of each other by a write clock and a read clock, and a write start reference signal indicating a write start reference timing of the memory. The count of the first clock is started, and repeatedly increasing or decreasing within a predetermined address range of the memory, so that data for a predetermined period can be written into the memory in a plurality of times. The last increment or decrement for each period increases within a narrower address range than within the predetermined address range. Alternatively, the second clock is counted from a first counter circuit unit for creating a write address of the memory and a read start reference signal indicating a read start reference timing of the memory so as to decrease the number, and divided into a plurality of times. The increase or decrease is repeated within the range of all addresses in the memory so that the data for the predetermined period written in the memory can be read out, and the last increase or decrease in the predetermined period is the predetermined increase or decrease. A second counter circuit for generating a read address of the memory so as to increase or decrease the address within a narrower address range than the address range; and delaying the write start reference signal to generate the read start reference signal And a delay adjustment circuit capable of adjusting the delay time.

According to the configuration, the data for a predetermined period such as the horizontal synchronization period is repeatedly increased or decreased in the address within a predetermined range of the memory, and the last increase or decrease in the predetermined period is performed within the range of the predetermined address. By performing writing so as to increase or decrease within a narrow address range, data of different addresses is repeatedly rewritten to the same address a plurality of times, thereby delaying the write start position and the read start position while reducing the memory capacity. For the adjustment, the data is converted from the first clock to the second clock without causing the write data and the read data of the memory to overtake or overtake the data.

A clock converter according to claim 6 of the present invention is the clock converter according to any one of claims 1 to 5, wherein a multiple of the maximum value of the write address is sampled by the first clock within the predetermined period. The number of write addresses near the sample number of the sampled data is stored in the memory, and the number of read addresses whose multiple of the maximum value of the read address is near the sample number of data sampled at the second clock is determined. It is intended to be used.

According to the configuration, the write start position and the read start position are delayed and adjusted to half of the maximum number of addresses, so that the write data and the read data of the memory do not overtake or overtake the first clock. To the second clock.

A clock converter according to claim 7 of the present invention is the clock converter according to any one of claims 1 to 5, wherein a multiple of the maximum value of the write address is sampled by the first clock within the predetermined period. The data is stored in the memory using a write address near the number of samples of the obtained data, and a read address having a maximum value equal to the maximum value of the write address is used.

According to the configuration, the write start position and the read start position are delayed and adjusted to half of the maximum number of addresses, so that the write data and the read data of the memory do not overtake or overtake the first data. Is converted to the second clock.

In a clock converter according to an eighth aspect of the present invention, in the clock converter according to any one of the first to fifth aspects, the predetermined period is one horizontal synchronization period.

According to the above configuration, the capacity of a memory that requires a capacity corresponding to one horizontal synchronization period is reduced.

A clock converter according to a ninth aspect of the present invention is the clock converter according to any one of the first to fifth aspects, wherein the first counter circuit counts the first clock and performs the write operation. A write address counter for creating an address is compared with a write address output from the write address counter and a settable maximum write value, and when the write address is equal to the maximum write value, the write address counter is reset. And a write maximum value limiter.

According to the configuration, the first counter unit can be realized by a counter having a reset function and a comparison circuit that resets the counter when the count value reaches the upper limit value. It is realized by a circuit configuration.

A clock converter according to a tenth aspect of the present invention is the clock converter according to any one of the first to fifth aspects, wherein the second counter circuit section counts the second clock and performs the read operation. A read address counter for creating an address is compared with a read address output from the read address counter and a settable read maximum value, and when the read address becomes equal to the read maximum value, the read address counter is reset. And a reading maximum value limiter.

According to the above configuration, the second counter circuit section is realized by the same configuration as the first counter circuit section.

A clock conversion method according to claim 11 of the present invention is a clock conversion method for converting data synchronized with a first clock into data synchronized with a second clock, wherein an address required for storing data for a predetermined period is stored. In a memory having a smaller number of addresses and capable of performing a write operation and a read operation independently of each other by a write clock and a read clock, data of a predetermined period is written in a plurality of times. A write address is generated based on a first clock, and a read address is generated based on the second clock so that data for the predetermined period is read out of the memory a plurality of times. It is.

With the above configuration, by writing data for a predetermined period such as a horizontal synchronization period into a memory having a smaller capacity a plurality of times, the write data and the read data of the memory are reduced while the memory capacity is reduced. The data is converted from the first clock to the second clock without overtaking or overtaking.

A video display apparatus according to a twelfth aspect of the present invention includes a first video processing unit that performs a first video processing on a digital video signal based on a first clock, and a video signal output from the first video processing unit. A clock converter for converting the digital video signal from the first clock to a digital video signal synchronized with the second clock; and a digital video signal output from the clock converter based on the second clock. A second video processing unit that performs a second video processing; and a display device that displays a digital video signal output from the second video processing unit. It has less capacity than one horizontal line of the digital video signal output from the video processing unit, and the write operation and the read operation are independent from each other by the write clock and the read clock. And a digital video signal output from the first video processing unit are written to the memory in a plurality of times for each horizontal line, and a digital video signal written in the memory is written in the memory in a plurality of times. A memory control unit that controls the memory so that data can be read for each line.

According to the configuration, in performing the first video processing in synchronization with the first clock and then performing the second video processing in synchronization with the second clock, the second video processing is performed within a predetermined period such as a horizontal synchronization period. By writing the data into the memory having a smaller capacity a plurality of times, the data written in the memory and the read data are not overtaken or overtaken by the first data while reducing the memory capacity. Is converted to the second clock.

A video display device according to a thirteenth aspect of the present invention is the video display device according to the twelfth aspect, wherein the memory control unit receives the first clock signal by inputting a write start reference signal indicating a write start reference timing of the memory. A first counter circuit section for creating a write address of the memory so that data for one horizontal line can be written to the memory in a plurality of times, and a read start of the memory. The second clock is counted from a read start reference signal indicating a reference timing, and the read address of the memory is changed so that data of one horizontal line written to the memory can be read in a plurality of times. And a second counter circuit section to be created.

According to the configuration, in performing the first video processing in synchronization with the first clock and then performing the second video processing in synchronization with the second clock, the second video processing is performed within a predetermined period such as a horizontal synchronization period. By writing the data into the memory with a smaller capacity a plurality of times and writing the write start reference signal as the reference timing, the memory write data and read data are overtaken or overtaken while reducing the memory capacity. The data is converted from the first clock to the second clock without causing the following.

A memory address setting method for a video display device according to claim 14 of the present invention, wherein a first video processing unit that performs a first video processing on a digital video signal based on a first clock; A clock converter for converting the digital video signal output from the processing unit from the first clock to a digital video signal synchronized with the second clock; and a second video converter for converting the digital video signal output from the clock converter to the second video signal. A second video processing unit that performs a second video processing based on the clock of the above, and a display device that displays a digital video signal output from the second video processing unit. Has a smaller number of addresses than the address required to store data for a predetermined period, and the write operation and the read operation are mutually performed by the write clock and the read clock. The first counter circuit unit generates a write address based on the first clock so as to write data for a predetermined period into a plurality of times into a memory that can be executed vertically, A video display device that performs clock conversion by generating a read address based on the second clock so that the data for the predetermined period is read out from the memory in a plurality of times. A determining step of determining a broadcasting method of a digital video signal input to the first video processing unit, and a method of setting a broadcasting method according to the broadcasting method determined by the determining step. A search step for searching for an upper limit or a lower limit of the count value of the first and second counter circuit sections corresponding to the search step, and The upper limit or lower limit of the count value, the first, in which to include a setting step of setting the second counter circuit unit.

According to the above configuration, in performing the second video processing in synchronization with the second clock after performing the first video processing in synchronization with the first clock, the first video processing is performed for a predetermined period such as a horizontal synchronization period. By writing data into a memory having a smaller capacity in a plurality of times, the first and second data can be reduced without causing the data to be overwritten or overtaken while reducing the memory capacity. The operation of converting data from the clock to the second clock is performed according to the broadcasting system. An address suitable for the broadcasting system is automatically determined, and this is set in the first and second counter circuit units.

According to the clock converter according to claim 1 of the present invention, as described above, data for a predetermined period is written into a memory having a smaller capacity than data for a predetermined period in a plurality of times, and the data is written in a plurality of times. Since the separately written data for a predetermined period is read, the first clock can be output while the memory write data and the read data are not overtaken or overtaken while reducing the memory capacity. There is an effect that data can be converted from data to the second clock.

Further, according to the clock converter according to the second aspect of the present invention, as described above, the input of the write start reference signal causes the data for the predetermined period to be stored a plurality of times in the memory having a smaller capacity than the data for the predetermined period. Data is written for a predetermined period, which is written a plurality of times, and is read by inputting a read start reference signal, so that the memory write data and read data can be reduced while reducing the memory capacity. This has the effect that the data can be converted from the first clock to the second clock without causing data overtaking or overtaking.

Further, according to the clock converter according to the third aspect of the present invention, as described above, the input of the write start reference signal causes the memory having a smaller capacity than the data of the predetermined period to transmit the data for the predetermined period a plurality of times. The data is divided into a plurality of times and written for a predetermined period, and the data for a predetermined period is read by the input of the read start reference signal delayed from the write start reference signal, so that the memory capacity can be reduced. There is an effect that the data can be converted from the first clock to the second clock without causing the write data and the read data of the memory to pass or overtake the data.

Further, according to the clock converter according to claim 4 of the present invention, as described above, by inputting the write start reference signal, the address is increased within a predetermined range to a memory having a smaller capacity than data for a predetermined period. Alternatively, the data for a predetermined period is written in a plurality of times by repeating the decrease, and the data for a predetermined period written in a plurality of times is input into a read start reference signal delayed from the write start reference signal. As a result, the address is read by repeatedly increasing or decreasing the address within a predetermined range, so that the memory write data and the read data may overtake or overtake the data while reducing the memory capacity. Thus, there is an effect that data can be converted from the first clock to the second clock.

Further, according to the clock converter according to claim 5 of the present invention, as described above, by inputting the write start reference signal, its address is increased within a predetermined range to a memory having a smaller capacity than data for a predetermined period. Alternatively, repeating the decrease, the last increase or decrease for each predetermined period is performed by increasing or decreasing within a range narrower than the predetermined range, so that the data for the predetermined period is written in a plurality of times, and written in a plurality of times. By inputting the read start reference signal delayed from the write start reference signal, the address is repeatedly increased or decreased within a predetermined range, and the last increase or decrease in the predetermined period is performed. Reduces the memory capacity by performing reading by increasing or decreasing within a narrower range than the specified range While, without the memory write data and read data or cause the overtaken overtaking and data, there is an effect capable of converting data from a first clock to a second clock.

Further, according to the clock converter according to claim 6 of the present invention, as described above, the multiple of the maximum value of the write address is close to the number of samples of the data sampled by the first clock within the predetermined period. The memory is stored in the memory using a write address which becomes a read address whose multiple of the maximum value of the read address is close to the number of samples of the data sampled by the second clock. The read start position and the read start position are adjusted to a delay of half the maximum number of addresses, so that the write data and read data of the memory can be shifted from the first clock to the second clock without overtaking or overtaking data. There is an effect that can be converted.

Further, according to the clock converter according to claim 7 of the present invention, as described above, the multiple of the maximum value of the write address is close to the number of samples of the data sampled by the first clock within the predetermined period. The memory is stored in the memory using a write address that is equal to the maximum address of the write address, and the read address having the same maximum value is used, so that the write start position and the read start position are adjusted to half the maximum number of addresses. Therefore, there is an effect that the data can be converted from the first clock to the second clock without causing the write data and the read data of the memory to pass or overtake the data.

According to the clock converter according to claim 8 of the present invention, in the clock converter according to any one of claims 1 to 5, the predetermined period is one horizontal synchronization period. This has the effect of reducing the capacity of a memory that requires a capacity corresponding to.

Further, according to the clock conversion device of the ninth aspect of the present invention, the first counter circuit section counts the first clock and creates the write address, and the write address counter. Since the write address output by the counter is compared with the settable maximum write value, and when the write address and the maximum write value are equal, the write address counter has a write maximum value limiter that resets the write address counter. Since the first counter unit can be realized by a counter with a reset function and a comparison circuit that resets the counter when the count value reaches an upper limit value, the first counter unit can be realized with a small circuit configuration. There is.

According to a clock converter according to claim 10 of the present invention, in the clock converter according to any one of claims 1 to 5, the second counter circuit section counts the second clock. Since the read address of the memory is created so that the data for a predetermined period written in the memory can be read out a plurality of times, the second counter circuit unit is provided with the first counter circuit unit. There is an effect that can be realized with the same configuration as the counter circuit section of FIG.

According to a clock conversion method according to claim 11 of the present invention, a clock conversion method for converting data synchronized with a first clock into data synchronized with a second clock as described above, The data for a predetermined period is written into a memory having a smaller capacity than the address required to store the data in the memory in a plurality of times, and the data in the predetermined period is read from the memory in a plurality of times. Therefore, there is an effect that the data can be converted from the first clock to the second clock without reducing the memory capacity and without causing data overtaking or overtaking of the write data and the read data of the memory. .

According to the video display device of the present invention, when the output of the first video processing unit is input to the second video processing unit via the clock conversion unit as described above, A memory having a capacity smaller than one horizontal line of the digital video signal is used as a memory of the conversion unit, and the digital video signal is written into the memory in a plurality of times for each horizontal line, and is written in the memory in a plurality of times. Since the data is read out for each horizontal line, after the first video processing is completed, when the second clock is switched from the first clock to the second clock for the second video processing, the memory is used. The capacity can be reduced, and the data written from the first clock to the second clock can be transferred without causing the write data and the read data of the memory to overtake or overtake the data. There is an effect that it is not in place.

According to the video display device of the present invention, as described above, the memory control unit of the clock conversion unit writes the digital video signal into the memory a plurality of times for each horizontal line. Since one counter circuit unit and a second counter circuit unit that reads data of each horizontal line written into the memory in a plurality of times are provided, after the first video processing is completed. In switching the second clock from the first clock for the second video processing, the memory capacity can be reduced by controlling the address of the counter circuit unit, and the write data and the read data of the memory can pass the data. There is an effect that data can be switched from the first clock to the second clock without causing overtaking or overtaking.

According to the memory address setting method for a video display device according to claim 14 of the present invention, the digital video signal input to the counter circuit of the video display device configured in the same manner as in claim 13 of the present invention And the upper or lower limit of the count value of the first and second counter circuits corresponding to the determined broadcast system is searched, and the upper or lower limit of the searched count value is set. Therefore, after the first video processing is completed, the memory capacity can be reduced without changing the circuit configuration when switching from the first clock to the second clock for the second video processing, The transfer of the data from the first clock to the second clock is different without the data being overwritten or overtaken between the write data and the read data of the memory. Even when displaying a video signal of a broadcast system that has an effect made possible.

Embodiment 1 FIG.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of the clock converter according to the present embodiment. In FIG. 1, reference numeral 101 denotes a write address counter for write address control, which starts counting up a first clock (write clock) S109 in response to a horizontal synchronization pulse signal (write start reference signal) S101, and sets the count value as the count value. The write address S102 of the memory 107 is output, reset once by the next horizontal synchronization pulse signal S101, and the next up-count starts. Reference numeral 102 denotes a write maximum value limiter (a maximum value limiter circuit) for a write address. When the write address S102 becomes equal to the value set by the maximum value control signal S112, the write address counter 101 is reset by a write address reset signal S103. . Reference numeral 10 denotes a first counter circuit unit including the write address counter 101 and the maximum write value limiter 102, counts the first clock S109, and outputs one horizontal cycle (predetermined period), that is, data for one horizontal synchronization period. A write address S102 of the memory 107 is created so that writing to the memory 107 can be performed a plurality of times. The write address S102 is, as shown in FIG. 7, repeated up-counting within a predetermined range of the address of the memory 107, or, as shown in FIG. 4 to FIG. 6, FIG. For the count, an address is created so as to perform up-counting within a range narrower than a predetermined address.

A delay adjustment circuit 103 generates a read reference pulse (read start reference signal) S104 by delaying the horizontal synchronization pulse S101 according to the value of the delay difference signal S113, and 104 denotes a read address counter (counter circuit) for controlling read addresses. ), The count-up of the second clock (read clock) S110 is started by the read reference pulse S104 from the delay adjustment circuit 103, and the read address S105 of the memory 107 is output as the count value, and the next read reference Once reset by the pulse S104, the next up-counting is started. Reference numeral 105 denotes a read maximum value limiter (maximum value limiter circuit) for the read address. When the read address S105 becomes equal to the set value by the maximum value control signal S112, the read address counter 104 is reset by the read address reset signal S106. . Reference numeral 11 denotes a second counter circuit section including the read address counter 104 and the read maximum value limiter 105, which counts the second clock S110 and divides data for one horizontal cycle (predetermined period) into a plurality of times. A read address S105 of the memory 107 is created so as to enable reading from the memory 107. This read address S105 repeats up-counting within a predetermined range of the address of the memory 107 as shown in FIG. 7, or as shown in FIG. 4 to FIG. 6 or FIG. For the count, an address is created so as to perform up-counting within a range narrower than a predetermined address.

Reference numeral 106 denotes an interpolation circuit for generating interpolation data of the input video signal S107, and reference numeral 107 denotes a memory that can separately control writing and reading, and stores a video signal for one horizontal synchronization period (data for a predetermined period). Has an address smaller than the address necessary for the input, receives the interpolated video signal S108 as an input, and outputs an output signal S111.

FIG. 2 is a block diagram showing a configuration of the first counter unit 10 and the second counter unit 11 of FIG. In FIG. 2A, 101a and 104a are selectors, 101b and 104b are flip-flops that delay the outputs of the selectors 101a and 104a by one clock period of the first and second clocks S109 and S110, and 101c and 104c are flip-flops. This is an adder for adding a value "1" to the outputs of 101b and 104b, and these selectors 101a and 104a, flip-flops 101b and 104b, and adders 101c and 104c constitute a write address counter 101 and a read address counter 104, respectively. .

Also, 102a and 105a are decoders for decoding the outputs of the T flip-flops 101b and 104b, 102b and 105b are initial value generating circuits for generating initial count values to be set in the counters 101a and 104a, and 101d is for horizontal synchronization with the output of the decoder 102a. An OR circuit 104 outputs an OR of the pulse S101 to the control input of the selector 101a, and an OR circuit 104d outputs an OR of the output of the decoder 105a and the read reference pulse S104 to the control input of the selector 104a. , 104a, decoders 102a and 105a, initial value generation circuits 102b and 105b, and OR circuits 101d and 104d constitute a maximum write value limiter 102 and a maximum read value limiter 105, respectively.

FIG. 2 (b) shows a case where the decoder of FIG. 2 (a) is configured by a comparator, and shows a case of a 4-bit configuration as an example. In FIG. 2B, reference numerals 1021, 1022, 1023, and 1024 denote exclusive OR circuits having the same weighted bit outputs of the limit value generating circuit 1026 and the flip-flop 101b as inputs, and reference numeral 1025 denotes an exclusive OR circuit 1021, NOR circuits to which the outputs of 1022, 1023, and 1024 are input; 1051, 1052, 1053, and 1054 are exclusive OR circuits that have the same weighted bit outputs of the limit value generation circuit 1056 and the flip-flop 104b as inputs; This is a NOR circuit to which the outputs of the exclusive OR circuits 1051, 1052, 1053, and 1054 are input.

FIG. 3 is a block diagram showing a configuration of the delay adjustment circuit of FIG. In FIG. 3, 103a is a delay adjustment counter for counting the horizontal synchronization pulse S101, and 103b is a delay adjustment decoder for decoding the count value of the delay adjustment counter 103a.

The operation of the clock converter configured as described above will be described below.
In FIG. 1, S101 is a horizontal synchronization pulse signal, which is a reference pulse (write start reference signal) for determining a start position of a write address. When the horizontal synchronizing pulse signal S101 is input, the write address counter 101 is reset to the initial address value "0", and the output, the write address S102, is updated to this value "0". Each time S109 is input, the write address S102 counts up. If the first clock S109 is set to have a higher frequency than the second clock S110, the interpolation circuit 106 writes the sampling points into the memory 107 while thinning the sampling points. The write address counter 101 stops counting up so that data is not written to the memory 107.

As described above, the write address counter 101 counts the horizontal synchronization pulse signal S101 and outputs the write address S102. However, the write maximum value limiter 102 determines the write address S102 and the write address maximum value defined by the maximum value control signal S112. Are compared, and when they have the same value, a write address reset signal S103 is output, and the write address reset signal S103 causes the write address counter 101 to reset to an initial address value "0".

S109 is a first clock which is a clock on the writing side of the memory 107. The input video signal S107 processed by the first clock S109 is subjected to the interpolation circuit 106 to reduce the number of samplings or to perform an enlargement process. The video signal S108 interpolated by the interpolation circuit 106 is written to the specified address of the memory 107 by the first clock S109 and the write address S102.

On the other hand, the horizontal synchronization pulse S101 is input to the delay adjustment circuit 103, and the delay adjustment circuit 103 uses the horizontal synchronization pulse S101 as a reference and has a read reference having a delay amount based on the delay difference signal S113 determined by a delay difference setting register (not shown). The pulse S104 is output, and the start position of the read address is determined. When the read reference pulse S104 is input, the read address counter 104 is reset to the initial address value “0”, the output read address S105 is updated to this value “0”, and the second clock S110 is output. Every time is input, the read address S105 counts up. The read maximum value limiter 105 compares the read address S105 with the address maximum value specified by the maximum value control signal S112, and outputs a read address reset signal S106 when they become the same value. In S106, the read address counter 104 performs reset processing to the initial address value "0".

S110 is a second clock which is a clock on the read side of the memory 107. The signal written in the memory 107 is read as an output signal S111 in accordance with the read address S105 every time the second clock S110 is generated. Thus, the input signal processed by the first clock S109 can be converted to the second clock S110, and an output signal can be obtained.

Hereinafter, the operation of the first counter unit 10 and the second counter unit 11 will be described.
In FIG. 2A, when the values of the horizontal synchronizing pulse S101 and the read reference pulse S104 first become "L", the selectors 101a and 104a select the initial values output by the initial value generating circuits 102b and 105b. The outputs of 101a and 104a are delayed by one clock by flip-flops 101b and 104b and fed back to adders 101c and 104c. The fed-back values are added to "1" of the power supply voltage level by adders 101c and 104c. The sum is output to the selectors 101a and 104a. At this time, since the values of the horizontal synchronizing pulse S101 and the read reference pulse S104 have just changed to “H”, the selectors 101a and 104a select an added value, and the added value is output to the flip-flops 101b and 104b. . By repeating this cycle every clock, the counters 101a and 104a increase the count value by "1" every clock.

The count value is also supplied to the decoders 102a and 105a, and the decoders 102a and 105a decode the count value. If the decoded result matches a value set in advance, the write address reset signal S103, The read address reset signal S106 is output, and the selectors 101a and 104a select the outputs of the initial value generation circuits 102b and 105b via the OR circuits 101d and 104d. As a result, the count values of the counters 101 and 104 are temporarily reset, and the above operation is repeated until the values of the horizontal synchronization pulse S101 and the read reference pulse S104 become "L". As a result, the count values of the counters 101a and 104a repeat the saw-toothed up-counting as shown in FIG.

When the decoders 102a and 105a have a 4-bit configuration, they may have a configuration as shown in FIG. 2B. The outputs of the flip-flops 101b and 104b and the outputs of the reset value generation circuits 1026 and 1056 are exclusive OR circuits. Bits 1021 to 1024 and 1051 to 1054 compare the bits, and if they match, the NOR circuits 1025 and 1055 output reset signals S103 and S106 of “H”.

FIG. 4 shows a case where a standard signal is input in the NTSC system, and a sampling frequency that is four times the color subcarrier frequency of 3.58 MHz is used as both the first clock S109 and the second clock S110. 5 shows the relationship between the horizontal sampling point and the write address and read address of the memory when there is no memory, and shows, as an example, the case where a memory with no thinning in the horizontal direction and the number of addresses is "256" is used. . The horizontal axis indicates the horizontal sampling point, and indicates that the address value increases by "1" each time the horizontal sampling number increases by one, and returns to the initial address value "0" when the address exceeds the maximum number. I have. In this case, the write address is stored in the memory 107 using a write address in which a multiple of the maximum value “255” of the write address is close to the sample number “910” of the data sampled by the first clock within the horizontal period, and the read address is stored. As the maximum value, a value equal to the maximum value of the write address is used.

FIG. 5 shows a case where a standard signal is input in the NTSC system, a sampling frequency that is four times the color subcarrier frequency of 3.58 MHz is used for both the first clock S109 and the second clock S110, and the thinning process in the horizontal direction is performed. It shows the relationship between the horizontal sampling point and the write address and the read address of the memory when there is no data, and shows the relationship between the horizontal sampling point and the write address and the read address of the memory when limiter processing is applied in the write and read control of the memory. , And the case where the number of addresses is “256” is shown as an example. The horizontal axis indicates the horizontal sampling point, and indicates that the address value increases by "1" each time the horizontal sampling number increases by one, and returns to the initial address value "0" when the address exceeds the maximum number. I have.

In this case, the write address is stored in the memory 107 using a write address in which a multiple of the maximum value “227” of the write address is near the sample number “910” of the data sampled by the first clock within the horizontal period, and the read address is stored. As the maximum value, a value equal to the maximum value of the write address is used.

In FIG. 4, when the horizontal synchronization pulse S101 is input, the write address S102 is initially reset to an address value “0”, and the write address S102 is counted up every first clock. In the NTSC broadcast, the memory size in one line period is 910 addresses. Therefore, when the maximum value of the maximum value control signal S112 is set to "255", the address value returns to "0" when the maximum value exceeds "255". Once the write maximum value limiter 102 is set in this way, the write address counter 101 repeats such an operation a plurality of times for each one line period. That is, in the example of FIG. 4, the up-counting from the address value “0” to the maximum value “255” is repeated three times from the initial reset until the next horizontal synchronization pulse S101 is input. Then, the line end value of the write address S112 is interrupted at "141". This is because the count of the horizontal sampling point reaches 910 in the course of the fourth up-counting, and at the time when the count of 910 is counted, the write address counter 102 is reset by the next horizontal synchronization pulse S101. This is because the point of time corresponds to “141” in the fourth up-count (910 = 256 × 3 + 142).

On the other hand, the read address S105 is also counted up in the same manner as the write address S102. However, the start position of the read address S105 is, for example, a value “71” which is a half of the line end value of the write address is sent to the delay adjustment circuit 103 by the delay control signal S113. Set as As a result, the read address S105 is counted up by "72" horizontal sampling points later than the write address S102. For this reason, for example, even if the horizontal synchronization pulse is disturbed and a shift of 71 clocks occurs on the left and right when reproducing a video tape recorder which is a non-standard signal of the NTSC system, when reading out the write data of the memory, A standard signal can be configured without overtaking or overtaking.

At that time, by configuring the delay adjustment circuit 103 as shown in FIG. 3, the read reference pulse S104 can be output at a timing delayed by a required delay amount from the horizontal synchronization pulse S101. That is, when a single horizontal synchronization pulse S101 is input, the delay adjustment counter 103a counts up by itself using this as a trigger, and the count value is output to the delay control signal S113 set in the delay adjustment decoder 103b. , The readout reference pulse S104 is output, and the delay adjustment counter 103a is thereby reset. Here, by changing the set value of the delay adjustment decoder 103b, the read reference pulse S104 can be output at a timing delayed by a desired delay amount from the horizontal synchronization pulse S101.

On the other hand, in FIG. 5, when the horizontal synchronization pulse S101 is input, the write address S102 is initially reset to an address value “0”, the write address S102 is counted up at every first clock, and the maximum value of the write address S112 is set. Is set to “227”, the repetition of returning the address value to “0” when the maximum value exceeds “227” is repeated three times until the next horizontal synchronization pulse S101 is input. The last line value of the write address S112 from the input of S101 to the reset is “225” (910 = 228 × 3 + 226). The start position of the read address S105 is determined by the delay control signal S113, for example, by setting a half value “112” of the line end value of the write address as the delay difference, thereby reproducing a non-standard NTSC video tape recorder. Even if the horizontal synchronization pulse is disturbed and a clock shift of 112 clocks occurs on the left and right, a standard signal can be configured without data overtaking or overtaking when reading write data in the memory.

Here, by setting the maximum value control signal S112 such that the integral multiple of the maximum memory address value is close to the specified horizontal sampling number in the standard signal state, that is, as shown in FIG. Instead of setting the value “141” of the maximum value of the write address at the time of writing to be significantly different from the majority of the value “255”, as shown in FIG. Are set to "227" and "225", which are almost the same value, so that a signal in a non-standard state is input, and even if the horizontal synchronization pulse is disturbed, data overtaking and overtaking occur. The range not to be used can be greatly expanded as compared with the case of FIG.

FIG. 6 shows a case where a standard signal is input in the PAL system, a sampling frequency that is four times the color subcarrier frequency 4.43 MHz is used as both the first clock S109 and the second clock S110, and there is no horizontal thinning processing. It shows the relationship between the horizontal sampling point and the write address and read address of the memory in this case, and shows, as an example, the case where there is no thinning in the horizontal direction and a memory having the number of addresses of "256" is used. The horizontal axis indicates the horizontal sampling point, and indicates that the address value increases by "1" each time the horizontal sampling number increases by one, and returns to the initial address value "0" when the address exceeds the maximum number. I have.

FIG. 7 shows a case where a standard signal is input in PAL broadcasting, a sampling frequency four times the color subcarrier frequency 4.43 MHz is used as the first clock S109 and the second clock S110, and there is no horizontal thinning processing. It shows the relationship between the horizontal sampling point of the memory and the write address and read address of the memory, and shows the relationship between the horizontal sampling point and the write address and the read address of the memory when limiter processing is applied in the write and read control of the memory. , The number of addresses is "256". The horizontal axis indicates the horizontal sampling point, and indicates that the address value increases by "1" each time the horizontal sampling number increases by one, and returns to the initial address value "0" when the address exceeds the maximum number. I have.

In FIG. 6, when the horizontal synchronization pulse S101 is input, the write address S102 is initially reset to an address value “0”, and the write address S102 is counted up every first clock. In PAL broadcasting, since the memory size in one line period is 1135 addresses, if the maximum value of the maximum value control signal S112 is set to "255", the address value returns to "0" repeatedly when the maximum value exceeds 255. The process is repeated four times until the next horizontal synchronization pulse S101 is input, and the final line value of the write address S112 until the next horizontal synchronization pulse S101 is input and reset is “110” (1135 = 256 × 4 + 111). The start position of the read address S105 is, for example, a video tape recorder, which is a non-standard signal of the PAL system, reproduced by setting, for example, a half value “55” of the line end value of the write address as a delay difference by the delay control signal S113. In this case, even if the horizontal synchronizing pulse is disturbed and a shift of 55 clocks occurs on the left and right sides, when reading out the write data of the memory, it is possible to configure a circuit that does not overtake the data and does not cause overtaking.

In FIG. 7, when the horizontal synchronization pulse S101 is input, the write address S102 is initially reset to an address value “0”, the write address S102 is counted up every first clock, and the maximum value of the write address S112 is changed to “ When it is set to "226", the repetition of returning the address value to "0" when it exceeds the maximum value "226" is repeated four times until the next horizontal synchronization pulse S101 is input. The last line value of the write address S112 from the input to the reset is “226” (1135 = 227 × 5). The start position of the read address S105 is determined by the delay control signal S113, for example, by setting a half value “113” of the write address line final value as a delay difference, thereby reproducing a video tape recorder which is a non-standard signal of the PAL system. Even if the horizontal synchronizing pulse is disturbed and a shift of 113 clocks occurs on the left and right sides, when reading out the write data of the memory, the data can be passed without overtaking or overtaking. Here, by setting the maximum value control signal S112 so that the integral multiple of the maximum memory address value is close to the specified horizontal sampling number in the standard signal state, a signal in a non-standard state is input, and the horizontal synchronization pulse is generated. Even if disturbed, data can be overtaken, and the range in which overtaking does not occur can be greatly expanded.

FIG. 8 shows a case where the maximum number of memory addresses is constituted by "128" and the maximum value of the write address S112 is set to "113". In the NTSC system, a standard signal is inputted, and the first clock S109 and the first clock S109 are inputted. 2 shows a relationship between a horizontal sampling point and a write address and a read address of a memory when there is no thinning process in the horizontal direction, using a sampling frequency four times the color subcarrier frequency of 3.58 MHz as the second clock S110. 4 shows the relationship between the horizontal sampling point and the write address and read address of the memory when a limiter process is added in the writing and reading control of the memory. The horizontal axis indicates the horizontal sampling point, and indicates that the address value increases by "1" each time the horizontal sampling number increases by one, and returns to the initial address value "0" when the address exceeds the maximum number. I have.

In FIG. 8, when the horizontal synchronization pulse S101 is input, the write address S102 is initially reset to an address value “0”, and the write address S102 is counted up every first clock. When the maximum value of the maximum value control signal S112 is set to “113”, the repetition of returning to “0” when the address value exceeds the maximum value 113 is repeated seven times until the next horizontal synchronization pulse S101 is input. The final line value of the write address S112 until the next horizontal synchronization pulse S101 is input and reset is "111" (910 = 114 * 7 + 112). The start position of the read address S105 is determined by setting the delay control signal S113 to a value "56", which is half the line end value of the write address, as a delay difference, for example, when a video tape recorder which is a non-standard signal of the NTSC system is reproduced. When the horizontal synchronization pulse is disturbed and the write data in the memory is read up to the occurrence of a shift of up to 56 clocks to the left and right, a standard signal can be formed without data overtaking or overtaking. Here, by setting the maximum value control signal S112 so that the integral multiple of the maximum memory address value is close to the specified horizontal sampling number in the standard signal state, a signal in a non-standard state is input, and the horizontal synchronization pulse is generated. Even if disturbed, data can be overtaken, and the range in which overtaking does not occur can be greatly expanded.

As described above, according to the clock conversion device of the first embodiment, when converting the signal processed by the first clock to the second clock, the address of the memory that stores the video signal for one horizontal line period By greatly reducing the number, writing and reading the video signal for one horizontal line period a plurality of times, the memory capacity can be reduced, and not only for one broadcasting system, but also for multiple broadcasting systems , The circuit scale can be reduced. In addition, by setting the integral multiple of the maximum value of the memory address to be close to the value of the number of samples in the horizontal period, a non-standard signal such as when a video tape recorder is reproduced is input and the horizontal synchronization pulse is disturbed. Even in this case, the written data can be overtaken and read from the memory without being overtaken.

In the example of the above embodiment, the first clock and the second clock are described using the same frequency. However, different clocks having different frequencies may be used.
FIG. 9 shows a case where different clocks are used and the maximum number of memory addresses is "227". A standard signal is input in the NTSC system, and the color subcarrier frequency 3 is used as the first clock S109. A sampling frequency (= 14.3 MHz) that is four times as high as .58 MHz is used, and a sampling frequency (= 13.5 MHz) that is four times the color subcarrier frequency 3.38 MHz is used as the second clock S110. 5 shows the relationship between the horizontal sampling points and the write address and read address of the memory when no thinning processing is performed. By setting the horizontal sampling points of 114 × 858/910 = 107 as the delay adjustment, FIG. As in the case of, for example, when a video tape recorder which is a non-standard signal of the NTSC system is reproduced, When reading the horizontal sync memory write data on the left and right pulse is disturbed to a maximum 107 clock drift occurs, passing data, overtaken can constitute a standard signal without generating. Here, 910 and 858 are the number of horizontal sampling points defined in IEEE ITU656 when the sampling frequency is 14.3 MHz and 13.5 MHz, respectively, and 114 is a half value of the maximum memory address number “227”. Note that the first clock and the second clock are not limited to the above example, and the second clock may have a higher frequency than the first clock. Also, the maximum number of memory addresses is not limited to “227”.

In addition, by writing data having a larger capacity than the memory into a plurality of times in a memory in which writing and reading can be independently performed based on different clocks, and performing reading in a plurality of times. Any hardware configuration may be used as long as the method of reading data is executed.

Further, in the first embodiment, the maximum value of the write address and the maximum value of the read address of the memory are set to be the same value. However, they may be different values, except that the resolution changes. The same effects as those of the first embodiment can be obtained.

Embodiment 2 FIG.
FIG. 10 is a block diagram showing a configuration of a television receiver including a video display device having the clock conversion device according to the first embodiment. In FIG. 10, reference numeral 501 denotes a tuner connected to a terrestrial analog broadcast antenna 530, 502 denotes a digital broadcast decoder for decoding a digital broadcast signal such as an RF input input from a digital broadcast input 533, and 503 denotes a digital broadcast decoder from the tuner 501. A selector 504 for selecting a video demodulation signal, a VCR from the external video input 531, a reproduction video signal from a DVD player or the like, and a digital video signal decoded by the digital broadcast decoder 502. A selector 520 for selecting a reproduced audio signal from a VCR or a DVD player, or a digital audio signal decoded by the digital broadcast decoder 502, processes the video signal selected by the selector 503, and displays it on a monitor (display device) 510. Video display device 511 processes the audio signal selected by the selector 504, an audio processing unit for outputting to the speaker 512.

Further, in the video display device 520, a first video processing unit 505 processes a digital video signal obtained by inputting an output of the selector 503 to an A / D conversion unit (not shown) in synchronization with a first clock. 505a is an internal selector, 505b is a crystal oscillator that supplies a clock to the first video processing unit 505, 506 is a memory that stores the output of the first video processing unit 505, 508 Is a memory control unit that controls the memory 506 according to settings made by the microcomputer 509, and 507 is a second video processing unit that processes the output of the first video processing unit 505 obtained via the memory 506 in synchronization with the second clock. 507a is a PLL that generates a second clock. A clock conversion unit 550 includes a memory 506, a memory control unit 508, and a microcomputer 509, and corresponds to the clock conversion device according to the first embodiment. The memory control unit 508 includes the first counter circuit unit 10 in FIG. The microcomputer 509 sets the upper limit value of the count to the limit value generation circuits (registers) 1026 and 1056 in FIG. 2 by the maximum value control signal S112 in FIG. Then, the delay amount is set for the delay adjustment circuit 103 in FIG. 1 by the delay difference signal S113. The tuner 501 outputs the horizontal synchronization pulse S101 to the first counter circuit unit 10 and the second counter circuit unit 11 of FIG. 1 directly and via the delay adjustment circuit 103.

Note that the video display device 520 may be constituted by one semiconductor integrated circuit, and the microcomputer 509 and the memory 506 may be mounted inside or connected externally. Further, the microcomputer 509 may be a tuning microcomputer for tuning.

Next, the operation will be described.
First, the selectors 503 and 504 select whether to receive a terrestrial analog broadcast, to play package media such as a VCR (Video Casette Recorder) or a DVD (Digital Versatile Disk), or to receive a digital broadcast. First, it is assumed that reception of terrestrial analog broadcast has been selected. In the terrestrial analog TV broadcast received by the antenna 530, a desired channel is selected by the tuner 501, and an analog combo-video signal and an audio demodulated signal as demodulated outputs are displayed on the video via selectors 503 and 504, respectively. It is input to the device 520 and the audio processing unit 511.

The analog combo video signal input to the video display device 520 is converted into a digital signal by an A / D conversion unit (not shown) and output to the first video processing unit 505. The first video processing unit 505 Video signal processing such as Y / C separation and color demodulation is performed based on a first clock having a frequency corresponding to a broadcasting system such as NTSC or PAL. The Y signal and the color difference signal after the video signal processing are output via the selector 505a in the first video processing unit 505, and the output video signal is input to the memory 506 so as to be replaced with the second clock. You. The video signal replaced by the second clock in the memory 506 is displayed by the second video processing unit 507, that is, image quality improvement processing such as changing the gain of contrast and brightness, and synchronization of the video signal with the clock. And conversion into RGB signals are performed in synchronization with the second clock. The first clock obtained from the crystal oscillator 505b is synchronized with a burst signal called, for example, a burst lock clock and the like, and its frequency is determined according to the broadcasting system, whereas the second clock obtained from the PLL circuit 507a is used. Is synchronized with a horizontal frequency called a horizontal line lock clock or the like, and the frequency is determined according to the screen size of the monitor 510. The video of the RGB signal output from the second video processing unit 507 is displayed on the monitor 510.

On the other hand, the audio demodulation signal from the tuner 501 selected by the selector 504 is subjected to audio signal processing by the audio processing unit 511, and the audio is output from the speaker 512.

(4) By selecting the external video input 531 and the external audio input 532 by the selectors 503 and 504, it is possible to select a reproduced analog signal from a VCR, a DVD, or the like connected thereto. The operation in this case is the same as when the tuner 501 is selected.

On the other hand, when the output of the digital broadcast decoder 502 is selected, the digital video output is already separated into the Y signal and the color difference signal at the time when the digital video decoder 502 outputs the digital video output. At 505, almost no processing is performed, the data passes through the inside, and is output to the memory 506 via the selector 505 a in the first video processing unit 505.

By the way, the memory 506 corresponds to the memory 107 in FIG. 1. The video signal for one horizontal period is written and read in a plurality of times under the control of the memory control unit 508 to reduce the capacity of the memory 506. It can be reduced from one horizontal period.

The memory control unit 508 is composed of the first counter circuit unit 10, the second counter circuit unit 11, and the delay adjustment circuit 103 in FIG. 1, and according to the broadcasting system, the maximum write value limiter 102 and the maximum read value The limiter value of the limiter 105 is set by a microcomputer 509 such as a channel selection microcomputer. Note that the interpolation circuit 106 in FIG. 1 is included in the first video processing unit 505.

FIG. 11 shows a processing flow of the microcomputer 509. In step S1 (determination step), the broadcast system of the digital video signal input to the first video processing unit 505 is determined by determining the broadcast system of the received TV signal. Determine the method. For this determination, for example, it is determined whether the frequency of the vertical synchronization signal is 50 Hz or 60 Hz and whether the PAL system or the NTSC system is used, and by detecting the frequency of the horizontal synchronization signal, a plurality of processes such as sub-classifying the PAL system or the NTSC system are performed. Do this by: The determination of these frequencies is performed by inputting the output of a synchronization signal (not shown) output from the tuner 501 to the microcomputer 509. Next, in step S2 (search step), a table showing limit values (upper limit of count value) calculated in advance for each broadcasting system is searched, and in step S3 (setting step), the searched limiter values are searched. Are set in registers 10 and 11 of the first and second counter circuit units, that is, limit value generating circuits 1026 and 1056 of decoders 102a and 105a.

This limiter value may be set once unless the broadcast system is changed, whereby the memory control unit 508 sequentially generates addresses as shown in FIG. 9, for example, and stores data of one horizontal line in a smaller capacity. The n-th reading is started when the n-th writing (n is an integer of 1 or more) is half completed, and the (n + 1) -th data overwriting is performed on the same memory. Since the n-th read operation is completed at the time of performing the half operation, the data is switched from the first clock to the second clock by utilizing a small memory capacity without causing data overtaking or overtaking. It can be performed.

Thereby, even when receiving TV broadcasts of various broadcast systems, when changing the video signal from the first clock to the second clock, the capacity of the memory used for the change is changed to one horizontal period. Less than a minute.

As described above, according to the television receiver of the second embodiment, when the video signal is switched from the first clock to the second clock in the video display device such as the television receiver, the switching is performed. Can reduce the capacity of the memory used for one horizontal period, reduce the circuit scale and circuit area, reduce power consumption, etc., and change the limiter value written to the register by the microcomputer. Thus, even when receiving a TV broadcast of a different broadcast system, the above advantages can be enjoyed without changing the circuit configuration.

In the second embodiment, the microcomputer changes the limiter value to be written into the register, but this may be manually set.

Further, in the second embodiment, a television receiver for digital terrestrial analog broadcasting has been described as an example. However, a television receiver dedicated to terrestrial analog broadcasting or dedicated to digital broadcasting may be used. Furthermore, a video display device as a display for displaying various video sources input from the outside may be used.

Further, the switching from the first clock to the second clock may be performed to realize a so-called picture-in-picture.

In the first and second embodiments, the case where the first and second counter circuit units perform up-counting has been described, but this may be performed by down-counting.

Data for a predetermined period, such as one horizontal period, can be written to a memory having a smaller capacity, and is suitable for reducing the circuit scale in a video display device or the like when a data clock is switched. ing.

FIG. 1 is a block diagram illustrating a configuration of a clock conversion device according to a first embodiment of the present invention. FIG. 2A is a block diagram illustrating an internal configuration of first and second counter circuit units of the clock converter according to the first embodiment of the present invention. FIG. 2A illustrates a write address counter, a read address counter, and a write maximum value. FIG. 2B is a block diagram showing an internal configuration of a value limiter and a read maximum value limiter, and FIG. 2B is a block diagram showing an internal configuration of a decoder of a write maximum value limiter and a read maximum value limiter. FIG. 2 is a block diagram showing an internal configuration of a delay adjustment circuit of the clock conversion device according to the first embodiment of the present invention. FIG. 4 is a diagram showing write / read addresses when the clock converter according to the first embodiment of the present invention uses an NTSC 256 address memory. FIG. 4 is a diagram showing write / read addresses when the clock converter according to the first embodiment of the present invention uses an NTSC 256 address memory. FIG. 4 is a diagram showing write and read addresses when the PAL 256-address memory is used in the clock converter according to the first embodiment of the present invention. FIG. 4 is a diagram showing write and read addresses when the PAL 256-address memory is used in the clock converter according to the first embodiment of the present invention. FIG. 6 is a diagram showing write / read addresses when the clock converter according to the first embodiment of the present invention uses an NTSC 128 address memory. FIG. 4 is a diagram showing write / read addresses when the frequency of the first clock and the second clock are different when using the NTSC 256 address memory of the clock converter according to the first embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a television receiver having a video display device according to Embodiment 2 of the present invention. FIG. 9 is a flowchart illustrating a control operation of a microcomputer of the video display device according to the second embodiment of the present invention.

Explanation of reference numerals

Reference Signs List 10 first counter circuit section 11 second counter circuit section 101 write address counter 102 maximum write value limiter 103 delay adjustment circuit 104 read address counter 101a, 104a selector 101b, 104b flip-flop 101c, 104c adder 101d, 104d OR circuit 102a, 105a Decoders 102b, 105b Initial value generation circuits 1021 to 1024, 1051 to 1054 Exclusive OR circuits 1024, 1055 NOR circuit 103a Delay adjustment counter 103b Delay adjustment decoder 105 Read maximum value limiter 106 Interpolation circuit 107 Write and read And a memory 500 that can be separately controlled 500 Television receiver 501 Tuner 502 Digital broadcast decoder 503, 504 Selector 5 05 First video processing unit 505a Selector 506 Memory 507 Second video processing unit 508 Memory control unit 509 Microcomputer 510 Monitor 511 Audio processing unit 512 Speaker 520 Video display device 550 Clock conversion unit S1 Judgment step for determining broadcast system S2 Broadcast Search step for performing a table search for limiter values calculated for each method S3 Setting step for setting limiter values in registers S101 Horizontal synchronization pulse S102 Write address S104 Read reference pulse S105 Read address S108 Interpolated video signal S109 One clock S110 Second clock S111 Output signal

Claims (14)

A clock converter for converting data synchronized with a first clock to data synchronized with a second clock,
A memory having an address smaller than an address required to store data for a predetermined period, and capable of executing a write operation and a read operation independently of each other by a write clock and a read clock;
A first counter circuit unit that counts the first clock and creates a write address of the memory so that data for a predetermined period can be written to the memory in a plurality of times;
A second counter circuit unit that counts the second clock and creates a read address of the memory so as to enable reading of data for a predetermined period written to the memory in a plurality of times; Equipped,
A clock converter characterized by the above-mentioned. A clock converter for converting data synchronized with a first clock to data synchronized with a second clock,
A memory having an address smaller than an address required to store data for a predetermined period, and capable of executing a write operation and a read operation independently of each other by a write clock and a read clock;
The first clock count is started by input of a write start reference signal indicating a write start reference timing of the memory, and the data for a predetermined period is divided into a plurality of times so that the memory can be written to the memory. A first counter circuit unit for creating a write address of the memory;
The second clock is counted from a read start reference signal indicating a read start reference timing of the memory, and the memory for reading a predetermined period of data written to the memory in a plurality of times is enabled. A second counter circuit unit for creating a read address of
A clock converter characterized by the above-mentioned. A clock converter for converting data synchronized with a first clock to data synchronized with a second clock,
A memory having an address smaller than an address required to store data for a predetermined period, and capable of executing a write operation and a read operation independently of each other by a write clock and a read clock;
The first clock count is started by input of a write start reference signal indicating a write start reference timing of the memory, and the data for a predetermined period is divided into a plurality of times so that the memory can be written to the memory. A first counter circuit unit for creating a write address of the memory;
The second clock is counted from a read start reference signal indicating a read start reference timing of the memory, and the memory for reading a predetermined period of data written to the memory in a plurality of times is enabled. A second counter circuit unit for creating a read address of
A delay adjusting circuit capable of delaying the write start reference signal and generating the read start reference signal, and adjusting a delay time,
A clock converter characterized by the above-mentioned. A clock converter for converting data synchronized with a first clock to data synchronized with a second clock,
A memory having an address smaller than an address required to store data for a predetermined period, and capable of executing a write operation and a read operation independently of each other by a write clock and a read clock;
The first clock count is started by input of a write start reference signal indicating a write start reference timing of the memory, and the data for a predetermined period is divided into a plurality of times so that the memory can be written to the memory. A first counter circuit unit for creating a write address of the memory, which repeats increasing or decreasing within a predetermined address range of the memory;
The second clock is counted from a read start reference signal indicating a read start reference timing of the memory, and the memory for reading a predetermined period of data written to the memory in a plurality of times is enabled. A second counter circuit unit for creating a read address of the memory, which repeats increasing or decreasing within a predetermined address range of:
A delay adjusting circuit capable of delaying the write start reference signal and generating the read start reference signal, and adjusting a delay time,
A clock converter characterized by the above-mentioned. A clock converter for converting data synchronized with a first clock to data synchronized with a second clock,
A memory having an address smaller than the address required for storing data within a predetermined period, and capable of executing a write operation and a read operation independently of each other by a write clock and a read clock;
The first clock count is started by input of a write start reference signal indicating a write start reference timing of the memory, and the data for a predetermined period is divided into a plurality of times so that the memory can be written to the memory. The memory is repeatedly increased or decreased within a predetermined address range of the memory, and the last increase or decrease every predetermined period is increased or decreased within a narrower address range than within the predetermined address range. A first counter circuit unit for creating a write address of
The second clock is counted from a read start reference signal indicating a read start reference timing of the memory, and the memory for reading a predetermined period of data written to the memory in a plurality of times is enabled. Of the memory is repeated so that the last increase or decrease in the predetermined time period increases or decreases within a narrower address range than the predetermined address range. A second counter circuit for creating an address;
A delay adjusting circuit capable of delaying the write start reference signal and generating the read start reference signal, and adjusting a delay time,
A clock converter characterized by the above-mentioned. The clock converter according to any one of claims 1 to 5,
Storing in the memory using the number of write addresses in which a multiple of the maximum value of the write address is close to the number of samples of data sampled by the first clock within the predetermined period;
Using the number of read addresses where the multiple of the maximum value of the read address is close to the number of samples of data sampled at the second clock;
A clock converter characterized by the above-mentioned. The clock converter according to any one of claims 1 to 5,
Storing in the memory using a write address whose multiple of the maximum value of the write address is near the number of samples of the data sampled by the first clock within the predetermined period;
A clock converter using a read address having a maximum value equal to the maximum value of the write address. The clock converter according to any one of claims 1 to 5,
The predetermined period is one horizontal synchronization period.
A clock converter characterized by the above-mentioned. The clock converter according to any one of claims 1 to 5,
The first counter circuit section includes:
A write address counter that counts the first clock and generates the write address;
Comparing the write address output by the write address counter with the settable write maximum value, and having a write maximum value limiter that resets the write address counter when the write address and the write maximum value are equal.
A clock converter characterized by the above-mentioned. The clock converter according to any one of claims 1 to 5,
The second counter circuit section includes:
A read address counter that counts the second clock and creates the read address;
A read maximum value limiter that compares the read address output by the read address counter with a settable read maximum value, and resets the read address counter when the read address and the read maximum value are equal.
A clock converter characterized by the above-mentioned. A clock conversion method for converting data synchronized with a first clock to data synchronized with a second clock,
A memory having a smaller number of addresses than that required to store data for a predetermined period, and capable of performing a write operation and a read operation independently of each other by a write clock and a read clock, stores a plurality of data for a predetermined period Generating a write address based on the first clock so that the write is performed in separate times;
Generating a read address based on the second clock so as to read the data for the predetermined period from the memory a plurality of times;
A clock conversion method characterized by the above-mentioned. A first video processing unit that performs first video processing on the digital video signal based on a first clock;
A clock converter for converting the digital video signal output from the first video processor to a digital video signal synchronized with the first clock from the second clock;
A second video processing unit that performs second video processing on the digital video signal output from the clock conversion unit based on the second clock;
A display device for displaying a digital video signal output from the second video processing unit;
With
The clock converter,
A memory having a capacity smaller than one horizontal line of the digital video signal output from the first video processing unit and capable of performing a write operation and a read operation independently of each other by a write clock and a read clock;
The digital video signal output from the first video processing unit is written into the memory a plurality of times for each horizontal line, and the data read out for each horizontal line written to the memory a plurality of times is read out. A memory control unit for controlling the memory so as to enable the memory;
A video display device comprising: The image display device according to claim 12,
The memory control unit includes:
A count of the first clock is started by input of a write start reference signal indicating a write start reference timing of the memory, and data of one horizontal line is divided into a plurality of times so that writing to the memory can be performed. A first counter circuit unit for creating a write address of the memory;
The second clock is counted from a read start reference signal indicating a read start reference timing of the memory, and the data of one horizontal line written in the memory can be read in a plurality of times. A second counter circuit unit for creating a memory read address;
A video display device comprising: A first video processing unit that performs first video processing on the digital video signal based on a first clock;
A clock converter for converting the digital video signal output from the first video processor to a digital video signal synchronized with the first clock from the second clock;
A second video processing unit that performs second video processing on the digital video signal output from the clock conversion unit based on the second clock;
A display device for displaying a digital video signal output from the second video processing unit;
With
The clock converter,
A memory having an address smaller than the address required for storing data for a predetermined period, and capable of performing a write operation and a read operation independently of each other by a write clock and a read clock,
The first counter circuit unit generates a write address based on the first clock so as to write data for a predetermined period in a plurality of times,
A second counter circuit unit for generating a read address based on the second clock so as to read the data for the predetermined period from the memory in a plurality of times; A method for setting a memory address in a display device, comprising:
A determining step of determining a broadcasting system of the digital video signal input to the first video processing unit;
A search step of searching an upper limit or a lower limit of a count value of the first and second counter circuit units corresponding to the broadcast system according to the broadcast system determined in the determination step;
A setting step of setting an upper limit or a lower limit of the count value searched in the search step in the first and second counter circuit units;
A memory address setting method for a video display device, comprising:

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