JP2004088525A - Instantaneous response amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an instantaneous response amplifier circuit which does not require a potential holding circuit and eliminates instability or noise increase in circuit operations caused by DC coupling. <P>SOLUTION: The amplifier circuit has an average value detecting circuit 13A having a time constant about from several bits of bit width of an input signal to dozens of bits and a differential amplitude limit amplifier circuit 12A, an output terminal of the average value detecting circuit 13A is connected to one of differential input terminals of the differential amplitude limit amplifier circuit 12A to configure a basic amplification stage with an input terminal of the average value detecting circuit 13A and the other input terminal of the differential amplitude limit amplifier circuit 12A as an input terminal couple and with differential output terminals of the differential amplitude limit amplifier circuit 12A as an output terminal couple, and two basic amplification stages are cascade connected. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an instantaneous response amplifier circuit that instantaneously responds to an intermittently received optical signal such as an optical packet signal and differentially outputs a good amplified signal with little distortion.
[0002]
[Prior art]
In an optical network that handles an optical packet signal or the like, since a signal having a different light intensity is received for each packet, a receiver requires an amplifier circuit for equalizing and amplifying the signal. Generally, only one light receiving element such as a photodiode for receiving an optical signal is used per channel. Therefore, an impedance conversion amplifier circuit that converts a current signal output from the photodiode into a voltage signal has a single input / output. A single-ended amplifier circuit is used. However, for the purpose of improving the operation stability of the amplifier circuit and improving the consistency of the interface with the logic circuit, a differential circuit configuration has been used in the amplifier stage subsequent to the impedance conversion amplifier circuit. .
[0003]
In order for the differential amplifier circuit to operate normally, it is necessary to apply an intermediate level reference potential of the input signal to the input terminal to which the output of the impedance conversion amplifier circuit is not connected. If the level deviates from the level, distortion such as a decrease in the amplitude of the output signal or a fluctuation in the duty occurs, and the quality of the signal deteriorates. That is, the instantaneous response amplifier circuit needs to have a function of instantly extracting an optimum reference potential from the received packet signals having different light intensities and outputting a good differential signal.
[0004]
FIG. 13 shows an example of a conventional typical instantaneous response amplifier circuit. In FIG. 13, 1 is an input terminal, 2 is a differential amplifier circuit, 3 is a highest potential holding circuit, 4 is a lowest potential holding circuit, 5 and 5 'are resistors having the same value, and 6 and 7 are input terminals of the differential amplifier circuit. , 8, and 9 indicate output terminals of the differential amplifier circuit, and 10 and 11 indicate reset signal input terminals.
[0005]
The output signal of the impedance conversion amplifier circuit is input from the input terminal 1 to the input terminal 6 of the differential amplifier circuit 2. On the other hand, the signal branched at the input terminal 1 is input to the highest potential holding circuit 3 and the lowest potential holding circuit 4, and the highest potential and the lowest potential of the signal are instantaneously extracted and held. A good differential output can be obtained by generating an intermediate potential from the held highest potential and the lowest potential by dividing the two resistors 5, 5 'and inputting the intermediate potential to the input terminal 7 of the differential amplifier circuit 2. .
[0006]
[Problems to be solved by the invention]
The conventional instantaneous response amplifier circuit requires a high-speed potential holding circuit as described above. However, since the potential holding circuit generally has a configuration in which a potential is held by accumulating electric charges in a capacitor, a high-speed response performance is provided. In such a case, a very small capacity is required, and there is a problem that the holding force is reduced. Further, in the configuration using the potential holding circuit, it is necessary to reset the held potential before the next packet signal is input, and there is a problem that the configuration of the system becomes complicated.
[0007]
Further, in the conventional instantaneous response amplifying circuit, it is necessary to DC-couple the output terminal of the impedance conversion amplifying circuit and the input terminal 1 of the instantaneous response amplifying circuit from the principle of operation. This is because when connection is made using a coupling capacitance, the intermediate level of the signal greatly fluctuates with time due to a transient phenomenon of the coupling capacitance. For this reason, there has been a problem that the DC gain of the amplifier is increased, operation stability is lost, and low-frequency noise is increased.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide an instantaneous response amplifying circuit which solves the above-mentioned problem without using a potential holding circuit.
[0009]
[Means for Solving the Problems]
The invention according to claim 1 has an average value detection circuit having a time constant of about several bits to several tens of bits of a bit width of an input signal, and a differential type amplitude limiting amplifier circuit. An output terminal is connected to one input terminal of a differential input terminal of the differential type amplitude limiting amplifier circuit, and an input terminal of the average value detecting circuit and the other input terminal of the differential type amplitude limiting amplifier circuit are input terminals. The instantaneous response amplification circuit is characterized in that a basic amplification stage is configured as a pair, and a differential output terminal of the differential type amplitude limiting amplifier circuit is used as an output terminal pair, and the two basic amplification stages are cascaded. .
[0010]
According to a second aspect of the present invention, in the instant response amplifying circuit according to the first aspect, a voltage amplitude adjusting circuit for adjusting a voltage amplitude is inserted in a signal input path of the differential type amplitude limiting amplifier circuit. An instant response amplifier circuit was used.
[0011]
According to a third aspect of the present invention, in the instantaneous response amplifier circuit according to the second aspect, the voltage amplitude adjustment circuit is provided on a side of the differential type amplitude limiting amplifier circuit opposite to a side to which the average value detection circuit is connected. An instantaneous response amplifying circuit characterized in that it is a circuit for reducing the amplitude of a signal input to an input terminal.
[0012]
According to a fourth aspect of the present invention, in the instant response amplifying circuit according to the second aspect, the voltage amplitude adjusting circuit is connected to an input terminal of the differential type amplitude limiting amplifier circuit on the side where the average value detecting circuit is connected. The instant response amplifier circuit is a circuit for raising the lowest potential of the input signal.
[0013]
According to a fifth aspect of the present invention, in the instantaneous response amplifying circuit according to any one of the first to fourth aspects, one or both of the input section of the instantaneous response amplifying circuit and the basic amplifying stage has a coupling capacitance. And an instantaneous response amplifier circuit characterized by being connected by using the same.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention constitutes a basic amplification stage in which an average value detection circuit having a time constant of several bits to several tens of bits of an input signal is connected to one of differential input terminals of a differential type amplitude limiting amplifier circuit. By cascade-connecting the two basic amplification stages, waveform distortion due to high-speed operation of the average value detection circuit is compensated, and an appropriate differential output signal can be obtained.
[0015]
As a result, the present invention does not require a potential holding circuit as compared with the related art, so that it is possible to avoid a problem in a high-speed potential holding circuit configuration and to realize an instantaneous response amplifier circuit that does not require reset in a system configuration. it can. Further, since the present invention is effective even when the input portion of the instantaneous response amplifier circuit or the basic amplifier stage is capacitively coupled, it is possible to realize an instantaneous response amplifier circuit without instability of circuit operation and increase in noise due to DC coupling. Can be.
[0016]
[First Embodiment]
FIG. 1 is a block diagram showing an instantaneous response amplifier circuit according to the first embodiment. In FIG. 1, 1 is an input terminal, 12A and 12B are differential-type amplitude limiting amplifier circuits, 13A and 13B are average value detection circuits whose time constants are set to several bits to several tens of bits, and 14 , 15 are input terminals of the first-stage differential amplitude limiting amplifier circuit 12A, 16 and 17 are output terminals of the first-stage differential amplitude limiting amplifier circuit 12A, and 18 and 19 are second-stage differential amplitude limiting amplifier circuits. Input terminals of the amplitude limiting amplifier circuit 12B, 20 and 21 are output terminals of the second-stage differential type amplitude limiting amplifier circuit 12B, 22 and 23 are differential output terminals, 24 and 25 are power supply or electrical ground, and 26 is A first basic amplification stage 27 indicates a second basic amplification stage.
[0017]
FIG. 2 shows a specific example of the average value detection circuits 13A and 13B shown in FIG. In FIG. 2, 28 is a resistor, 29 is a capacitor, 30 is an input terminal, and 31 is an output terminal.
[0018]
FIG. 3 shows operation waveforms of the instantaneous response amplifier circuit of the first embodiment shown in FIG. 3A shows an input signal waveform diagram of the first-stage differential amplitude limiting amplifier circuit 12A, FIG. 3B shows an input signal waveform diagram of the second-stage differential amplitude limiting amplifier circuit 12B, and FIG. ) Is a differential output signal waveform diagram of the differential output terminals 22 and 23, (d) is an enlarged view of a packet head portion of the differential output signal waveform, (e) is an enlarged view of a packet signal central portion of the differential output signal waveform, (F) is an enlarged view of a portion of the alternating signal after the continuous sign of the differential output signal waveform, and 14 ', 15', 18 ', 19', 22 ', and 23' are 14, 15, 18, 19, 22 in FIG. , 23 show the voltage waveforms at the terminals.
[0019]
The voltage signal 14 'input from the input terminal 1 is input to the input terminal 14 of the first-stage differential type amplitude limiting amplifier circuit 12A and at the same time to the average value detection circuit 13A, and its output voltage signal 15'. Is input to the input terminal 15 of the first-stage differential amplitude limiting amplifier circuit 12A. Here, the time constant of the average value detection circuit 13A is set to about several bits to several tens of bits for the bit width of the signal, and the average value can be instantaneously detected in about the time constant from the start of signal input. .
[0020]
However, as is apparent from the voltage waveform 15 'at the input terminal 15 of the first-stage differential type amplitude limiting amplifier circuit 12A in FIG. 3, the fast-responding average value detection circuit 13A responds to the sign of the signal to some extent. Would. This is particularly remarkable when a continuous code is input, and the output potential of the average value detection circuit 13A is drawn to the high potential side when "1" is continuous and to the low potential side when "0" is continuous. I will. The high-speed operation of the average value detection circuit 13A causes an undesired fluctuation in the reference potential of the differential type amplitude limiting amplifier circuit 12A, and thus causes distortion and duty fluctuation in the output waveform of the amplitude suppression amplifier circuit 12A. Let me do it.
[0021]
Therefore, in the present invention, the distortion and the duty fluctuation are compensated by using the second-stage differential amplitude limiting amplifier circuit 12B and the average value detection circuit 13B. The operation of the second basic amplification stage 27 will be described below. The signals output from the output terminals 16 and 17 of the first-stage differential-type amplitude limiting amplifier circuit 12A have the waveforms in which the distortion and the duty fluctuation described above have occurred. If the amplitude limiting function of the circuit 12A is a signal within an effective input signal amplitude range, the amplitude of the output waveform is limited to a constant value and output. Therefore, when the output signal of the output terminal 17 is input to the average value detection circuit 13B of the second stage, the voltage 15 'of the reference potential waveform input to the input terminal 15 of the differential amplitude limiting amplifier circuit 12A of the first stage. A voltage 19 'having a waveform substantially equal to the waveform obtained by inverting the vertical direction is output. The voltage 19 'having this waveform is input to the input terminal 19 of the second-stage differential amplitude limiting amplifier circuit 12B, and the differential voltage is applied as a reference potential to the input voltage 18' of the second-stage differential amplitude limiting amplifier circuit 12B. When the amplification operation is performed, the distortion and the duty fluctuation substantially opposite to the distortion and the duty fluctuation generated in the first-stage differential amplitude limiting amplifier circuit 12A can be generated. The differential output voltages 22 'and 23' of the amplifier circuit 12B have good waveforms with little distortion and fluctuation in duty.
[0022]
3 (d) to 3 (f) show enlarged waveforms of the differential output voltages 22 'and 23'. It can be seen that good waveforms with little distortion and duty fluctuation can be obtained also in the packet head part (d), the packet signal central part (e), the alternating continuous code part (f) after the continuous code, and the like.
[0023]
[Second embodiment]
FIG. 4 shows an instantaneous response amplifier circuit according to the second embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, the second-stage average value detection circuit 13B is connected between the output terminal 16 of the first-stage differential amplitude limiting amplifier circuit 12A and the input terminal 18 of the second-stage differential amplitude limiting amplifier circuit 12B. Shows what was inserted in the. When the output signal of the output terminal 16 is input to the second-stage average value detection circuit 13B, the output has a waveform substantially equal to the output signal of the first-stage average value detection circuit 13A. This waveform is input to the input terminal 18 of the second-stage differential amplitude limiting amplifier circuit 12B, and the other input terminal 19 is output from the output terminal 17 of the first-stage differential amplitude limiting amplifier circuit 12A. By inputting the inverted output signal, the same effect as in the first embodiment can be obtained.
[0024]
As described above, the instantaneous response amplifying circuit of the present invention is effective regardless of whether the average value detecting circuit is inserted on either side of the differential terminal pair, and can be arbitrarily selected in all the basic amplifying stages.
[0025]
[Third Embodiment]
FIG. 5 shows an instantaneous response amplifier circuit according to the third embodiment. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals. 32A and 32B indicate voltage amplitude adjustment circuits. FIG. 6 shows a specific example of the voltage amplitude adjusting circuits 32A and 32B. In FIG. 6, 33 is a resistor, 34 is an input terminal, and 35 is an output terminal.
[0026]
As is clear from the principle of operation of the instantaneous response amplifier circuit of the present invention, the fluctuation range of the reference potential output from the average value detection circuit is limited by the differential amplitude limit on the side to which the output terminal of the average value detection circuit is not connected. It must be within the amplitude of the signal input to the input terminal of the amplifier circuit. The output potential width of the average value detection circuit is determined by the ratio between the input / output impedance of the average value detection circuit and the input impedance of the differential amplitude limiting amplifier circuit. If the input impedance of the amplifier circuit is not negligible, the output potential width decreases and the entire output reference potential shifts up and down according to the DC potential of the input terminal of the differential amplitude limiting amplifier circuit. I do. When this shift causes the output minimum potential of the average value detection circuit to fall below the minimum potential of the signal input to the input terminal of the differential type amplitude limiting amplifier circuit on the side to which the output terminal of the average value detection circuit is not connected. Cannot operate normally.
[0027]
The voltage amplitude adjusting circuits 32A and 32B shown in FIG. 6 are composed of resistors 33, and have the same resistance value as the resistance 28 of the average value detecting circuits 13A and 13B shown in FIG. By connecting this to the side where the average value detection circuits 13A and 13B are not connected as shown in FIG. 5, the amplitude of the signal input to the differential type amplitude limiting amplifier circuits 12A and 12B can be reduced. It can be adjusted to the reference potential fluctuation width output from 13A and 13B.
[0028]
[Fourth embodiment]
FIG. 7 shows an instantaneous response amplifier circuit according to the fourth embodiment. 7, the same components as those in FIG. 1 are denoted by the same reference numerals. 36A and 36B denote another voltage amplitude adjusting circuit, and 37 and 38 denote a power supply or an electrical ground. FIG. 8 shows a specific example of another voltage amplitude adjustment circuit 36A, 36B. 8, 39 and 40 are resistors, 41 is an input terminal, and 42 is an output terminal.
[0029]
In the present embodiment, by applying a potential higher than the lowest potential level of the signal to the power supply or the electrical ground 37, 38 of the voltage amplitude adjusting circuits 36A, 36B, the lowest potential of the signal input to the average value detection circuits 13A, 13B is provided. And the minimum potential of the output reference potential can be raised. Further, since the potential width of the output signals of the voltage amplitude adjustment circuits 36A and 36B is reduced by the resistors 39 in the voltage amplitude adjustment circuits 36A and 36B, the output signals are input to the input terminals 14 and 18 of the differential type amplitude limiting amplifier circuit. It is easy to fit within the amplitude of the signal. However, when the average value detection circuits 13A and 13B sufficiently reduce the output potential width, the resistor 39 may be short-circuited.
[0030]
[Fifth Embodiment]
FIG. 9 shows an instantaneous response amplifier circuit according to the fifth embodiment. 9, the same components as those in FIGS. 5 and 7 are denoted by the same reference numerals. Reference numerals 43 and 44 indicate a power supply or an electrical ground. An example in which the voltage amplitude adjustment circuits 32A, 32B in FIG. 5 and another voltage amplitude adjustment circuit 36A, 36A ', 36B, 36B' as described with reference to FIG. Can be.
[0031]
FIGS. 5 and 7 show an example in which the voltage amplitude adjustment circuits 32A and 32B and another voltage amplitude adjustment circuit 36A and 36B are used in all the basic amplification stages. However, if it is used for at least one basic amplification stage, an effect can be obtained. The other voltage amplitude adjusting circuits 36A and 36B in FIG. 7 may be used for both input terminal pairs of the basic amplification stage as shown in FIG.
[0032]
FIGS. 7 and 9 show an example in which another voltage amplitude adjustment circuit 36A, 36A ', 36B, 36B' is connected to the input terminals of the average value detection circuits 13A, 13B and the voltage amplitude adjustment circuits 32A, 32B. However, the same effect can be obtained by inserting between the average value detection circuits 13A and 13B and the voltage amplitude adjustment circuits 32A and 32B and the differential amplitude limiting amplifier circuits 12A and 12B.
[0033]
Further, FIG. 9 shows an example in which another voltage amplitude adjusting circuit 36A, 36A ', 36B, 36B' is inserted into the differential input terminal pair of all the basic amplification stages. The same effect can be obtained if at least one of the voltage amplitude adjusting circuits 36A and 36B is inserted.
[0034]
[Sixth Embodiment]
FIG. 10 shows an instantaneous response amplifier circuit according to the sixth embodiment. 10, the same components as those in FIG. 1 are denoted by the same reference numerals. 45A, 45A ', 45B, 45B' denote coupling capacitances, 46A, 46A ', 46B, 46B' denote bias circuits, and 47-50 denote power supplies or electrical grounds. FIG. 11 shows a specific example of the bias circuits 46A, 46A ', 46B, 46B'. 11, 51 indicates an inductor, 52 indicates an input terminal, and 53 indicates an output terminal.
[0035]
FIG. 12 shows operation waveforms of the instantaneous response amplifier circuit shown in FIG. The symbols in the figure are the same as those in FIG. 3, and 14 ', 15', 18 ', 19', 22 ', and 23' are the terminals of 14, 15, 18, 19, 22, and 23 in FIG. 3 shows a voltage waveform. If the time constants of the coupling capacitors 45A, 45A ', 45B, 45B' and the input impedances of the basic amplification stages 26, 27 are designed to be sufficiently larger than the time constants of the average value detection circuits 13A, 13B, the average value detection circuits 13A, 13B The average value detection circuit 13A of the first basic amplification stage 26 can normally generate the reference potential because it can follow the fluctuation of the intermediate potential of the signal due to the transient phenomenon of the coupling capacitors 45A, 45A ', 45B, 45B'. Works without problems.
[0036]
Here, when the same potential is applied to the input terminals 14 and 15 of the first-stage differential type amplitude limiting amplifier circuit 12A through the bias circuits 46A and 46A ', the standby state (no signal state) or the average value For example, when a continuous code having a length equal to or longer than the time constant of the detection circuit 13A is input, the output potential of the first basic amplification stage 26 is drawn to the intermediate potential of the differential amplitude limiting amplifier circuit 12A. Due to this operation, the amplitude of the output of the first basic amplification stage 26 becomes about half that of the data input after the leading portion of the packet or after the continuous code (FIG. 12B). Since the output signal of the first basic amplification stage 26 is a differential signal, the capacitive coupling between the basic amplification stages greatly separates the intermediate potentials of the differential input signals of the second basic amplification stage 27. However, this effect is compensated (mitigated) because the amplitude of the head portion is small, and although distortion and duty fluctuation slightly remain after the packet head portion and the continuous code, the operation is basically performed in the same manner as in DC coupling. (FIGS. 12D to 12F).
[0037]
FIG. 10 shows an example in which both the input section of the instantaneous response amplification circuit and the basic amplification stage are capacitively coupled for convenience, but either one may be used. As in the third embodiment (FIG. 5) of the present invention, the voltage amplitude adjusting circuit 32A is connected to the input terminals of the differential type amplitude limiting amplifier circuits 12A and 12B on the side where the average value detecting circuits 13A and 13B are not connected. , 32B may be used. Also, the bias circuits 46A, 46A ', 46B, 46B' are similar to the other voltage amplitude adjustment circuits 36A, 36A ', 36B, 36B' in FIG. 9, and have average value detection circuits 13A, 13B and voltage amplitude adjustment circuits 32A, 32A. 32B and the differential type amplitude limiting amplifier circuits 12A and 12B. Furthermore, the bias circuits 46A, 46A ', 46B, 46B' may be replaced by resistors or another voltage amplitude adjusting circuits 36A, 36A ', 36B, 36B', and impedance matching between the input and output of the circuit is required. In this case, the bias may be supplied using an impedance matching circuit. When an impedance matching circuit is built in the differential type amplitude limiting amplifier circuits 12A and 12B, or when a part is DC-coupled, all the bias circuits 46A, 46A ', 46B and 46B' are not necessarily provided. It does not need to be connected to the input.
[0038]
[Other embodiments]
In the instantaneous response amplifier circuits of the first to sixth embodiments described above, the input terminal 1 is represented as two input terminal pairs for the sake of convenience. It is good. In the first to sixth embodiments, when impedance matching is required between the input section of the instantaneous response amplifier circuit or the basic amplifier stages 26 and 27, an impedance matching circuit may be used.
[0039]
In the instantaneous response amplifier circuits of the third to sixth embodiments, for convenience, the average value detection circuits 13A and 13B are connected to the input terminals 15 and 19 of the differential amplitude limiting amplifier circuits 12A and 12B in all the basic amplification stages. Although an example has been shown, for the same reason as in the second embodiment shown in FIG. 4, it is effective regardless of which side the average value detection circuits 13A and 13B are inserted, as long as it is one of the differential terminal pairs. It can be selected arbitrarily in all basic amplification stages.
[0040]
Further, the average value detection circuits 13A and 13B shown in FIG. 2, the voltage amplitude adjustment circuits 32A and 32B shown in FIG. 6, the other voltage amplitude adjustment circuits 36A and 36B shown in FIG. 8, and the bias shown in FIG. The circuits 46A, 46A ', 46B, 46B' are effective in any circuit configuration as long as they provide similar functions. Also, circuit blocks with the same number and distinguished by subscripts A, B, A ', and B' used in a plurality of locations in all circuit diagrams need to have exactly the same circuit configuration as long as they provide similar functions. Absent.
[0041]
【The invention's effect】
As described above, since the instantaneous response amplifier circuit of the present invention does not require a potential holding circuit as compared with the related art, it is possible to avoid a problem in a high-speed potential holding circuit configuration and does not require a reset in a system configuration. Further, since the present invention is effective even when capacitive coupling is performed between the basic amplification stages, it is possible to realize an instantaneous response amplification circuit free from instability of circuit operation and increase in noise due to DC coupling.
[Brief description of the drawings]
FIG. 1 is a block diagram of an instantaneous response amplifier circuit according to a first embodiment.
FIG. 2 is a circuit diagram of a specific example of an average value detection circuit in FIG.
3A and 3B are diagrams showing operation waveforms of the instantaneous response amplifier circuit of FIG. 1, wherein FIG. 3A is an input signal waveform diagram of a first-stage differential type amplitude limiting amplifier circuit, and FIG. (C) is a differential output signal waveform diagram, (d) is an enlarged view of a packet head portion of the differential output signal waveform, and (e) is a packet signal of the differential output signal waveform FIG. 7F is an enlarged view of a central portion, and FIG.
FIG. 4 is a block diagram of an instantaneous response amplifier circuit according to a second embodiment.
FIG. 5 is a block diagram of an instantaneous response amplifier circuit according to a third embodiment.
FIG. 6 is a circuit diagram of a specific example of a voltage amplitude adjustment circuit in FIG. 5;
FIG. 7 is a block diagram of an instantaneous response amplifier circuit according to a fourth embodiment.
8 is a circuit diagram of a specific example of the voltage amplitude adjustment circuit in FIG.
FIG. 9 is a block diagram of an instantaneous response amplifier circuit according to a fifth embodiment.
FIG. 10 is a block diagram of an instantaneous response amplifier circuit according to a sixth embodiment.
11 is a circuit diagram of a specific example of the bias circuit in FIG.
12A and 12B are diagrams illustrating operation waveforms of the instantaneous response amplifier circuit of FIG. 10, wherein FIG. 12A is an input signal waveform diagram of a first-stage differential amplitude limiting amplifier circuit, and FIG. (C) is a differential output signal waveform diagram, (d) is an enlarged view of a packet head portion of the differential output signal waveform, and (e) is a packet signal of the differential output signal waveform FIG. 7F is an enlarged view of a central portion, and FIG.
FIG. 13 is a block diagram of a conventional instantaneous response amplifier circuit.
[Explanation of symbols]
1: Input terminal 2: Differential amplifier circuit 3: Highest potential holding circuit 4: Lowest potential holding circuit 5, 5 ': Resistors 6, 7: Input terminals 8, 9 of differential amplifier circuit: Output terminals of differential amplifier circuit 10, 11: reset signal input terminals 12A, 12B: differential amplitude limiting amplifier circuits 13A, 13B: average value detection circuit 14, 15: input terminals 14 ', 15 of the first stage differential amplitude limiting amplifier circuit 12A. ': Voltage waveforms 16 and 17 at terminals 14 and 15: output terminal 18 of differential amplitude limiting amplifier circuit 12A of first stage, 19: input terminal 18' of differential amplitude limiting amplifier circuit 12B of second stage, 19 ': Voltage waveforms at terminals 18, 19, 20, 21: Output terminals 22, 23 of the second-stage differential amplitude controlled amplification circuit 12B: Differential output terminals 22', 23 ': Voltages at terminals 22, 23 Waveforms 24 and 25: power supply or electric ground 26: first basic amplification stage 2 7: Second basic amplification stage 28: Resistance 29: Capacitance 30: Input terminal 31 of the average value detection circuit: Output terminals 32A and 32B of the average value detection circuit: Voltage amplitude adjustment circuit 33: Resistance 34: Voltage amplitude adjustment circuit Input terminal 35: Output terminal 36A, 36A ', 36B, 36B' of voltage amplitude adjustment circuit: Another voltage amplitude adjustment circuit 37, 38: Power supply or electric ground 39, 40: Resistance 41: Another voltage amplitude adjustment Input terminal 42 of the circuit: output terminals 43 and 44 of another voltage amplitude adjusting circuit: power supply or electric ground 45A, 45A ', 45B, 45B': coupling capacitance 46A, 46A ', 46B, 46B': bias circuit 47 50: power supply or electric ground 51: inductor 52: input terminal of bias circuit 53: output terminal of bias circuit

Claims (5)

An average value detection circuit having a time constant of about several tens bits to several tens of bits of a bit width of an input signal, and a differential type amplitude limiting amplifier circuit,
An output terminal of the average value detection circuit is connected to one input terminal of a differential input terminal of the differential type amplitude limiting amplifier circuit, and an input terminal of the average value detection circuit and the other of the differential type amplitude limiting amplifier circuit. The input terminals of the differential-type amplitude limiting amplifier circuit as a pair of output terminals, and configure a basic amplification stage having a pair of differential output terminals as an output terminal pair;
An instantaneous response amplifying circuit comprising two cascade-connected basic amplifying stages. The instant response amplifier circuit according to claim 1,
An instant response amplifier circuit, wherein a voltage amplitude adjusting circuit for adjusting a voltage amplitude is inserted into a signal input path of the differential type amplitude limiting amplifier circuit. The instantaneous response amplifier circuit according to claim 2,
The voltage amplitude adjustment circuit is a circuit for reducing the amplitude of a signal input to an input terminal of the differential type amplitude limiting amplifier circuit which is opposite to a side to which the average value detection circuit is connected. Response amplification circuit. The instantaneous response amplifier circuit according to claim 2,
The instantaneous response amplification circuit, wherein the voltage amplitude adjustment circuit is a circuit that raises a minimum potential of a signal input to an input terminal of the differential type amplitude limiting amplifier circuit that is connected to the average value detection circuit. . The instantaneous response amplifier circuit according to any one of claims 1 to 4,
An instantaneous response amplifying circuit, wherein either one or both of an input section of the instantaneous response amplifying circuit and between the basic amplifying stages are connected using a coupling capacitor.

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