JP2004080334A - Packet transfer circuit in ip over atm - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a packet transfer circuit in IP over ATM exhibiting a maximum packet transfer capacity by performing read, write and refresh within a predetermined period using an SDRAM. <P>SOLUTION: A packet processing section comprises a buffer memory consisting of a plurality (n) of SDRAMs accessible in parallel, a serial/parallel converter receiving input packets in series and delivering them in parallel, and a parallel/serial converter for storing a plurality of parallel signals read out from the buffer memory and generating an output packet. Three operations, i.e. an operation for storing packets in the serial/parallel converter and writing them simultaneously in parallel into respective SDRAMs, an operation for storing signals read out from the SDRAMs in the parallel/serial converter, and a refresh operation, are performed within the refresh period. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a packet transfer circuit in an IP over ATM (ATM) that transfers an IP (Internet Protocol) packet, which is variable-length data, through an ATM (Asynchronous Transfer Mode) that transmits a fixed-length cell.
[0002]
In recent years, techniques for efficiently transferring digital signals of various speeds in the form of fixed-length cells by ATM have been used. The ATM network uses fixed-length cells. On the other hand, IP networks for transferring digital signals from personal computers and various terminals using variable-length packets have become widespread, and their use is expected to increase in the future. Has come to be used. The transfer of such an IP packet by ATM is hereinafter referred to as IP over ATM.
[0003]
When an IP packet is transferred on an ATM network, a buffer memory is used to perform a routing process of the IP packet, and a reduction in the size and cost of the buffer memory is desired.
[0004]
[Prior art]
FIG. 7 is an example of the configuration of a system to which the present invention is applied, and FIG. 8 is an explanatory diagram of a conventional buffer memory.
[0005]
In the configuration of FIG. 7, an IP network 80 and an ATM network 85 are connected. At the boundary between the IP network 80 and the ATM network 85, an input processing unit 81 for converting an ATM cell (consisting of a 5-byte header and a 48-byte payload) into an IP packet (variable length), An output processing unit 82 for converting to an ATM cell is provided. The IP network 80 is provided with an IP processing unit 83 for performing processing such as routing a packet to each destination, and a buffer memory 84 for performing the processing. That is, a process of inputting an IP packet, determining its destination, selecting an optimal route, creating a header, reading the packet from the buffer memory 84 and adding the created header is performed.
[0006]
A conventional buffer memory will be described with reference to FIG. When a conventional asynchronous variable-length packet is input, the process of writing to the buffer memory and reading the packet is performed asynchronously.
[0007]
FIG. Is a case where an SDRAM (Synchronous Dynamic Random Access Memory) 90 is used as a buffer memory. When accessing the buffer memory 90, control is easy if writing and reading are performed independently (moved at different timings). However, if writing and reading are attempted at the same time due to the processing time, a collision between writing and reading occurs in an SDRAM having a single port. Further, the DRAM needs to perform the refresh operation at a constant period (every 64 ms), and it is difficult to perform the asynchronous processing.
[0008]
As a method for resolving such a collision, FIG. In some cases, a DPRAM (Dual Port RAM) 91 having two ports as shown in FIG. However, this DPRAM has a small storage capacity and it is difficult to handle high-speed and large-capacity data.
[0009]
In addition, an SSRAM (Synchronous Static RAM) may be used as a buffer memory. This SSRAM does not need to be refreshed, but cannot perform write and read processing at the same time, and has a small capacity like a DPRAM.
[0010]
[Problems to be solved by the invention]
As described above, SSRAM is not suitable for a buffer memory of a processing unit of IP over ATM, and DPRAM has a problem that its storage capacity is small. In addition, even in a configuration using a conventional SDRAM, there is a problem that it is difficult to perform refresh at a constant cycle.
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems in the prior art and to provide a packet transfer circuit in an IP over ATM in which a read / write operation and a refresh can be performed within a fixed period using a large capacity SDRAM. .
[0012]
[Means for Solving the Problems]
FIG. 1 is a diagram for explaining the principle of the present invention. Indicates the configuration; Indicates the operation timing. FIG. , 1 is a buffer memory composed of a plurality of SDRAMs (single-port DRAMs) requiring a refresh operation, 10-1 to 10-n are a plurality (n) of SDRAMs constituting the buffer memory 1, and 2 Is a serial / parallel converter, and 3 is a parallel / serial converter.
[0013]
When the input packet signal (including a case where a plurality of bits are input in parallel) is input to the serial-to-parallel converter 2, it is converted into n parallel digital signals (each of which may have a plurality of bits). Are input to the plurality of SDRAMs 10-1 to 10-n to perform a write operation. Read signals from the SDRAMs 10-1 to 10-n of the buffer memory 1 are input to corresponding positions of the parallel-to-serial converter 3 and set, and then output in series from the parallel-to-serial converter 3 to form packet signals. Is output. At this time, processing such as changing the header or the like is performed on the output packet. As described above, since writing and reading to and from the buffer memory 1 are simultaneously performed for a plurality of bits (for example, 32 bits) in parallel, the writing time and the reading time are reduced as compared with the case where the serial input signal is sequentially performed. Therefore, the refresh time of the buffer memory 1 can be sufficiently secured. FIG. In the example of the operation timing shown in (1), in one cycle (time shorter than the refresh cycle), a sufficient refresh time Rf can be secured in addition to the write time Wr and the read time Rd.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 2 shows the configuration of the embodiment. In the figure, 1 is a buffer memory, 10-1 to 10-4 are SDRAMs as in FIG. 1, 11 is a control unit for controlling writing, reading and refresh operations to and from the buffer memory 1, and 20 is a control unit in FIG. Corresponding to the serial-to-parallel converter 2, a write FIFO (First In First) having a function of storing input signals serially while shifting them sequentially from the head, converting them into parallel signals, and outputting write data to the buffer memory 1 Out) and 30 correspond to the parallel-to-serial converter 3 of FIG. 1 and have a function of storing data read from the buffer memory 1 in parallel and outputting the data serially, and a read FIFO 4a to the write FIFO 20. , 4b is a cycle number, 5a is an output signal from the read FIFO 30, and 5b is a cycle number.
[0015]
In this embodiment, the input signal 4a and the output signal 5a in FIG. 2 are represented by one pulse-like waveform for each of the cycle numbers 4b and 5b indicated by 1 to 8, but one bit is provided for each cycle. Is transmitted (input or output), but a 16-bit parallel signal is transmitted (input or output) in one cycle. An operation of storing the input signals 1 to 8 for eight cycles in the write FIFO 20 in two stages of 1 to 4, 5 to 8 and storing four parallel outputs in the buffer memory 1 is performed. By performing two cycles, input signals 1 to 8 can be written. Also, in the read FIFO 30, four parallel read signals are stored in parallel in one cycle, and by performing this operation in two cycles, eight signals 1-4 and 5-8 are stored in the two-stage FIFO 30. Is stored.
[0016]
The operation will be described. First, each of the signals 1 to 8 (each a 16-bit parallel signal) shown in FIG. As shown in (1), they are sequentially stored in two stages of storage positions 1-4 and 5-8. Thereafter, the first to fourth signals of the write FIFO 20 are set to B.B. At the write timing (length of 2 cycles) indicated by Wr. That is, in the first cycle of Wr, data is written in parallel to the SDRAMs 10-1 to 10-4 of the buffer memory 1, and in the second cycle of Wr, the signals of the next stage 5-8 of the write FIFO 20 are transmitted to the SDRAMs 10-1 to 10-8. It is written to the next address in 10-4.
[0017]
Thereafter, the reading of the data written in the buffer memory 1 is performed according to B. At the timing (the length of two cycles) indicated by Rd. That is, in the first cycle of Rd, signals 1 to 4 written in parallel to the SDRAMs 10-1 to 10-4 of the buffer memory 1 are read out in parallel and placed in the positions indicated by 1 to 4 of the read FIFO 30. Is stored. B. of FIG. In the second cycle of Wr, the signals 5 to 8 written to the SDRAMs 10-1 to 10-4 are read out in parallel and stored in the reading FIFO 30. Thereafter, the contents of the read FIFO 30 are sequentially read in accordance with the timing of the cycle numbers 5b of 1 to 8, and a serial output signal 5a is obtained. When packet data having a plurality of ATM cells (payload portion) is written in the SDRAM of the buffer memory 1, the destination of the packet data is determined, and routing processing (packet header processing) is performed.
[0018]
FIG. 3 shows a control flow until one packet is input, the buffer (SDRAM) is accessed by the control unit (11 in FIG. 2), and the packet is output. First, when a packet is input, it is determined whether the write FIFO (represented by wFifo) is full (full of data) or packet end (end of packet input) (S1 in FIG. 3). When the write FIFO is full or at the end of the packet, it is determined whether the write time has come (step S2). If it is the write time, write to the SDRAM (S3 in FIG. 3). Subsequently, it is determined whether the packet writing is completed (S4 in FIG. 3), and if completed, it is determined whether it is the reading time (S5 in FIG. 3). If the reading time is reached, the SDRAM is read (S6). . Next, it is determined whether the read FIFO (represented by rFifo) is full or packet end (S7 in FIG. 3), and if any of them is satisfied, a packet is output from the read FIFO.
[0019]
FIG. 4 shows an example of the transfer operation when the packet processing cycle is set to 2 cell times. Here, the 2-cell time represents a time corresponding to two (128 bytes) in the case of a 64-byte ATM cell, and the cycle (packet cycle) means writing and refreshing in the IP processing unit (1 in FIG. 1). , Readout process means a combination cycle. A. of FIG. Is a case where there are input of 2 cells / packet, Is a case where there are input of 3 cells / packet.
[0020]
First, in FIG. To explain the example, (1) represents a period (packet period), which is 2 cell times. {Circle around (2)} indicates the timing of accessing the buffer memory (represented by BM), and three processes of writing (represented by Write), refreshing (represented by Ref), and reading (represented by Read) are performed within two cell times. It is repeated for each cycle. For such a processing cycle, when an input (indicated by input) of a 2-cell packet shown in (3) occurs as represented by numbers 1, 2, 3, and 4, a readout output (indicated by output) Occurs at the timing shown in (4).
[0021]
That is, the input of the packet 1 in (3) is stored in the write FIFO (20 in FIG. 2), and is then written in parallel to the buffer memory (a plurality of SDRAMs) at the timing of W1 in (2). Are read in parallel from the buffer memory at the timing of R1. After the packet 2 input of (3) is stored in the FIFO, it is written in parallel to the buffer memory at the timing of W2 of (2), and is read in parallel from the buffer memory at the timing of R2 of (2).
[0022]
In FIG. In the case of the input of 2 cells / packet, transfer at the maximum speed can be realized.
[0023]
Next, in FIG. For example, (1) indicates that the cycle (packet cycle) is A. In this example, the packet input is A. In this case, the length is 3 cells / packet as shown in (3). In this case, the access timing of the buffer memory (BM) is B. The configuration shown in (2) above is obtained. That is, since the input packet is long, the above A.P. Similarly to (2), operation time for write (Write), refresh (Ref), and read (Read) is provided, and thereafter, operation time for write (Write) and refresh (Ref) for one cell is provided. Then, write (W), refresh (Ref), and read (R) are performed twice for each packet (for example, write W1-1 and W1-2 twice for packet 1, and read R1-1 for packet 1-1). , R1-2, and refresh twice).
[0024]
The write operation will be described. When two cells (from the beginning to the 2/3 position) of the input of the packet 1 in (3) are stored in the FIFO, at the timing of W1-1 in (2). The remaining one cell of the input packet 1 shown in (3) is written into the buffer memory and stored in the FIFO, and then written into the buffer memory at the timing of W1-2 in (2). When two cells of the input packet 2 shown in (3) are stored in the FIFO, they are written into the buffer memory at the timing of W2-1 in (2), and the remaining one cell of the input packet 2 is stored in the FIFO. After being stored, it is written into the buffer memory at the timing of W2-2 in (2), and similarly in the case of B.2 in FIG. Each packet shown in (3) is sequentially written to the buffer memory.
[0025]
B. of FIG. In the output (reading) operation from the buffer memory, two cells are read out from the buffer memory to the FIFO at R1-1 in (2), which is the first read timing after the input packet 1 is written into the buffer memory. , Two cells are output from the FIFO at the timing indicated by the output packet 1 in (4). At the timing of R1-2 of (2), the remaining one cell of the output packet 1 is read from the buffer memory to the FIFO, and is output from the FIFO following the preceding two cells. As indicated by {circle around (4)} in FIG. 4, after the output of the packet 1, a loss time occurs until the output of the packet 2. This occurs until the timing (R2-1) of reading the packet 2 from the buffer memory follows the timing (R1-2) at which the reading of the packet 1 from the buffer memory is completed, as shown in (2). This is because the time interval is empty. This is because the input packet is as long as three cells.
[0026]
A. of FIG. In the example shown in (1), if the input packet has a speed of 600 Mbps, the output packet is also delayed by two packets, but a throughput of 600 Mbps is obtained. In contrast, FIG. In the case of (1), the input packet is 600 Mbps, and a loss occurs by 1/4 at the time of output.
[0027]
FIGS. 5 and 6 show examples (part 1) and (part 2) of the transfer operation when the processing cycle of the packet is optimized. Note that this example of the transfer operation is an example of the operation in the system configuration shown in FIG. 7 described above.
[0028]
FIG. 5 shows an example of optimization in the case where the packet input is composed of two cells. Referring to FIG. 7, the description will be made from the ATM cell domain of FIG. 7 every two cell periods shown in (1) of FIG. (2) (displayed as input) 1, 2,... Are input to the input processing unit (81 in FIG. 7). Each input of (2) contains two ATM cells each including an ATM header (5 bytes). The input processing unit removes the ATM header and converts the packet into a packet (compatible with IP). As shown by (3) in (5), packet inputs 1, 2,... To the IP processing unit (83 in FIG. 7) are made shorter (the ATM header is removed). In the IP processing unit, as shown in (4) in FIG. 5, the operation is performed in a packet cycle shorter than the cell cycle shown in (1) (the same as the packet input length shown in (3)), and shown in FIG. As shown in {circle around (5)} in FIG. 5, the access to the buffer memory (BM) composed of a plurality of SDRAMs depends on the combination of the write (Write), refresh (Ref), and read (Read) cycles. Done at the same time.
[0029]
After the packet input 1 indicated by (3) in FIG. 5 is stored in the FIFO, it is written into the buffer memory by the write operation W1 of (5) in FIG. 5, which is the first write operation. Similarly, the packet inputs 2 and 3 of (3) are written into the buffer memory at the timings of W2 and W3 of the buffer memory (BM) access of (5), and the packet input 4 is written in the buffer memory (BM) shown in (5). Due to the timing of the access, the data is written to the buffer memory at the timing of W4 in (5) with a delay of a certain time. Reading from the buffer memory is performed at the timing of R1, which is a read access shown in (5), is stored in the FIFO, and a packet output 1 is generated from the FIFO as shown in (6). Similarly, the packet output 2 is generated at the timing of R2 in (5), the packet output 3 is generated at R3, and the packet output 4 is generated at a fixed time interval. These packets are output for two cells (not including the header), and are input from the IP processing unit to the output processing unit (82 in FIG. 7). In this output processing unit, the input packet (for two cells) is converted into two ATM cells. At that time, an ATM header is added to each ATM cell, so that the data length is input as shown in (7) in FIG. Longer than the packet. Due to the operation of the output processing unit, the packet output 4 shown in (6) occurs continuously after the packet output 3 and the throughput is good.
[0030]
Next, FIG. 6 shows an example of optimization in the case where the packet input is composed of three cells. Referring to FIG. 7, the description will be given. From the ATM cell domain of FIG. Are input to the input processing unit (81 in FIG. 7) with respect to the cell cycle of (3). Each input of (2) contains three ATM cells each including an ATM header (5 bytes), and the input processing unit removes the ATM header of each ATM cell to form a packet (compatible with IP). The packet is converted and becomes the packet input 1, 2,... To the IP processing unit (83 in FIG. 7) as shown by (3) in FIG.
[0031]
In the IP processing unit, as shown in (4) in FIG. 6, the packet period is shorter than the cell period shown in (1) (shorter than the packet input shown in (3), the same period as (4) in FIG. 5). The operation is performed, and the access to the buffer memory (BM) including a plurality of SDRAMs is performed in a cycle of a combination of a write (Write), a refresh (Ref), and a read (Read) as shown in (5) of FIG. It is performed in the same cycle as the packet cycle.
[0032]
The packet input 1 indicated by (3) in FIG. 6 is written into the buffer memory (a plurality of SDRAMs) at the timing of W1-2 of (5) in FIG. 6, which is the first write operation after being stored in the FIFO. The next packet input 2 is written to the buffer memory at the timing of W2-2 of (5) in FIG. 6, and the packet input 3 is written to the buffer at the timing of W3-2 of (5) in FIG. Reading from the buffer memory is performed at the timing of R1-1, which is the read access shown in (5), and stored in the FIFO, and a packet output 1 shown in (6) is generated from the FIFO. Thereafter, at short intervals, a packet output 2 is generated at the timing of R2-1 in (5), and a packet output 3 is generated at the same timing of R3-1 at a short interval. These packet outputs are for three cells (not including the header) and are input from the IP processing unit to the output processing unit (82 in FIG. 7). In this output processing unit, the input packet (for three cells) is converted into three ATM cells. At that time, an ATM header is added to each ATM cell, so that the data length is input as shown in (7) in FIG. The packet length becomes longer than the packet and becomes a continuous signal.
[0033]
(Supplementary Note 1) In the packet transfer circuit in the IP over ATM, which includes an input processing unit for assembling an ATM cell into a packet, a packet processing unit for processing the packet, and an output processing unit for disassembling the packet into cells and transmitting the packet, The unit has a buffer memory composed of a plurality (n) of SDRAMs that can be accessed in parallel, a serial-parallel converter that receives input packets in series and outputs them in parallel, and a read-out circuit from the buffer memory. A parallel-to-serial converter for storing a plurality of parallel signals and generating an output packet in series, storing the packets in series in the serial-to-parallel converter, and outputting the parallel packet output to each SDRAM of the buffer memory , And an operation of storing a read signal from the SDRAM in the parallel-to-serial converter and the SDR. A packet transfer circuit in an IP over ATM, wherein three operations of an AM refresh operation are periodically processed asynchronously within a refresh period.
[0034]
(Supplementary Note 2) The packet transfer circuit in IP over ATM according to supplementary note 1, wherein the serial / parallel converter and the parallel / serial converter are configured by FIFO.
[0035]
(Supplementary note 3) The packet transfer circuit in the IP over ATM according to supplementary note 1, wherein a cycle of the asynchronous processing is a multiple of 48 bytes.
[0036]
(Supplementary Note 4) In Supplementary Note 1, the plurality of (n) SDRAMs each have a configuration in which a plurality (m) bits are accessed in parallel, and the input packet is input in series with a plurality (m) bit width. A serial-to-parallel converter that outputs in parallel, and a parallel-to-serial converter that stores a plurality of (n) parallel signals each having a plurality (m) bit width and read out from the buffer memory to generate an output packet in series A packet transfer circuit in IP over ATM, comprising a converter.
[0037]
(Supplementary Note 5) In the supplementary note 1, the length of the packet input / output to / from the buffer memory is set to the length of two ATM cells, and the packet processing cycle is set to two cell times of the ATM cell excluding the header. Packet transfer circuit in over ATM.
[0038]
(Supplementary Note 6) In the supplementary note 1, the length of the packet input / output to / from the buffer memory is set to three ATM cells, and the packet processing cycle is set to two ATM cell times excluding the header. Packet transfer circuit in IP over ATM.
[0039]
【The invention's effect】
According to the present invention, the SDRAM can be applied by performing the periodic processing in the IP processing circuit in the ATM network, so that downsizing and economy can be achieved.
[0040]
Further, by optimizing the periodic processing, the maximum transfer capability can be exhibited without deteriorating the transfer capability.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a diagram illustrating a configuration of an embodiment.
FIG. 3 is a diagram showing a control flow until a packet is output by performing buffer memory access by a control unit.
FIG. 4 is a diagram illustrating an example of a transfer operation when a processing cycle of a packet is set to two cell times.
FIG. 5 is a diagram illustrating an example (part 1) of a transfer operation when a packet processing cycle is optimized;
FIG. 6 is a diagram illustrating an example (part 2) of a transfer operation when a processing cycle of a packet is optimized.
FIG. 7 is a diagram showing a configuration example of a system to which the present invention is applied.
FIG. 8 is an explanatory diagram of a conventional buffer memory.
[Explanation of symbols]
1 Buffer memory 10-1 to 10-n SDRAM
2 serial-parallel converter 3 parallel-serial converter

Claims (4)

In a packet transfer circuit in IP over ATM comprising an input processing unit for assembling an ATM cell into a packet, a packet processing unit for processing the packet, and an output processing unit for disassembling the packet into cells and transmitting the cell,
The packet processing unit includes a buffer memory composed of a plurality (n) of SDRAMs that can be accessed in parallel,
A serial-to-parallel converter that receives input packets in series and outputs them in parallel; and a parallel-to-serial converter that stores a plurality of parallel signals read from the buffer memory and generates output packets in series. ,
After storing the packets in the serial-to-parallel converter in series, simultaneously writing the parallel packet output to each SDRAM of the buffer memory, storing the read signal from the SDRAM in the parallel-serial converter, and A packet transfer circuit in an IP over ATM, wherein three operations of a refresh operation of an SDRAM are asynchronously and cyclically processed within a refresh period. In claim 1,
A packet transfer circuit in IP over ATM, wherein the serial / parallel converter and the parallel / serial converter are configured by FIFO. In claim 1,
The plurality of (n) SDRAMs each have a configuration in which a plurality of (m) bits are accessed in parallel.
A serial-to-parallel converter in which the input packets are input in series with a plurality (m) bit width and output in parallel, and a plurality (n) each having a plurality (m) bit width read from the buffer memory A parallel-to-serial converter for storing parallel signals and generating output packets in series. In claim 1,
A packet transfer circuit in IP over ATM, characterized in that the length of a packet input / output to / from the buffer memory is the length of two ATM cells, and the packet processing cycle is two cell times of the ATM cell excluding the header.

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