JP2004079928A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004079928A
JP2004079928A JP2002241417A JP2002241417A JP2004079928A JP 2004079928 A JP2004079928 A JP 2004079928A JP 2002241417 A JP2002241417 A JP 2002241417A JP 2002241417 A JP2002241417 A JP 2002241417A JP 2004079928 A JP2004079928 A JP 2004079928A
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Japan
Prior art keywords
semiconductor device
semiconductor
resin layer
forming
wafer
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Pending
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JP2002241417A
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Japanese (ja)
Inventor
Munehiro Eguchi
江口　宗博
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2002241417A priority Critical patent/JP2004079928A/en
Publication of JP2004079928A publication Critical patent/JP2004079928A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which the peeling of a sealing resin layer from a semiconductor can be prevented and which can be protected from mechanical shocks, and to provide the semiconductor device. <P>SOLUTION: The method of manufacturing semiconductor device includes at least a step of forming groove sections on the main surface 1a of the semiconductor wafer 1 along the boundary faces of semiconductor elements, a step of forming the sealing resin layer, through which electrodes 2 and boundary lines 3 are exposed, after the groove sections are formed, and a step of only dicing the wafer 1 along the boundary lines 3. Consequently, the side faces of the semiconductor elements can also be covered with an insulating resin and, at the same time, only the wafer 1 can be diced efficiently through a small number of steps. In addition, since a resin layer is also formed on the backside of the wafer 1, the warping of the semiconductor device can be prevented and, at the same time, the semiconductor device can be protected from the mechanical shocks. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置およびその製造方法に係わるものである。
【０００２】
【従来の技術】
近年、電子装置の小型化、軽量化により、電子装置に組み込まれる半導体装置は高密度で実装が行われており、半導体装置には小型化、軽量化、および低価格化の要求が強くなっている。そこで近年、パッケージ工程をウェハ状態で行う方法が実用化されている。この方法では、ウェハ状態で半導体素子の表面を保護する封止樹脂層が形成される。これにより、半導体装置の製造コストを低減できるだけでなく、製造工程において回路形成面が汚染などから保護されるとともに、薄くてダメージを受けやすい半導体ウェハの取り扱いが容易になる。半導体ウェハは封止樹脂層の形成後、ダイシングブレードによって個片に分割される。
【０００３】
しかしながら、このようにして得られる半導体装置は側面および裏面が露出しているため、機械的な衝撃によってチッピングが起こりやすく、信頼性が乏しいといえる。
【０００４】
これを解決する手段として、特開２００１−１６８２３１号公報に提案がある。図４に特開２００１−１６８２３１号公報で開示された半導体装置１００の断面図を示す。１０１は半導体ウェハ、１１は半導体ウェハの主面に形成された電極、２０は絶縁層、２２は樹脂層である。また、半導体装置の製造方法は、半導体装置の側面１０ｂは主面１０ａとなす角が鈍角をなすように形成されている。次に、絶縁層２０が主面１０ａ上に加えて、側面１０ｂにも形成される。次に、裏面を研磨することにより側面１０ｂ上に形成された絶縁層２０を裏面１０ｃから露出させる。さらに、半導体ウェハ１０１の裏面上に樹脂層２２を形成する。そして最終的に個々の半導体装置に分割される。これによると半導体装置の側面および裏面が絶縁層で形成されているので、物理的な衝撃を緩和して半導体素子装置の側面を保護することができ、チッピングの発生を防止することができる。
【０００５】
【発明が解決しようとする課題】
しかしながら、特開２００１−１６８２３１号公報記載の半導体装置の製造方法は、半導体装置の側面および裏面を保護することはできるが、裏面１０ｃを研磨する際、絶縁層２０の残留応力によって半導体装置１００が反るという問題が生じる。この問題を、主面１０ａにバックグラインドテープを接着してから研磨することにより防いではいるが、研磨前にバックグラインドテープを貼り、研磨後にまたそのテープを剥がさなくてはいけないために工程が煩雑になる。
【０００６】
そこで、本発明が解決しようとする課題は、少ない工程数で効率よく半導体装置の側面および裏面を保護し、製造工程における封止樹脂膜と半導体ウェハとの剥がれおよび半導体ウェハの反りを防止でき、信頼性の向上を目的とした半導体装置を低コストで提供することである。
【０００７】
【課題を解決するための手段】
上記課題を解決するために、本発明の半導体装置は電極を有する複数の半導体素子が形成された半導体装置の主面、側面および裏面に封止機能を有する感光性樹脂層が形成されているものである。
【０００８】
このことで物理的な衝撃を緩和して半導体素子装置の側面および裏面を保護することができ、チッピングの発生を防止することができる。
【０００９】
次に本発明の半導体装置の製造方法は、電極を有する複数の半導体素子が形成された半導体ウェハの主面に個々の半導体装置に分割する境界線に沿って溝部を形成する工程を有し、この前記半導体ウェハの主面に個々の半導体装置に分割する境界線に沿って溝部を形成する工程の後に、前記主面、前記溝部の側面および裏面に半導体装置の境界線を露出させた封止機能を有する樹脂層を形成する工程を有し、この前記主面、前記溝部の側面および裏面に半導体装置の境界線を露出させた封止機能を有する樹脂層を形成する工程後に、前記半導体ウェハを露出した境界線に沿って個々の半導体装置にダイシングする工程を有するものである。また、ここでの樹脂層は感光性樹脂を用いるものである。
【００１０】
このことで効率よく少ない工程数で半導体装置の側面および裏面を保護でき、製造工程における封止樹脂膜と半導体ウェハとの剥がれおよび半導体ウェハの反りを防止できる。
【００１１】
【発明の実施の形態】
（実施の形態）
以下、本発明の実施の形態について、図１、図２および図３を用いて詳しく説明する。以下の図面においては、実質的に同一の機能を有する構成要素を同一の参照符号で示す。
【００１２】
図１に本発明の実施形態における半導体装置５０を模式的に示す断面図を示す。半導体装置５０は電極を有する半導体ウェハ１の主面１ａに絶縁樹脂層４と金属バンプ５を少なくとも有している。また、半導体装置５０の側面にも樹脂が形成されており、エピタキシャル層９を機械的なチッピングから保護している。
【００１３】
ここでの絶縁樹脂層４はノボラック樹脂を主材とした感光性樹脂を用いている。この感光性樹脂はエポキシ樹脂等に比べて耐湿性、密着性、絶縁性が優れていることから、半導体装置としての信頼性が向上できるとともに、樹脂層を薄くすることが可能となり、半導体装置の薄型化が期待できる。
【００１４】
なお、図２は図１の半導体装置の裏面にも絶縁樹脂層が形成されている半導体装置６０を模式的に示す断面図である。半導体装置６０は半導体装置５０に比べて、裏面にも樹脂層が形成されていることから、裏面を機械的な衝撃から保護することができ、信頼性を向上することができる。
【００１５】
図３に本発明における半導体装置の製造方法の工程図を示す。図は半導体ウェハの一部分を示したものである。図３（ａ）において、１は複数の半導体素子や集積回路からなる半導体ウェハである。半導体ウェハ１の主面１ａには外部接続用のアルミからなる電極２が形成されており、半導体ウェハをそれぞれ個片化するために境界線３が形成されている。次に図３（ｂ）に示すように、半導体ウェハ１の主面１ａから境界線３に沿い、例えばダイシングブレードを用いて、溝部６を構成する。この溝部６は半導体装置の側面にあるエピタキシャル層９を保護することを目的としており、このエピタキシャル層を樹脂層で覆うように溝部の大きさを構成する。ここでは深さ４０μｍ、幅６０μｍとした。次に図３（ｃ）に示すように、半導体ウェハ１の主面１ａに絶縁樹脂層４として感光性樹脂を塗布する。次に図３（ｄ）に示すように、フォトリソグラフィー技術を用いて電極２と境界線３を露出した絶縁樹脂層４が形成される。ここでは境界線の幅を２０μｍとし、溝部の両側面６ａには幅２０μｍの絶縁樹脂が形成される。その後、図３（ｅ）に示すように電極上部にバンプ５が例えば金属めっきで形成され、最後に図３（ｆ）に示すように境界線３に沿ってダイシングを行い、図３（ｇ）に示すように、個々の半導体装置に分割する。
【００１６】
本実施形態では、絶縁樹脂層４として感光性樹脂を使用することにより、フォトリソグラフィー技術による微細なパターニングが可能となり、境界線の樹脂を取り除くことができる。このことにより、少ない工程数で効率よく半導体装置の側面も封止樹脂で覆うことができるとともに、ウェハのみダイシングすることができる。このことにより、機械的な衝撃から半導体装置の側面を保護でき、製造工程における封止樹脂膜と半導体ウェハとの剥がれを防止できる。
【００１７】
裏面にも樹脂層を形成する場合においては、図示しないが、図３（ｃ）において、主面に絶縁樹脂層を形成する工程と同時に裏面にも絶縁樹脂層を形成する。次に図３（ｄ）において、裏面１ｂも同様に境界線３を露出した絶縁樹脂層４を形成する。この工程を含めることにより、主面、裏面とを同時に封止樹脂層４を形成することができ、半導体装置の反りを効果的に防ぐことができる。また、同一の封止樹脂層を用いていることから硬化収縮や熱膨張係数が等しくなり、半導体装置の反りをより効果的に防ぐことができる。
【００１８】
以上、本発明の実施の形態を示したが、本発明の実施の形態は上述した図面および記述に限定されるものではなく、例えば溝部の幅や深さを変化させるなど、趣旨に基づき種々の変形を行っても構わないことはいうまでもない。また、主面１ａと裏面１ｂの上部に形成する樹脂層はそれぞれ別の樹脂を利用しても構わない。
【００１９】
【発明の効果】
本発明の半導体装置によれば、半導体装置の側面および裏面にも樹脂層が形成されていることから、物理的な衝撃を緩和して、チッピングの発生を防止することができる。また、今回使用した感光性樹脂はエポキシ樹脂等に比べて耐湿性、密着性、絶縁性が優れていることから、半導体装置としての信頼性が向上できるとともに、樹脂層を薄くすることが可能となり、半導体装置の薄型化が期待できる。
【００２０】
また、絶縁樹脂として感光性樹脂を使用することにより、少ない工程数で効率よく半導体装置の側面および裏面に封止樹脂層を形成できる。また、半導体ウェハの電極形成面に境界線を露出した封止樹脂層を形成できるため、ウェハのみダイシングすることができる。よって、機械的な衝撃から半導体装置を保護することができ、封止樹脂と半導体ウェハとの密着性が確保できる。さらに、主面、裏面とを同時に封止樹脂層を形成できることから、半導体装置の反りを防ぐことができる。
【図面の簡単な説明】
【図１】本発明の実施形態における半導体装置５０を模式的に示す断面図
【図２】本発明の実施形態における半導体装置６０を模式的に示す断面図
【図３】（ａ）〜（ｇ）は本発明の実施形態における半導体装置の製造方法を説明するための工程断面図
【図４】従来の半導体装置の製造法で得られた半導体装置の断面説明図
【符号の説明】
１、１０１　半導体ウェハ
１ａ　半導体ウェハの主面
２、１１　電極
３　境界線
４、２０　絶縁樹脂層
５　金属バンプ
６　溝部
６ａ　溝部側面
７　酸化膜
８　窒化膜
９　エピタキシャル層
２２　樹脂層
５０、６０、１００　半導体装置[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as electronic devices have become smaller and lighter, semiconductor devices incorporated in electronic devices have been mounted at higher density, and demands for smaller, lighter, and lower cost semiconductor devices have increased. I have. Therefore, in recent years, a method of performing the packaging process in a wafer state has been put to practical use. In this method, a sealing resin layer for protecting the surface of the semiconductor element in a wafer state is formed. This not only reduces the manufacturing cost of the semiconductor device, but also protects the circuit formation surface from contamination and the like in the manufacturing process, and facilitates the handling of a thin and easily damaged semiconductor wafer. After the formation of the sealing resin layer, the semiconductor wafer is divided into individual pieces by a dicing blade.
[0003]
However, since the side and back surfaces of the semiconductor device thus obtained are exposed, chipping is likely to occur due to mechanical impact, and the reliability is poor.
[0004]
As means for solving this, there is a proposal in JP-A-2001-168231. FIG. 4 is a sectional view of a semiconductor device 100 disclosed in Japanese Patent Application Laid-Open No. 2001-168231. 101 is a semiconductor wafer, 11 is an electrode formed on the main surface of the semiconductor wafer, 20 is an insulating layer, and 22 is a resin layer. Further, in the method of manufacturing a semiconductor device, the side surface 10b of the semiconductor device is formed such that the angle formed with the main surface 10a is obtuse. Next, the insulating layer 20 is formed on the side surface 10b in addition to the main surface 10a. Next, the insulating layer 20 formed on the side surface 10b is exposed from the back surface 10c by polishing the back surface. Further, a resin layer 22 is formed on the back surface of the semiconductor wafer 101. Then, the semiconductor device is finally divided into individual semiconductor devices. According to this, since the side surface and the back surface of the semiconductor device are formed of the insulating layer, the physical impact can be reduced, the side surface of the semiconductor element device can be protected, and the occurrence of chipping can be prevented.
[0005]
[Problems to be solved by the invention]
However, the method for manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. 2001-168231 can protect the side surface and the back surface of the semiconductor device, but when polishing the back surface 10c, the semiconductor device 100 The problem of warpage arises. Although this problem is prevented by attaching a back grinding tape to the main surface 10a and then polishing, the process is complicated because the back grinding tape must be applied before polishing and the tape must be removed after polishing. become.
[0006]
Therefore, the problem to be solved by the present invention is to efficiently protect the side surface and the back surface of the semiconductor device with a small number of steps, to prevent peeling of the sealing resin film from the semiconductor wafer and warpage of the semiconductor wafer in the manufacturing process, An object of the present invention is to provide a semiconductor device for improving reliability at low cost.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor device of the present invention has a plurality of semiconductor elements having electrodes, and has a main surface, a side surface, and a back surface on which a photosensitive resin layer having a sealing function is formed. It is.
[0008]
Thus, physical impact can be reduced to protect the side surface and the back surface of the semiconductor element device, and occurrence of chipping can be prevented.
[0009]
Next, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a groove along a boundary line dividing the individual semiconductor device on a main surface of a semiconductor wafer on which a plurality of semiconductor elements having electrodes are formed, After the step of forming a groove on the main surface of the semiconductor wafer along a boundary line for dividing the semiconductor device into individual semiconductor devices, sealing is performed by exposing the boundary line of the semiconductor device on the main surface, the side surface and the back surface of the groove portion. Forming a resin layer having a function, and forming a resin layer having a sealing function exposing a boundary line of a semiconductor device on the main surface, the side surface and the back surface of the groove, and then forming the semiconductor wafer. Is diced into individual semiconductor devices along the exposed boundaries. Further, the resin layer here uses a photosensitive resin.
[0010]
As a result, the side surface and the back surface of the semiconductor device can be efficiently protected with a small number of steps, and peeling of the sealing resin film from the semiconductor wafer and warpage of the semiconductor wafer in the manufacturing process can be prevented.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1, 2, and 3. FIG. In the drawings, components having substantially the same function are denoted by the same reference numerals.
[0012]
FIG. 1 is a sectional view schematically showing a semiconductor device 50 according to an embodiment of the present invention. The semiconductor device 50 has at least an insulating resin layer 4 and a metal bump 5 on a main surface 1a of a semiconductor wafer 1 having electrodes. A resin is also formed on the side surface of the semiconductor device 50 to protect the epitaxial layer 9 from mechanical chipping.
[0013]
Here, the insulating resin layer 4 uses a photosensitive resin mainly composed of a novolak resin. This photosensitive resin has better moisture resistance, adhesion, and insulation than epoxy resin and the like, so that the reliability as a semiconductor device can be improved and the resin layer can be made thinner. Thinning can be expected.
[0014]
FIG. 2 is a cross-sectional view schematically showing a semiconductor device 60 in which an insulating resin layer is also formed on the back surface of the semiconductor device of FIG. Since the semiconductor device 60 has a resin layer also formed on the back surface as compared with the semiconductor device 50, the back surface can be protected from mechanical shock, and the reliability can be improved.
[0015]
FIG. 3 shows a process chart of a method for manufacturing a semiconductor device according to the present invention. The figure shows a part of a semiconductor wafer. In FIG. 3A, reference numeral 1 denotes a semiconductor wafer including a plurality of semiconductor elements and integrated circuits. An electrode 2 made of aluminum for external connection is formed on the main surface 1a of the semiconductor wafer 1, and a boundary line 3 is formed to singulate the semiconductor wafer. Next, as shown in FIG. 3B, a groove 6 is formed along the boundary 3 from the main surface 1a of the semiconductor wafer 1 using, for example, a dicing blade. The purpose of the groove 6 is to protect the epitaxial layer 9 on the side surface of the semiconductor device, and the size of the groove is configured so as to cover the epitaxial layer with a resin layer. Here, the depth is 40 μm and the width is 60 μm. Next, as shown in FIG. 3C, a photosensitive resin is applied as the insulating resin layer 4 to the main surface 1a of the semiconductor wafer 1. Next, as shown in FIG. 3D, an insulating resin layer 4 exposing the electrode 2 and the boundary 3 is formed by using a photolithography technique. Here, the width of the boundary line is set to 20 μm, and an insulating resin having a width of 20 μm is formed on both side surfaces 6a of the groove. Thereafter, as shown in FIG. 3E, a bump 5 is formed on the electrode by, for example, metal plating, and finally, dicing is performed along the boundary 3 as shown in FIG. As shown in the figure, the semiconductor device is divided into individual semiconductor devices.
[0016]
In the present embodiment, by using a photosensitive resin as the insulating resin layer 4, fine patterning by photolithography becomes possible, and the resin at the boundary can be removed. Thus, the side surface of the semiconductor device can be efficiently covered with the sealing resin in a small number of steps, and dicing can be performed only on the wafer. Thus, the side surface of the semiconductor device can be protected from mechanical shock, and peeling of the sealing resin film and the semiconductor wafer in the manufacturing process can be prevented.
[0017]
In the case where the resin layer is also formed on the back surface, although not shown, in FIG. 3C, the insulating resin layer is formed on the back surface simultaneously with the step of forming the insulating resin layer on the main surface. Next, in FIG. 3D, an insulating resin layer 4 having the boundary line 3 exposed is similarly formed on the back surface 1b. By including this step, the sealing resin layer 4 can be formed on the main surface and the back surface at the same time, and the warpage of the semiconductor device can be effectively prevented. Further, since the same sealing resin layer is used, the curing shrinkage and the thermal expansion coefficient become equal, and the warpage of the semiconductor device can be more effectively prevented.
[0018]
As described above, the embodiment of the present invention has been described. However, the embodiment of the present invention is not limited to the above-described drawings and description. For example, various widths and depths of the groove portion are changed based on the purpose. It goes without saying that deformation may be performed. Further, different resin may be used for the resin layer formed on the main surface 1a and the upper surface of the back surface 1b.
[0019]
【The invention's effect】
According to the semiconductor device of the present invention, since the resin layer is also formed on the side surface and the back surface of the semiconductor device, physical impact can be reduced and occurrence of chipping can be prevented. In addition, the photosensitive resin used this time has better moisture resistance, adhesion, and insulation than epoxy resin, etc., which can improve the reliability as a semiconductor device and make the resin layer thinner. In addition, thinning of a semiconductor device can be expected.
[0020]
Further, by using a photosensitive resin as the insulating resin, the sealing resin layer can be efficiently formed on the side surface and the back surface of the semiconductor device with a small number of steps. In addition, since a sealing resin layer having a boundary line exposed on the electrode forming surface of the semiconductor wafer can be formed, only the wafer can be diced. Therefore, the semiconductor device can be protected from mechanical shock, and the adhesion between the sealing resin and the semiconductor wafer can be ensured. Further, since the sealing resin layer can be formed on the main surface and the back surface at the same time, warpage of the semiconductor device can be prevented.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically illustrating a semiconductor device 50 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating a semiconductor device 60 according to an embodiment of the present invention. 4) is a process sectional view for explaining the method of manufacturing the semiconductor device according to the embodiment of the present invention. [FIG. 4] A sectional view of the semiconductor device obtained by the conventional method of manufacturing a semiconductor device [Description of symbols]
DESCRIPTION OF SYMBOLS 1, 101 Semiconductor wafer 1a Main surface 2, 11 of semiconductor wafer Electrode 3 Boundary 4, 20 Insulating resin layer 5 Metal bump 6 Groove 6a Groove side 7 Oxide film 8 Nitride film 9 Epitaxial layer 22 Resin layers 50, 60, 100 Semiconductor apparatus

Claims (7)

電極が形成された半導体素子の主面および側面に封止機能を有する感光性樹脂層が形成されていることを特徴とする半導体装置。A semiconductor device, wherein a photosensitive resin layer having a sealing function is formed on a main surface and a side surface of a semiconductor element on which an electrode is formed. 前記半導体素子裏面に封止機能を有する感光性樹脂層が形成されていることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a photosensitive resin layer having a sealing function is formed on the back surface of the semiconductor element. 電極を有する複数の半導体素子が形成された半導体ウェハの主面に個々の半導体素子に分割する境界線に沿って溝部を形成する工程と、前記主面および前記溝部の側面上に半導体装置の境界線を露出させた封止機能を有する樹脂層を形成する工程と、露出した境界線に沿って前記半導体ウェハを個々の半導体装置にダイシングする工程とを有することを特徴とする半導体装置の製造方法。Forming a groove on a main surface of a semiconductor wafer on which a plurality of semiconductor elements having electrodes are formed along a boundary dividing the semiconductor device into individual semiconductor elements; and forming a boundary of a semiconductor device on a side surface of the main surface and the groove. Forming a resin layer having a sealing function with exposed lines, and dicing the semiconductor wafer into individual semiconductor devices along exposed boundaries. . 前記半導体ウェハの主面に個々の半導体装置に分割する境界線に沿って溝部を形成する工程後に、前記主面および前記溝部の側面に半導体装置の境界線を露出させた封止機能を有する樹脂層を形成する工程を有し、この前記主面および前記溝部の側面に半導体装置の境界線を露出させた封止機能を有する樹脂層を形成する工程後に、前記半導体ウェハを露出した境界線に沿って個々の半導体装置にダイシングする工程を有することを特徴とする請求項３記載の半導体装置の製造方法。A resin having a sealing function of exposing a boundary line of a semiconductor device on the main surface and a side surface of the groove after a step of forming a groove along a boundary dividing the semiconductor device into individual semiconductor devices on the main surface of the semiconductor wafer A step of forming a layer, and after forming a resin layer having a sealing function exposing a boundary line of the semiconductor device on the side surfaces of the main surface and the groove portion, the semiconductor wafer is exposed to the boundary line. 4. The method for manufacturing a semiconductor device according to claim 3, further comprising a step of dicing the semiconductor device into individual semiconductor devices. 前記半導体ウェハの裏面に個々の半導体素子に分割する境界線を露出させた樹脂層を形成する工程を含むことを特徴とした請求項３記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of forming a resin layer on a back surface of the semiconductor wafer, exposing a boundary line for dividing into individual semiconductor elements. 前記半導体ウェハの主面に個々の半導体素子に分割する境界面に沿って溝部を形成する工程後に、前記主面、前記溝部の側面および裏面に半導体装置の境界線を露出させた封止機能を有する樹脂層を形成する工程を有し、この前記主面、前記溝部の側面および裏面に個々の半導体装置に分割する境界線を露出させた封止機能を有する樹脂層を形成する工程後に、前記半導体ウェハを露出した境界線に沿って個々の半導体装置にダイシングする工程を有することを特徴とする請求項５記載の半導体装置の製造方法。After the step of forming a groove on the main surface of the semiconductor wafer along a boundary surface to be divided into individual semiconductor elements, the main surface, a sealing function of exposing a boundary line of the semiconductor device on the side surface and the back surface of the groove portion. Having a step of forming a resin layer having a sealing function of exposing boundaries dividing the individual semiconductor devices on the side surfaces and the back surface of the trenches, 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of dicing the semiconductor wafer into individual semiconductor devices along an exposed boundary line. 前記記載の樹脂層は感光性樹脂を用いることを特徴とする請求項３、請求項４、請求項５および請求項６記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 3, wherein said resin layer uses a photosensitive resin.
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Cited By (4)

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US7387945B2 (en) 2004-05-11 2008-06-17 Seiko Epson Corporation Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same
JP2008141021A (en) * 2006-12-01 2008-06-19 Rohm Co Ltd Semiconductor device and manufacturing method of the semiconductor device
JP2009267331A (en) * 2008-03-31 2009-11-12 Casio Comput Co Ltd Semiconductor device and manufacturing method therefor
US8587124B2 (en) 2007-09-21 2013-11-19 Teramikros, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same

Cited By (9)

* Cited by examiner, † Cited by third party
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US7387945B2 (en) 2004-05-11 2008-06-17 Seiko Epson Corporation Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same
JP2008141021A (en) * 2006-12-01 2008-06-19 Rohm Co Ltd Semiconductor device and manufacturing method of the semiconductor device
US8587124B2 (en) 2007-09-21 2013-11-19 Teramikros, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same
US8871627B2 (en) 2007-09-21 2014-10-28 Tera Probe, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same
US9070638B2 (en) 2007-09-21 2015-06-30 Tera Probe, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same
US9640478B2 (en) 2007-09-21 2017-05-02 Aoi Electronics Co., Ltd. Semiconductor device having low dielectric insulating film and manufacturing method of the same
JP2009267331A (en) * 2008-03-31 2009-11-12 Casio Comput Co Ltd Semiconductor device and manufacturing method therefor
JP4666028B2 (en) * 2008-03-31 2011-04-06 カシオ計算機株式会社 Semiconductor device
US8154133B2 (en) 2008-03-31 2012-04-10 Casio Computer Co., Ltd. Semiconductor device having low dielectric constant film and manufacturing method thereof

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