JP2004079914A - Electronic component mounting reliability prediction method and its prediction system - Google Patents

Electronic component mounting reliability prediction method and its prediction system Download PDF

Info

Publication number
JP2004079914A
JP2004079914A JP2002241111A JP2002241111A JP2004079914A JP 2004079914 A JP2004079914 A JP 2004079914A JP 2002241111 A JP2002241111 A JP 2002241111A JP 2002241111 A JP2002241111 A JP 2002241111A JP 2004079914 A JP2004079914 A JP 2004079914A
Authority
JP
Japan
Prior art keywords
reliability
solder joint
amount
positional relationship
storage unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002241111A
Other languages
Japanese (ja)
Other versions
JP3900042B2 (en
Inventor
Satoshi Iwazu
岩津 聡
Koichi Shiozawa
塩沢 宏一
Hiroko Shimada
嶋田 裕子
Kazuko Yamagishi
山岸 和子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2002241111A priority Critical patent/JP3900042B2/en
Publication of JP2004079914A publication Critical patent/JP2004079914A/en
Application granted granted Critical
Publication of JP3900042B2 publication Critical patent/JP3900042B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the need of preparing an FEM model for every reliability evaluation and to easily and quickly predict the reliability service life of a solder joint inside an electronic appliance. <P>SOLUTION: A method is for predicting the mounting reliability of CSP to a mounting board of the electronic appliance provided with the mounting board and composed by respectively attaching the CSP through a solder bump to both opposing surfaces of the substrate. The method comprises a process of obtaining a distortion amount generated at the solder bump corresponding to position relation between the CSP, and preparing a response surface for three-dimensionally displaying the distortion amount corresponding to the position relation between the CSP beforehand; and a process of arbitrarily setting the position relation between the CSP, applying the set position relation to the response surface, and calculating the distortion amount generated at the solder bump. The reliability service life of the solder bump is easily and quickly predicted. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
この発明は、実装基板の両面にはんだバンプを介してCSP(Chip Size Package)が取り付けられて成る電子機器の信頼性評価に適用して好適な電子部品の実装信頼性予測方法及びその予測システムに関するものである。詳しくは、両面実装タイプの基板に対する電子部品の実装信頼性を予測する方法であって、予め、はんだ接合部に生じる歪量を電子部品間の位置関係に対応させて求めておくと共に、この歪量を電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面を作成しておくことによって、電子機器内のはんだ接合部の信頼性寿命を容易、かつ迅速に予測できるようにしたものである。
【0002】
【従来の技術】
近年、半導体パッケージ等の電子部品は、電子機器の小型軽量化に伴って年々小型化されつつある。その為、半導体パッケージのプリント実装基板へ接合する部分も小型化され、半導体パッケージと実装基板間の熱膨張率の差によって生じる熱ストレスに対して、半導体パッケージの実装信頼性を十分にする為の構造上の設計マージンが少なくなってきている。
【0003】
熱ストレスに対して十分に信頼性を保証する為には、様々な信頼性試験が必要となる。特に、CSPと呼ばれる、シリコンチップと大きさが殆ど変わらないように設計される半導体パッケージの場合、電気的接合も兼ねるはんだバンプに熱歪がかかるので、その信頼性を保証する試験は重要である。その為、各半導体メーカーやそれを使うセットメーカーでは恒温槽にCSPを実装した試験基板を投入し、温度を上下動させ実使用に耐える信頼性保証試験を行っている。
【0004】
両面実装基板に実装されるCSPの信頼性を保証する場合も、上述のケースと同様に両面実装タイプの試験基板にCSPを表裏両面に実装してその保証試験を実施している。信頼性保証をする為のCSPの試験には、2段階あり、1段階目は、試験基板上での信頼性確認であるが、2段階目は実際の製品と同じ状態での信頼性確認試験である。
【0005】
両面実装の場合は、実装基板での表と裏のCSPの配置状況により、CSPの実装信頼性が変化する事が知られており、片面試験の場合よりも、試験基板上での信頼性結果から実装基板上での信頼性を予測する事が難しい。裏面に配置されるCSPの位置・大きさによっては、1段階目の試験基板でOKでも2段階目の実装基板では信頼性試験で合格とならない場合が多くある。
【0006】
その場合、実装基板の材質・厚み・電子部品の配置等さまざまな設計ファクタで熱歪の影響低減を図り、設計変更をして製品化する事になる。しかしながら、昨今、製品の設計サイクルはますます短くなってきており、実装基板上での確認段階での設計変更は、一旦決定した仕様の変更につながる。これは、製品の設計期間を長期化させてしまい、開発・製造コストの上昇を招いてしまう。
【0007】
一方で、数値計算手法による半導体パッケージのはんだ接合部の寿命予測手法として、Coffin−Manson則等の疲労寿命式に基づいた予測法が知られている。
【0008】
この予測法は、基板と半導体パッケージ間で熱による膨張率が違う為に生じるはんだ接合部の塑性歪やクリープ歪の振幅量を有限要素法(Finite Element Method:以下で、FEM手法ともいう)から求めると共に、求めた歪の振幅量をCoffin−Manson則の疲労寿命式に当てはめて、はんだ接合部の信頼性寿命を予測する方法である。
【0009】
このFEM手法では、CSPの各構成部位ごとの形状・材料特性(ヤング率、ポアソン比、線膨張率等)をPre−Postプロセッサと呼ばれる専用ツールに数値入力して、図11に示すようなFEMモデル70を作成する。そして、このFEMモデル70に基づいて、例えば温度がある一定の範囲内で上下動した際に、CSP50A及び50Bの各構成部位ごとの形状・材料特性が、はんだバンプ75A及び75B等の接合部に及ぼす影響を算出する。
【0010】
はんだバンプ75A及び75Bの信頼性寿命は、バンプの形状、バンプの数・配置、内蔵されるシリコンチップの大きさ、厚さ、パッケージ全体の厚み・モールド(Mold)樹脂の剛性・線膨張率、インターポーザ基板(IP)の材質・厚み、パッケージの大きさ、実装基板の厚み・剛性・線膨張率に左右される。
【0011】
【発明が解決しようとする課題】
ところで、従来例に係るCSPの実装信頼性の予測方法によれば、CSP50A及び50Bの各構成部位ごとの形状・材料特性(ヤング率、ポアソン比、線膨張率等)をPre−Postプロセッサと呼ばれる専用ツールに数値入力してFEMモデル70を作成していた。
【0012】
そして、このFEMモデル70に基づいて、例えば温度がある一定の範囲内で上下動した場合に、CSP50A及び50Bの各構成部位ごとの形状・材料特性が、はんだバンプ75A及び75B等の接合部に及ぼす影響を算出していた。
【0013】
このため、従来例に係る実装信頼性の予測方法では、モデル定義の仕方(例えばFEMモデルの細かさ、計算の境界条件等)がオペレータ等によって異なると、パラメータ変数を同じ値に数値入力しても異なる予測結果が導き出されてしまうといった問題があった。
【0014】
即ち、FEM手法では、実装基板やはんだバンプの断面及び表面をメッシュで区分し、メッシュの節点を選択しながらFEMモデル70を構築する為、専用のPre−Postプロセッサを使用する必要があり、その操作に熟練した者、又は一定の知識を持つ専門の解析者がこのPre−Postプロセッサを操作しないと正しい解が導き出せないという不便さがある。それゆえ、従来例に係る予測方法では、CSP50A及び50Bの実装信頼性の予測は必ずPre−Postプロセッサを操作可能な専門の技術者が行う必要があった。
【0015】
また、上述したFEM手法は、熱ストレス(応力)等によってメッシュの節点がどれだけ変位するかを繰り返し計算するものであり、特にクリープ歪の算出は歪量を経過時間に沿って積分して求めていかなければならないので、計算処理に一定の時間を要してしまう。
【0016】
このため、CSP50A及び50Bの配置設計(フロアレイアウト)を決定した後に、パラメータ変数をPre−Postプロセッサに入力してFEMモデル70を作成し、その実装信頼性を予測するまでには、かなりの長時間を要してしまい、CSP50A及び50Bのフロアレイアウトと実装信頼性の関係をリアルタイムに把握することはできなかった。
【0017】
また、CSP50A及び50Bのフロアレイアウトを変更する場合には、上述したFEMモデル70を作成し直す必要があるので、CSP(以下で、電子部品ともいう)の実装信頼性の予測にはさらに時間を要してしまうという問題があった。
【0018】
そこで、この発明はこのような問題を解決したものであって、FEMモデルを信頼性評価毎にいちいち作成しなくても済むようにすると共に、電子機器内のはんだ接合部の信頼性寿命を容易、かつ迅速に予測できるようにした電子部品の実装信頼性予測方法及びその予測システムの提供を目的とする。
【0019】
【課題を解決するための手段】
上述した課題は、配線用の基板を有し当該基板の対向する両面にはんだ接合部を介して電子部品がそれぞれ取り付けられて成る電子機器の、当該基板に対する該電子部品の実装信頼性を予測する方法であって、予め、このはんだ接合部に生じる歪量を電子部品間の位置関係に対応させて求めておくと共に、当該歪量を該電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面を作成しておく工程と、この電子部品間の位置関係を任意に設定し、設定された位置関係を応答曲線又は応答曲面に当てはめてはんだ接合部に生じる歪量を算出する工程とを有することを特徴とする電子部品の実装信頼性予測方法によって解決される。
【0020】
本発明に係る電子部品の実装信頼性予測方法によれば、電子機器に対応したFEMモデルを信頼性評価毎にいちいち作成する手間を省くことができ、はんだ接合部の信頼性寿命を容易、かつ迅速に予測することができる。
【0021】
本発明に係る電子部品の実装信頼性予測システムは、配線用の基板を有し当該基板の対向する両面にはんだ接合部を介して電子部品がそれぞれ取り付けられて成る電子機器の、当該基板に対する該電子部品の実装信頼性を予測するシステムであって、このはんだ接合部に生じる歪量を電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面を格納するモデル格納部と、電子部品間の任意の位置関係情報を格納する位置情報格納部と、この位置情報格納部に格納された位置関係情報をモデル格納部に格納された応答曲線又は応答曲面に入力して、はんだ接合部に生じる歪量を算出する演算処理部とを備えたものである。
【0022】
本発明に係る電子部品の実装信頼性予測システムによれば、はんだ接合部に生じる歪量を電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面に、当該電子部品間の任意の位置関係情報が入力されて、はんだ接合部に生じる歪量が算出される。
【0023】
従って、従来方式と比べて、電子機器内のはんだ接合部の歪量を求めるために、当該電子機器に対応したFEMモデルを信頼性評価毎にいちいち作成しなくても済むので、信頼性評価に要する時間を大幅に短縮できる。
【0024】
【発明の実施の形態】
以下、図面を参照しながら本発明の実施形態に係る電子部品の実装信頼性予測方法及びその予測システムについて説明する。
【0025】
この実施形態では、配線用の基板を有し当該基板の対向する両面にはんだ接合部を介して電子部品がそれぞれ取り付けられて成る電子機器の、当該基板に対する該電子部品の実装信頼性を予測する際に、予め、はんだ接合部に生じる歪量を電子部品間の位置関係に対応させて求めておくと共に、当該歪量を該電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面を作成しておくことによって、FEMモデルを信頼性評価毎にいちいち作成しなくても済むようにすると共に、電子機器内のはんだ接合部の信頼性寿命を容易、かつ迅速に予測できるようにしたものである。
【0026】
まず始めに、本発明の実施形態に係る電子部品の実装信頼性予測システムについて説明する。
【0027】
図1は本発明の実施形態に係る電子部品の実装信頼性予測システム100の構成例を示すブロック図である。この実装信頼性予測システム100は、実装基板(配線用の基板の一例)を有し、当該基板の対向する両面にはんだバンプ(はんだ接合部の一例)を介してCSP等の半導体パッケージ(電子部品の一例)がそれぞれ取り付けられて成る電子機器において、その実装基板とCSP間の実装信頼性を予測するシステムである。
【0028】
図1に示すように、この実装信頼性予測システム(以下で、単に予測システムともいう)100は、パラメータ格納部(位置情報格納部の一例)11と、モデル格納部13と、疲労寿命式格納部15と、実験データ格納部17と、歪量格納部19と、信頼性データ格納部21と、CPU23と、ROM25及びモニタ27等から構成される。
【0029】
図1に示すパラメータ格納部11には、実装基板の両面に取り付けられるCSP間の位置関係や、CSPの形状と材料特性と、はんだバンプの形状及び材料特性等のパラメータ変数(以下で、単にパラメータともいう)が数値入力される。図2はパラメータ格納部11に格納されるパラメータ及びその設定範囲の一例を示す表図である。図2に示す各々のパラメータがその上下限の範囲内で数値設定され、パラメータ格納部11に格納される。このパラメータ格納部11は、例えばRAM(Random Access Memory)で構成される。
【0030】
モデル格納部13には、はんだバンプに生じる塑性歪及びクリープ歪等を実装基板の両面に取り付けられるCSP間の位置関係(ΔX、ΔY)に対応させて3次元的に表示する応答曲面が格納される。
【0031】
図3は応答曲面の一例を示す表図である。図3のX軸は、CSP50Aの中心点に対する、CSP50Bの中心点のX方向への相対的な位置ずれ量(ΔX)である。また、図3のY軸は、CSP50Aの中心点に対する、CSP50Bの中心点のY方向への相対的な位置ずれ量(ΔY)である。また、図3のZ軸は、例えば−25℃〜125℃の温度範囲でTC(Thermal Cycle)試験を1サイクル行った際のはんだバンプの歪量(以下で、非線形歪振幅量ともいう)である。
【0032】
図3に示す応答曲面は、例えば図5の▲1▼式で表される。▲1▼式において、変数X、Xは各パラメータを一般表記したものである。また、変数Yは上述したはんだバンプの非線形歪振幅量であり、β、β、βii、βij・・・はパラメータに応じた定数である。▲1▼式にCSP間の位置関係(ΔX、ΔY)をX、Xとして数値代入すると、当該位置関係に対応するはんだバンプの非線形歪振幅量が算出される。この応答曲面の作成方法については、後述する。
【0033】
図1に示すモデル格納部13は、例えばハードディスク(HDD)等の大容量記憶装置によって構成される。また、図1に示す歪量格納部19には、応答曲面から算出された非線形歪振幅量が格納される。この歪量格納部19は、例えばRAMで構成される。
【0034】
図1において、実験データ格納部17には、2個以上のCSPがはんだバンプを介して両面に取り付けられた実験用の基板上でのTC試験の結果、即ち、実験基板上で測定されるはんだバンプの非線形歪振幅量と信頼性寿命値(TC試験でのサイクル数)とが格納される。この実験データ格納部17は、例えばRAMで構成される。
【0035】
疲労寿命式格納部15には、例えば図5の▲2▼式に示すようなCoffin−Manson則の疲労寿命式が格納される。▲2▼式において、Yははんだバンプの非線形歪振幅量であり、εは疲労寿命特性である。この疲労寿命特性εは、個々のはんだバンプの形状に左右される値である。また、Nは熱サイクル寿命(はんだバンプの信頼性寿命値:cycle)である。▲2▼式の両辺を対数で表示すると図4に示す対数グラフを得ることができる。
【0036】
図4の横軸はNの対数であり、縦軸はYの対数である。図4に示すグラフ(線分)の傾きは、はんだバンプの材料特性によって異なるものである。例えば、Sn−Pb共晶はんだの場合は、−0.5程度である。また、このグラフ(線分)の高さは、疲労寿命特性εに依存して変動する。このようなCoffin−Manson則の式を格納する疲労寿命式格納部15は、例えばHDDである。
【0037】
ところで、図5の▲3▼式は、図5の▲2▼式と同様Coffin−Manson則の疲労寿命式である。▲3▼式において、Nは実験基板上でのTC試験の実験結果であり、はんだバンプの信頼性寿命値(cycle)である。また、Yは、実験基板上でのTC試験の実験結果であり、はんだバンプの非線形歪振幅量である。即ち、N及びYは既知のデータなので、▲3▼式よりεの値を求めることができる。実験基板上でも、はんだバンプの形状は実装基板上のものと同一であるため、▲3▼式で求めたεは▲2▼式のεに等しい。
【0038】
従って、▲3▼式より求めたεと、▲1▼式(応答曲面)より求めたはんだバンプの非線形歪振幅量Yとを▲2▼式に数値代入することによって、実装基板上でのはんだバンプの信頼性寿命値Nを得ることができる。
【0039】
図1に示す信頼性データ格納部21には、この信頼性寿命値Nが格納される。この信頼性データ格納部21は、例えばRAMである。この信頼性データ格納部21に格納されたはんだバンプの信頼性寿命値Nは、当該予測システム100の外部へ出力可能になされている。
【0040】
この予測システム100は、上述したパラメータ格納部11と、モデル格納部13と、疲労寿命式格納部15と、実験データ格納部17と、歪量格納部19と、信頼性データ格納部21とで格納部本体60を構成している。
【0041】
図1に示すCPU23は、格納部本体60を構成する各格納部からデータや計算式を読み込み、所定の計算処理を行い、その計算結果を格納部本体60に書き込むように動作する。また、ROM(Read Only Memory)25には、このCPU23用の動作プログラムが格納されている。さらに、モニタ27には、格納部本体60に格納された各データが任意に表示される。
【0042】
次に、上述したモデル格納部13に格納される応答曲面の作成方法について説明する。図3に示した応答曲面は多数の点で構成されている。この応答曲面を構成する一点一点は、はんだバンプの形状・数・配置、内蔵されるシリコンチップの大きさ・厚さ、パッケージ全体の大きさ・厚み、モールド樹脂の剛性・線膨張率、インターポーザの材質・厚み、実装基板の厚み・剛性・線膨張率等のパラメータに基づいて有限要素法(FEM手法)で算出する。
【0043】
但し、応答曲面に高精度・高範囲を求めるあまり、この応答曲面のパラメータ数やその変数範囲をむやみに増やしていくと、非線形歪振幅量のサンプリング数が膨大になってしまい、応答曲面の作成に長時間を要してしまうという問題も生じてくる。
【0044】
そこで、この実施例では、例えば、ポアソン比のように、通常0.3〜0.4のようにある幅で決まっている特性については、その平均的な値で固定する。また、実際のCSPのインターポーザ基板(IP)は、ポリイミド材又は、FR−4材の2種類が多い為、その材質も2水準(種類)に限定する。さらに、IPの厚さは、例えばポリイミド材ならば0.07mm、FR−4材ならば0.2mmと0.4mmが標準仕様なので、ポリイミド材の厚みを1水準に、FR−4材の厚みを2水準に限定する。
【0045】
また、応答曲面を構成するパラメータの中で、はんだバンプの信頼性寿命に関する感度の低いパラメータを平均的な値で固定し、感度の高いパラメータのみを絞り込む。これにより、応答曲面を構成するパラメータを効果的に削減でき、応答曲面の作成を容易にすることができる。
【0046】
ところで、このパラメータの絞り込みには、DOE手法(田口メソッド)を使う事ができる。例えば、図6はL12と呼ばれる、2水準、パラメータを7個にした感度解析の結果である。図6の横軸が水準(2水準を−1,1で表示)であり、縦軸がはんだバンプの非線形歪振幅量(歪量)である。
【0047】
図6から明らかなように、CSP間の相対位置ΔXと相対位置ΔYが、はんだバンプの信頼性寿命に関する感度が高く、Mold樹脂厚みは低い。従って、Mold樹脂厚みは、一般的なCSPの平均値に固定しても、計算結果にあまり違いはないことがわかる。これにより、Mold樹脂厚みをパラメータから除外して平均的な値で固定することも可能である。
【0048】
この実施例では、上述した方法によって応答曲面を構成するパラメータを絞り込み、図2に示したように、応答曲面を構成するパラメータを実装基板の形状及び材料特性と、CSPの形状及び材料特性と、CSP間の相対位置(位置関係)とした。また、実際にその使用が想定されうる材料特性や形状、レイアウト等を考慮して、それぞれのパラメータの上下限値を常識の範囲内で限定した。
【0049】
次に、応答曲面のX軸及びY軸を、CSP間の位置関係(ΔX、ΔY)とし、Z軸をはんだバンプの非線形歪振幅量(歪量)として、FEM手法により求めた一つ一つの点を繋いで応答曲面を作成する。実装基板の形状及び材料特性と、CSPの形状及び材料特性の種々の組合せに応じて、CSP間の位置関係(ΔX、ΔY)をX軸、Y軸とした応答曲面をそれぞれ形成する。
【0050】
図7は、有限要素法により求めた一点一点の解析結果から、1変数に対して4次の多項式で応答曲線(回帰曲線)を作成した例である。図7の横軸は、例えばCSP間の相対位置ΔXである。縦軸は、はんだバンプの非線形歪振幅量である。この多項式の作成は、例えば最小2乗法により行う。CSP間の相対位置ΔYが固定の場合には、この応答曲線からはんだバンプの非線形歪振幅量を求めることができる。CSP間の相対位置が2変数(ΔX、ΔY)に増えると、この応答曲線は多次元の応答曲面(回帰曲面)となる。
【0051】
次に、本発明の実施形態に係る電子部品の実装信頼性予測方法について説明する。図8は電子部品の実装信頼性の予測方法を示すフローチャートである。ここでは、上述した予測システム100を用いて、実装基板の両面に配置されるCSPの実装信頼性を予測することを前提とする。
【0052】
まず、始めに、図8のステップ1で、図2に示した各パラメータの数値をパラメータ格納部11に入力する。図9はモニタ27上での入力画面の一例を示す概念図である。オペレータは図9に示すような入力画面上で、図2に示した各々のパラメータについてその数値を入力する。
【0053】
数値入力した位置関係(ΔX、ΔY)に基づいて、CSPの重なり具合を入力画面上でリアルタイムに画像表示できるようにしておくと、位置関係(ΔX、ΔY)の入力ミスを防ぐことができ、便利である。
【0054】
次に、図8のステップ2で、入力画面上で数値入力したパラメータの各値が正しいかどうかを確認する。正しければステップ3へ進む。また、訂正が必要ならばステップ1へ戻り、パラメータの数値を入力し直す。図8のステップ3では、入力されたパラメータの数値に基づいて、モデル格納部13から所定の応答曲面が呼び出されモニタ27上に表示される。このモニタ画面上に表示された応答曲面から、CSP間の相対位置と、はんだバンプの非線形歪振幅量との関係を凡そ把握することができる。
【0055】
そして、図8のステップ4で、CPU23によってCSP間の位置関係(ΔX、ΔY)がこの応答曲面に当てはめられて、はんだバンプの非線形歪量が算出される。算出されたはんだバンプの非線形歪振幅量は、歪量格納部19に格納される。
【0056】
また、図8のステップ5では、実装基板ではなく、実験基板上でのはんだバンプの非線形歪振幅量と信頼性寿命値を実験データ格納部17に格納する。そして、図8のステップ6で、実装基板上でのはんだバンプの非線形歪振幅量(計算値)と、実験基板上でのはんだバンプの非線形歪振幅量(実験値)及び信頼性寿命(実験値)とが、Coffin−Manson則の疲労寿命式に数値代入される。
【0057】
これにより、実験基板上でのはんだバンプの信頼性寿命値が算出される(図5の▲1▼〜▲3▼式を参照)。これら一連の計算処理は、CPU23により行う。算出された実装基板上でのはんだバンプの信頼性寿命値は、信頼性データ格納部21に格納されると共に、モニタ27に画面表示される(ステップ7)。これにより、図8に示した電子部品の実装信頼性予測方法を終了する。
【0058】
このように、本発明の実施形態に係る電子部品の実装信頼性予測システム100によれば、応答曲面を利用して信頼性寿命解を導き出すので、FEMモデル等を書く手間がいらず、かつ数値入力後、直ぐに解が得られるため、操作者に専門知識が不要である。その為、信頼性設計はメカ分野にもかかわらず、フロアレイアウトを担当する電気設計者にも操作可能で、フロアレイアウトプランニングに活用する事ができる。
【0059】
また、この予測システム100では、実装基板の両面でCSPをどちらに動かせば、どのように信頼性が変化するか(例えば、良い方向か悪い方向か)をほぼリアルタイムに予測できるので、電送線路を考慮しつつ、より最適な配置位置を決定する事ができる。CSPのフロアレイアウトと実装信頼性の関係をほぼリアルタイムに把握できるので、実装信頼性のオーバスペックや、その逆に実装信頼性が不足してしまうといった事態を回避することができる。
【0060】
尚、この実施形態では、CSP間の位置関係(ΔX、ΔY)を応答曲面に入力してはんだバンプの歪量を求め、このはんだバンプの歪量を疲労寿命式に入力してはんだバンプの信頼性寿命値を算出するシステム及び方法について説明したが、その逆に、所望の信頼性寿命値を上述したCoffin−Manson則の疲労寿命式に入力してはんだバンプの歪量を求め、この歪量を応答曲面に入力して、所望の信頼性寿命値を満足するCSP間の位置関係(ΔX、ΔY)を算出することも可能である。
【0061】
図10は、実装信頼性予測システム100’の構成例を示すブロック図である。図10において図1と同一の機能を有するものには同一記号を付し、その説明を省略する。図10において、パラメータ格納部11には、CSP間の位置関係(ΔX、ΔY)を除いた、実装基板及びCSPの形状、材料特性のパラメータを格納する。また、実験データ格納部17には、試験基板上での実験結果(歪量、信頼性寿命値)を格納する。さらに、信頼性データ格納部21には、所望の信頼性寿命値を格納する。
【0062】
すると、CPU23’は、実験データ及び所望の信頼性寿命値を疲労寿命式(図5の▲2▼、▲3▼式を参照)に入力して、はんだバンプの非線形歪振幅量を算出する。さらに、このCPU23’は、算出したはんだバンプの非線形歪振幅量を応答曲面に入力して、所望の信頼性寿命値を満足するCSP間の位置関係(ΔX、ΔY)を出力する。
【0063】
出力されたCSP間の位置関係を、モニタ画面27上で等高線等で表示すれば、実装基板の両面に実装される各々のCSPをどの方向にどれだけ移動させると信頼性が向上するかを一目で把握でき、便利である。○○cycleまでCSPの接続信頼性が保持可能な配置エリアを把握する事ができ、フロアレイアウト設計者に容易に配置可能な場所を教示できる。例えば、図3に示した応答曲面がモニタ画面27上に表示される。
【0064】
また、電話回線、又は光ケーブル等の有線、或いは無線を介して、当該実装信頼性予測システム100及び100’に遠隔地からアクセス可能にしておくと、解析する場所を限定されずに信頼性寿命や、最適な位置関係(ΔX、ΔY)の計算処理を実行できるので、便利である。ウェブブラウザを介して当該システム100及び100’を利用することにより、ホームページ画面で入力・結果表示ができる。また、ソフトのバージョンアップやバグフィックスも一元管理できる。
【0065】
【発明の効果】
以上説明したように、本発明に係る電子部品の実装信頼性予測方法によれば、配線用の基板を有し当該基板の対向する両面にはんだ接合部を介して電子部品がそれぞれ取り付けられて成る電子機器の、当該基板に対する該電子部品の実装信頼性を予測する際に、予め、はんだ接合部に生じる歪量を電子部品間の位置関係に対応させて求めておくと共に、当該歪量を該電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面を作成しておくようになされる。
【0066】
この構成によって、従来方式と比べて、電子機器内のはんだ接合部の歪量を求めるために当該電子機器に対応したFEMモデルを信頼性評価毎にいちいち作成する必要がなく、電子機器の設計変更に合わせてFEMモデルを作成し直す必要もない。従って、電子機器内のはんだ接合部の信頼性寿命を容易、かつ迅速に予測することができる。
【0067】
また、本発明に係る電子部品の実装信頼性予測システムによれば、配線用の基板を有し当該基板の対向する両面にはんだ接合部を介して電子部品がそれぞれ取り付けられて成る電子機器の、当該基板に対する該電子部品の実装信頼性を予測するシステムであって、はんだ接合部に生じる歪量を電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面に、当該電子部品間の任意の位置関係情報を入力して、はんだ接合部に生じる歪量を算出する演算処理部を備えたものである。
【0068】
この構成によって、従来方式と比べて、電子機器内のはんだ接合部の歪量を求めるために、当該電子機器に対応したFEMモデルを信頼性評価毎にいちいち作成しなくても済む。従って、電子機器内のはんだ接合部の信頼性寿命を容易、かつ迅速に予測することができる。
【0069】
この発明は、実装基板の両面にはんだバンプを介してCSPが取り付けられて成るデジタルカメラやノートパソコン等の信頼性評価に適用して極めて好適である。
【図面の簡単な説明】
【図1】本発明の実施形態に係る実装信頼性予測システム100の構成例を示すブロック図である。
【図2】パラメータ及びその設定範囲の一例を示す表図である。
【図3】応答曲面の一例を示す表図である。
【図4】Coffin−Manson則の疲労寿命式を示す対数グラフである。
【図5】歪量の算出に用いる演算式の一例である。
【図6】田口メソッドによるパラメータ感度解析結果の一例を示す表図である。
【図7】応答曲線の一例を示す表図である。
【図8】実装信頼性の予測方法を示すフローチャートである。
【図9】入力画面の一例を示す概念図である。
【図10】実装信頼性予測システム100’の構成例を示すブロック図である。
【図11】FEMモデル70の一例を示す概念図である。
【符号の説明】
11・・・パラメータ格納部(位置情報格納部)、13・・・モデル格納部、15・・・疲労寿命式格納部、17・・・実験データ格納部、19・・・歪量格納部、21・・・信頼性データ格納部、23・・・CPU(第1、第2の演算処理部)、23’・・・CPU(第3、第4の演算処理部)、27・・・モニタ、50A,50B・・・CSP、60・・・格納部本体、100,100’・・・実装信頼性予測システム
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electronic component mounting reliability prediction method and a prediction system suitable for application to the reliability evaluation of an electronic device in which a CSP (Chip Size Package) is attached via solder bumps to both surfaces of a mounting board. Things. More specifically, this is a method for predicting the mounting reliability of an electronic component on a double-sided mounting type board. In advance, the amount of distortion generated in a solder joint portion is determined in advance in accordance with the positional relationship between the electronic components, and this distortion is determined. By making a response curve or a response surface that displays the quantity corresponding to the positional relationship between electronic components, the reliability life of solder joints in electronic equipment can be easily and quickly predicted. It is.
[0002]
[Prior art]
2. Description of the Related Art In recent years, electronic components such as semiconductor packages have been miniaturized year by year as electronic devices have become smaller and lighter. Therefore, the part of the semiconductor package that is bonded to the printed circuit board is also reduced in size, and the mounting reliability of the semiconductor package is sufficient for thermal stress caused by the difference in the coefficient of thermal expansion between the semiconductor package and the mounting board. Structural design margins are decreasing.
[0003]
To ensure sufficient reliability against thermal stress, various reliability tests are required. In particular, in the case of a semiconductor package called a CSP, which is designed so that its size is almost the same as that of a silicon chip, thermal bumps are applied to the solder bumps that also serve as electrical connections, so a test that guarantees its reliability is important. . For this reason, each semiconductor manufacturer and a set manufacturer using the same put a test board on which a CSP is mounted in a constant temperature chamber, and perform a reliability assurance test that withstands actual use by moving the temperature up and down.
[0004]
In order to guarantee the reliability of the CSP mounted on the double-sided mounting board, the CSP is mounted on the front and back surfaces of the double-sided mounting type test board in the same manner as in the case described above, and the assurance test is performed. The CSP test to guarantee reliability has two stages. The first stage is the reliability confirmation on the test board, but the second stage is the reliability confirmation test in the same state as the actual product. It is.
[0005]
In the case of double-sided mounting, it is known that the mounting reliability of the CSP changes depending on the arrangement of the front and back CSPs on the mounting board. It is difficult to predict the reliability on the mounting board from the data. Depending on the position and size of the CSP disposed on the back surface, even if the first stage test board is OK, the second stage mounting board often does not pass the reliability test.
[0006]
In this case, the effects of thermal strain are reduced by various design factors such as the material and thickness of the mounting board and the arrangement of the electronic components, and the design is changed to commercialize. However, in recent years, product design cycles have become increasingly shorter, and a design change at the confirmation stage on a mounting board leads to a change in specifications once determined. This prolongs the design period of the product, resulting in an increase in development and manufacturing costs.
[0007]
On the other hand, as a method of estimating the life of a solder joint of a semiconductor package by a numerical calculation method, a prediction method based on a fatigue life equation such as the Coffin-Manson rule is known.
[0008]
This prediction method is based on a finite element method (hereinafter, also referred to as an FEM method) in which an amplitude of plastic strain or creep strain of a solder joint generated due to a difference in thermal expansion coefficient between a substrate and a semiconductor package is determined. This is a method of predicting the reliability life of the solder joint by applying the obtained strain amplitude to the fatigue life formula of the Coffin-Manson rule.
[0009]
In this FEM method, the shape and material characteristics (Young's modulus, Poisson's ratio, linear expansion coefficient, etc.) of each component of the CSP are numerically input to a dedicated tool called a Pre-Post processor, and the FEM as shown in FIG. Create a model 70. Then, based on the FEM model 70, when the temperature moves up and down within a certain range, for example, the shape and material characteristics of each component of the CSPs 50A and 50B are changed to the joints such as the solder bumps 75A and 75B. Calculate the effect.
[0010]
The reliability life of the solder bumps 75A and 75B is determined by the shape of the bumps, the number and arrangement of the bumps, the size and thickness of the built-in silicon chip, the thickness of the entire package, the rigidity and linear expansion coefficient of the mold resin, It depends on the material and thickness of the interposer substrate (IP), the size of the package, and the thickness, rigidity, and coefficient of linear expansion of the mounting substrate.
[0011]
[Problems to be solved by the invention]
By the way, according to the method of estimating the mounting reliability of the CSP according to the conventional example, the shape and material characteristics (Young's modulus, Poisson's ratio, linear expansion coefficient, etc.) of each component of the CSPs 50A and 50B are called a Pre-Post processor. The FEM model 70 was created by inputting numerical values into the dedicated tool.
[0012]
Then, based on the FEM model 70, for example, when the temperature moves up and down within a certain range, the shape and material characteristics of each component of the CSPs 50A and 50B are changed to the joints such as the solder bumps 75A and 75B. The effect was calculated.
[0013]
For this reason, in the mounting reliability prediction method according to the conventional example, if the method of defining the model (for example, the fineness of the FEM model, the boundary condition of the calculation, etc.) differs depending on the operator or the like, the parameter variables are numerically input to the same value. However, there is a problem that a different prediction result is derived.
[0014]
That is, in the FEM method, it is necessary to use a dedicated Pre-Post processor to divide the cross section and surface of the mounting board and the solder bumps with a mesh and construct the FEM model 70 while selecting the nodes of the mesh. There is inconvenience that a correct solution cannot be derived unless a person skilled in operation or a specialized analyst with a certain knowledge operates this Pre-Post processor. Therefore, in the prediction method according to the conventional example, the prediction of the mounting reliability of the CSPs 50A and 50B must always be performed by a specialized engineer who can operate the Pre-Post processor.
[0015]
Further, the above-mentioned FEM method repeatedly calculates how much the nodes of the mesh are displaced by thermal stress (stress) or the like. In particular, the calculation of creep strain is obtained by integrating the strain amount along the elapsed time. Since it is necessary to keep going, the calculation process requires a certain amount of time.
[0016]
For this reason, after determining the layout design (floor layout) of the CSPs 50A and 50B, the parameter variables are input to the Pre-Post processor to create the FEM model 70, and it takes a considerable amount of time to predict the mounting reliability. It takes time, and the relationship between the floor layout of the CSPs 50A and 50B and the mounting reliability cannot be grasped in real time.
[0017]
Further, when changing the floor layout of the CSPs 50A and 50B, it is necessary to re-create the above-mentioned FEM model 70. Therefore, it takes more time to predict the mounting reliability of the CSP (hereinafter, also referred to as electronic components). There was a problem that it was necessary.
[0018]
Therefore, the present invention solves such a problem, and it is not necessary to create an FEM model for every reliability evaluation, and the reliability life of a solder joint in an electronic device can be easily shortened. It is an object of the present invention to provide a method for predicting the mounting reliability of an electronic component and a system for predicting the mounting reliability, which can be quickly and quickly predicted.
[0019]
[Means for Solving the Problems]
The above-described problem is to predict the mounting reliability of the electronic component with respect to the board of an electronic device having a wiring board and having the electronic component attached to both opposing surfaces of the board via solder joints. And a response curve displaying in advance the amount of strain occurring in the solder joint in accordance with the positional relationship between the electronic components and displaying the amount of strain in accordance with the positional relationship between the electronic components. Or a step of preparing a response surface, and a step of arbitrarily setting the positional relationship between the electronic components, and applying the set positional relationship to a response curve or a response surface to calculate a distortion amount generated in the solder joint. The problem is solved by a method for predicting mounting reliability of an electronic component, characterized by having:
[0020]
ADVANTAGE OF THE INVENTION According to the mounting reliability prediction method of the electronic component which concerns on this invention, the trouble which creates the FEM model corresponding to an electronic device for every reliability evaluation can be omitted, the reliability life of a solder joint part is easy, and Can be predicted quickly.
[0021]
An electronic component mounting reliability prediction system according to the present invention is directed to an electronic device having a wiring substrate and having electronic components attached to both opposing surfaces of the substrate via solder joints, with respect to the substrate. A system for predicting mounting reliability of an electronic component, comprising: a model storage unit for storing a response curve or a response surface for displaying an amount of strain generated in the solder joint in correspondence with a positional relationship between the electronic components; A position information storage unit for storing arbitrary positional relationship information between the two, and the positional relationship information stored in the position information storage unit is input to a response curve or a response surface stored in the model storage unit, and the position is stored in the solder joint. And an arithmetic processing unit for calculating the amount of distortion generated.
[0022]
According to the electronic component mounting reliability prediction system according to the present invention, a response curve or a response surface that displays the amount of strain generated at the solder joint portion in correspondence with the positional relationship between the electronic components includes an arbitrary value between the electronic components. The positional relationship information is input, and the amount of distortion generated in the solder joint is calculated.
[0023]
Therefore, compared to the conventional method, it is not necessary to create an FEM model corresponding to the electronic device for each reliability evaluation in order to obtain the amount of distortion of the solder joint in the electronic device. The time required can be greatly reduced.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method and a system for predicting the mounting reliability of an electronic component according to an embodiment of the present invention will be described with reference to the drawings.
[0025]
In this embodiment, the mounting reliability of the electronic component on the substrate is estimated for an electronic device having a wiring substrate and having electronic components attached to opposing surfaces of the substrate via solder joints, respectively. At this time, the amount of distortion generated in the solder joint is determined in advance in accordance with the positional relationship between the electronic components, and the response curve or the response surface displaying the amount of distortion in accordance with the positional relationship between the electronic components. In addition, the FEM model does not have to be created for each reliability evaluation, and the reliability life of the solder joint in the electronic device can be easily and quickly predicted. Things.
[0026]
First, an electronic component mounting reliability prediction system according to an embodiment of the present invention will be described.
[0027]
FIG. 1 is a block diagram illustrating a configuration example of an electronic component mounting reliability prediction system 100 according to an embodiment of the present invention. The mounting reliability prediction system 100 includes a mounting substrate (an example of a wiring substrate), and a semiconductor package (an electronic component such as a CSP) is provided on both opposing surfaces of the substrate via solder bumps (an example of a solder joint). Is a system for predicting the mounting reliability between a mounting board and a CSP in an electronic device to which each is attached.
[0028]
As shown in FIG. 1, the mounting reliability prediction system (hereinafter, also simply referred to as a prediction system) 100 includes a parameter storage unit (an example of a position information storage unit) 11, a model storage unit 13, and a fatigue life equation storage. The unit 15 includes an experiment data storage unit 17, a distortion amount storage unit 19, a reliability data storage unit 21, a CPU 23, a ROM 25, a monitor 27, and the like.
[0029]
The parameter storage unit 11 shown in FIG. 1 stores parameter variables such as the positional relationship between the CSPs attached to both sides of the mounting board, the shape and material characteristics of the CSP, and the shape and material characteristics of the solder bumps (hereinafter simply referred to as parameters). Is also input numerically. FIG. 2 is a table showing an example of parameters stored in the parameter storage unit 11 and their setting ranges. Each parameter shown in FIG. 2 is numerically set within the upper and lower limits, and stored in the parameter storage unit 11. The parameter storage unit 11 is configured by, for example, a RAM (Random Access Memory).
[0030]
The model storage unit 13 stores a response surface that three-dimensionally displays plastic strain, creep strain, and the like generated in the solder bumps in accordance with the positional relationship (ΔX, ΔY) between the CSPs mounted on both surfaces of the mounting board. You.
[0031]
FIG. 3 is a table showing an example of the response surface. The X axis in FIG. 3 is the relative displacement (ΔX) of the center point of the CSP 50B in the X direction with respect to the center point of the CSP 50A. The Y-axis in FIG. 3 is the relative displacement (ΔY) of the center point of the CSP 50B in the Y direction with respect to the center point of the CSP 50A. The Z-axis in FIG. 3 represents the amount of distortion (hereinafter, also referred to as nonlinear distortion amplitude) of the solder bumps when one cycle of a TC (Thermal Cycle) test is performed in a temperature range of −25 ° C. to 125 ° C. is there.
[0032]
The response surface shown in FIG. 3 is represented, for example, by the equation (1) in FIG. In equation (1), the variable X i , X j Is a general notation of each parameter. The variable Y is the amount of nonlinear distortion amplitude of the solder bump described above, and β 0 , Β i , Β ii , Β ij ... are constants according to the parameters. In equation (1), the positional relationship between the CSPs (ΔX, ΔY) is X i , X j , The amount of nonlinear distortion amplitude of the solder bump corresponding to the positional relationship is calculated. A method of creating the response surface will be described later.
[0033]
The model storage unit 13 illustrated in FIG. 1 is configured by a large-capacity storage device such as a hard disk (HDD). The distortion amount storage unit 19 shown in FIG. 1 stores the amount of nonlinear distortion amplitude calculated from the response surface. The distortion storage unit 19 is constituted by, for example, a RAM.
[0034]
In FIG. 1, the result of a TC test on an experimental board on which two or more CSPs are mounted on both sides via solder bumps, that is, the solder measured on the experimental board, The non-linear distortion amplitude of the bump and the reliability life value (the number of cycles in the TC test) are stored. The experiment data storage unit 17 is configured by, for example, a RAM.
[0035]
The fatigue life equation storage section 15 stores, for example, a fatigue life equation of the Coffin-Manson rule as shown in equation (2) of FIG. In equation (2), Y is the amount of nonlinear distortion amplitude of the solder bump, and ε 0 Is the fatigue life characteristic. This fatigue life characteristic ε 0 Is a value that depends on the shape of each solder bump. N is a thermal cycle life (reliable life value of the solder bump: cycle). When both sides of the equation (2) are displayed in logarithm, a logarithmic graph shown in FIG. 4 can be obtained.
[0036]
The horizontal axis in FIG. 4 is the logarithm of N, and the vertical axis is the logarithm of Y. The slope of the graph (line segment) shown in FIG. 4 differs depending on the material properties of the solder bump. For example, in the case of Sn-Pb eutectic solder, it is about -0.5. Also, the height of this graph (line segment) is the fatigue life characteristic ε. 0 Fluctuates depending on The fatigue life equation storage unit 15 for storing the equation of the Coffin-Manson rule is, for example, an HDD.
[0037]
By the way, the equation (3) in FIG. 5 is a fatigue life equation based on the Coffin-Manson rule like the equation (2) in FIG. In equation (3), N R Is the experimental result of the TC test on the experimental substrate, and is the reliability life cycle (cycle) of the solder bump. Also, Y R Is the experimental result of the TC test on the experimental substrate, and is the amount of nonlinear distortion amplitude of the solder bump. That is, N R And Y R Is known data, so from equation (3) 0 Can be obtained. Since the shape of the solder bumps on the experimental board is the same as that on the mounting board, the ε obtained by equation (3) was used. 0 Is ε in equation (2) 0 be equivalent to.
[0038]
Therefore, ε obtained from equation (3) 0 By substituting the non-linear distortion amplitude Y of the solder bump obtained from the equation (1) (response curved surface) into the equation (2), a reliability life value N of the solder bump on the mounting board is obtained. Can be.
[0039]
The reliability life value N is stored in the reliability data storage unit 21 shown in FIG. The reliability data storage unit 21 is, for example, a RAM. The reliability life value N of the solder bump stored in the reliability data storage unit 21 can be output to the outside of the prediction system 100.
[0040]
The prediction system 100 includes a parameter storage unit 11, a model storage unit 13, a fatigue life equation storage unit 15, an experiment data storage unit 17, a strain amount storage unit 19, and a reliability data storage unit 21. The storage unit main body 60 is configured.
[0041]
The CPU 23 shown in FIG. 1 operates so as to read data and calculation formulas from each storage unit constituting the storage unit main body 60, perform a predetermined calculation process, and write the calculation result to the storage unit main body 60. An operation program for the CPU 23 is stored in a ROM (Read Only Memory) 25. Further, on the monitor 27, each data stored in the storage unit main body 60 is arbitrarily displayed.
[0042]
Next, a method of creating the response surface stored in the model storage unit 13 will be described. The response surface shown in FIG. 3 is composed of many points. The points that make up this response surface are the shape, number and arrangement of solder bumps, the size and thickness of the silicon chip incorporated, the size and thickness of the entire package, the rigidity and linear expansion coefficient of the mold resin, It is calculated by the finite element method (FEM method) based on parameters such as the material and thickness of the interposer and the thickness, rigidity, and coefficient of linear expansion of the mounting board.
[0043]
However, if the number of parameters and the variable range of the response surface are increased unnecessarily because the response surface is required to have high accuracy and high range, the number of sampling of the amount of nonlinear distortion amplitude becomes enormous, and the response surface is created. A long time is required.
[0044]
Therefore, in this embodiment, for example, a characteristic determined by a certain width such as 0.3 to 0.4, such as a Poisson's ratio, is fixed at its average value. In addition, since there are many types of polyimide material or FR-4 material for the actual CSP interposer substrate (IP), the material is also limited to two levels (types). Furthermore, the thickness of the IP is, for example, 0.07 mm for the polyimide material and 0.2 mm and 0.4 mm for the FR-4 material as standard specifications. Is limited to two levels.
[0045]
In addition, among parameters constituting the response surface, parameters with low sensitivity relating to the reliability life of the solder bumps are fixed at an average value, and only parameters with high sensitivity are narrowed down. Thereby, the parameters constituting the response surface can be effectively reduced, and the creation of the response surface can be facilitated.
[0046]
Incidentally, the DOE method (Taguchi method) can be used to narrow down the parameters. For example, FIG. 6 shows the result of a sensitivity analysis called L12 with two levels and seven parameters. The horizontal axis in FIG. 6 is the level (two levels are represented by -1, 1), and the vertical axis is the amount of nonlinear distortion amplitude (distortion amount) of the solder bump.
[0047]
As is clear from FIG. 6, the relative position ΔX and the relative position ΔY between the CSPs have high sensitivity regarding the reliability life of the solder bumps, and the Mold resin thickness is low. Therefore, it can be seen that even if the Mold resin thickness is fixed to the average value of general CSP, there is not much difference in the calculation result. Thereby, it is also possible to exclude the Mold resin thickness from the parameters and to fix it at an average value.
[0048]
In this embodiment, parameters constituting the response surface are narrowed down by the above-described method, and as shown in FIG. 2, the parameters constituting the response surface are converted into the shape and material properties of the mounting board, the shape and the material properties of the CSP, The relative position (positional relationship) between the CSPs was taken. In addition, the upper and lower limits of each parameter are limited within the range of common sense in consideration of material properties, shapes, layouts, and the like that can be actually used.
[0049]
Next, the X- and Y-axes of the response surface are defined as the positional relationship between the CSPs (ΔX, ΔY), and the Z-axis is defined as the non-linear distortion amplitude (distortion) of the solder bumps. Create a response surface by connecting points. According to various combinations of the shape and material characteristics of the mounting substrate and the shape and material characteristics of the CSP, response curved surfaces with the positional relationship (ΔX, ΔY) between the CSPs as the X axis and the Y axis are formed.
[0050]
FIG. 7 is an example in which a response curve (regression curve) is created by a fourth-order polynomial for one variable from an analysis result of each point obtained by the finite element method. The horizontal axis in FIG. 7 is, for example, the relative position ΔX between the CSPs. The vertical axis indicates the amount of nonlinear distortion amplitude of the solder bump. The creation of this polynomial is performed by, for example, the least squares method. When the relative position ΔY between the CSPs is fixed, the nonlinear distortion amplitude of the solder bump can be obtained from this response curve. When the relative position between the CSPs increases to two variables (ΔX, ΔY), this response curve becomes a multidimensional response surface (regression surface).
[0051]
Next, a method for predicting the mounting reliability of an electronic component according to the embodiment of the present invention will be described. FIG. 8 is a flowchart showing a method for predicting the mounting reliability of an electronic component. Here, it is assumed that the mounting reliability of the CSP arranged on both sides of the mounting board is predicted using the above-described prediction system 100.
[0052]
First, at step 1 in FIG. 8, the numerical values of the parameters shown in FIG. FIG. 9 is a conceptual diagram showing an example of an input screen on the monitor 27. The operator inputs numerical values of each parameter shown in FIG. 2 on an input screen as shown in FIG.
[0053]
Based on the positional relationship (ΔX, ΔY) input by numerical values, if the overlapping degree of the CSPs can be displayed in real time on the input screen, it is possible to prevent the input error of the positional relationship (ΔX, ΔY), It is convenient.
[0054]
Next, in step 2 of FIG. 8, it is confirmed whether each value of the parameter numerically input on the input screen is correct. If correct, go to step 3. If correction is necessary, the process returns to step 1 and the numerical values of the parameters are re-input. In step 3 of FIG. 8, a predetermined response surface is called from the model storage unit 13 based on the input parameter values and displayed on the monitor 27. From the response surface displayed on the monitor screen, the relationship between the relative position between the CSPs and the amount of nonlinear distortion amplitude of the solder bump can be roughly grasped.
[0055]
Then, in step 4 in FIG. 8, the CPU 23 applies the positional relationship (.DELTA.X, .DELTA.Y) between the CSPs to the response surface to calculate the amount of nonlinear distortion of the solder bump. The calculated nonlinear distortion amplitude of the solder bump is stored in the distortion storage unit 19.
[0056]
In step 5 of FIG. 8, the amount of nonlinear distortion amplitude and the reliability life value of the solder bumps on the test board, not on the mounting board, are stored in the test data storage unit 17. Then, in step 6 of FIG. 8, the amount of nonlinear distortion amplitude (calculated value) of the solder bump on the mounting board, the amount of nonlinear distortion amplitude of the solder bump on the experimental board (experimental value), and the reliability life (experimental value) ) Is substituted into the fatigue life formula of the Coffin-Manson rule.
[0057]
Thereby, the reliability life value of the solder bump on the experimental board is calculated (see the equations (1) to (3) in FIG. 5). These series of calculation processes are performed by the CPU 23. The calculated reliability life value of the solder bump on the mounting board is stored in the reliability data storage unit 21 and displayed on the monitor 27 (step 7). Thus, the method for estimating the mounting reliability of the electronic component shown in FIG. 8 is completed.
[0058]
As described above, according to the electronic component mounting reliability prediction system 100 according to the embodiment of the present invention, since the reliability life solution is derived using the response surface, there is no need to write an FEM model or the like, and the numerical value is reduced. Since the solution can be obtained immediately after the input, the operator does not need specialized knowledge. Therefore, the reliability design can be operated by an electric designer in charge of the floor layout in spite of the mechanical field, and can be used for floor layout planning.
[0059]
Further, in this prediction system 100, it is possible to predict in real time how the CSP is moved on both sides of the mounting board and how the reliability changes (for example, whether the direction is good or bad). It is possible to determine a more optimal arrangement position while taking into account. Since the relationship between the floor layout of the CSP and the mounting reliability can be grasped almost in real time, it is possible to avoid an over-specification of the mounting reliability and conversely a situation in which the mounting reliability is insufficient.
[0060]
In this embodiment, the positional relationship between the CSPs (ΔX, ΔY) is input to the response surface to determine the amount of distortion of the solder bump, and the amount of distortion of the solder bump is input to the fatigue life equation to obtain the reliability of the solder bump. The system and method for calculating the characteristic life value have been described. Conversely, the desired reliability life value is input to the above-mentioned fatigue life formula of the Coffin-Manson rule to determine the strain amount of the solder bump. May be input to the response surface to calculate the positional relationship (ΔX, ΔY) between the CSPs that satisfies the desired reliability life value.
[0061]
FIG. 10 is a block diagram illustrating a configuration example of the mounting reliability prediction system 100 ′. 10, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 10, the parameter storage unit 11 stores parameters of the shape and material characteristics of the mounting board and the CSP excluding the positional relationship (ΔX, ΔY) between the CSPs. Further, the experiment data storage unit 17 stores the experiment results (strain amount, reliability life value) on the test board. Further, the reliability data storage unit 21 stores a desired reliability life value.
[0062]
Then, the CPU 23 'inputs the experimental data and the desired reliability life value into the fatigue life equation (see equations (2) and (3) in FIG. 5) and calculates the amount of nonlinear distortion amplitude of the solder bump. Further, the CPU 23 'inputs the calculated nonlinear distortion amplitude of the solder bump into the response surface, and outputs the positional relationship (ΔX, ΔY) between the CSPs that satisfies the desired reliability life value.
[0063]
By displaying the positional relationship between the output CSPs by contour lines or the like on the monitor screen 27, it is possible to determine at a glance which direction and how much each CSP mounted on both sides of the mounting board should be moved to improve the reliability. It is easy to grasp and convenient. It is possible to grasp the arrangement area where the connection reliability of the CSP can be maintained up to the XX cycle, and it is possible to easily teach the floor layout designer where the arrangement is possible. For example, the response surface shown in FIG. 3 is displayed on the monitor screen 27.
[0064]
In addition, if the mounting reliability prediction systems 100 and 100 ′ can be accessed from a remote place via a telephone line, a wired cable such as an optical cable, or a wireless communication, the analysis life is not limited and the reliability life can be improved. This is convenient because calculation processing of the optimal positional relationship (ΔX, ΔY) can be executed. By using the systems 100 and 100 'through a web browser, input and results can be displayed on a homepage screen. In addition, software upgrades and bug fixes can be centrally managed.
[0065]
【The invention's effect】
As described above, according to the method for predicting the mounting reliability of an electronic component according to the present invention, the electronic component is mounted on each of both opposing surfaces of the substrate via a solder joint on each of the opposing surfaces of the substrate. When estimating the mounting reliability of the electronic component on the board of the electronic device, the amount of distortion generated in the solder joint is determined in advance in accordance with the positional relationship between the electronic components, and the amount of distortion is determined. A response curve or a response surface to be displayed corresponding to the positional relationship between the electronic components is created.
[0066]
With this configuration, unlike the conventional method, it is not necessary to create an FEM model corresponding to the electronic device for each reliability evaluation in order to obtain the amount of distortion of the solder joint in the electronic device. It is not necessary to re-create the FEM model according to. Therefore, it is possible to easily and quickly predict the reliability life of the solder joint in the electronic device.
[0067]
Further, according to the electronic component mounting reliability prediction system according to the present invention, an electronic device having a wiring substrate and having the electronic component attached to both opposing surfaces of the substrate via solder joints, A system for predicting the mounting reliability of the electronic component with respect to the substrate, a response curve or a response surface that displays the amount of strain generated at the solder joint in accordance with the positional relationship between the electronic components, It is provided with an arithmetic processing unit for inputting arbitrary positional relationship information and calculating the amount of distortion generated in the solder joint.
[0068]
With this configuration, unlike the conventional method, it is not necessary to create an FEM model corresponding to the electronic device for each reliability evaluation in order to obtain the distortion amount of the solder joint in the electronic device. Therefore, it is possible to easily and quickly predict the reliability life of the solder joint in the electronic device.
[0069]
INDUSTRIAL APPLICABILITY The present invention is very suitable when applied to the reliability evaluation of digital cameras, notebook computers, and the like in which a CSP is attached to both sides of a mounting board via solder bumps.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a mounting reliability prediction system 100 according to an embodiment of the present invention.
FIG. 2 is a table showing an example of parameters and their setting ranges.
FIG. 3 is a table showing an example of a response surface.
FIG. 4 is a logarithmic graph showing a fatigue life formula based on the Coffin-Manson rule.
FIG. 5 is an example of an arithmetic expression used for calculating a distortion amount.
FIG. 6 is a table showing an example of a parameter sensitivity analysis result by the Taguchi method.
FIG. 7 is a table showing an example of a response curve.
FIG. 8 is a flowchart showing a method for predicting mounting reliability.
FIG. 9 is a conceptual diagram illustrating an example of an input screen.
FIG. 10 is a block diagram illustrating a configuration example of a mounting reliability prediction system 100 ′.
FIG. 11 is a conceptual diagram illustrating an example of an FEM model 70.
[Explanation of symbols]
11 ... parameter storage unit (position information storage unit), 13 ... model storage unit, 15 ... fatigue life type storage unit, 17 ... experiment data storage unit, 19 ... distortion amount storage unit, 21: reliability data storage unit, 23: CPU (first and second arithmetic processing units), 23 ': CPU (third and fourth arithmetic processing units), 27: monitor , 50A, 50B ... CSP, 60 ... Storage unit body, 100, 100 '... Mounting reliability prediction system

Claims (12)

配線用の基板を有し当該基板の対向する両面にはんだ接合部を介して電子部品がそれぞれ取り付けられて成る電子機器の、当該基板に対する該電子部品の実装信頼性を予測する方法であって、
予め、前記はんだ接合部に生じる歪量を前記電子部品間の位置関係に対応させて求めておくと共に、当該歪量を該電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面を作成しておく工程と、
前記電子部品間の位置関係を任意に設定し、設定された前記位置関係を前記応答曲線又は応答曲面に当てはめて前記はんだ接合部に生じる歪量を算出する工程とを有することを特徴とする電子部品の実装信頼性予測方法。
A method of predicting the mounting reliability of an electronic component on an electronic device having a wiring substrate and having electronic components attached to opposite surfaces of the substrate via solder joints, respectively,
In advance, the amount of distortion generated in the solder joint is determined in accordance with the positional relationship between the electronic components, and a response curve or a response surface displaying the amount of distortion in association with the positional relationship between the electronic components is calculated. The process of creating,
Arbitrarily setting a positional relationship between the electronic components, and applying the set positional relationship to the response curve or response surface to calculate a strain amount generated in the solder joint. Component mounting reliability prediction method.
前記応答曲線又は応答曲面から求めたはんだ接合部の歪量をCoffin−Manson則等の疲労寿命式に当てはめて、当該はんだ接合部の信頼性寿命値を算出する工程を有することを特徴とする請求項1に記載の電子部品の実装信頼性予測方法。Applying a strain amount of the solder joint obtained from the response curve or the response surface to a fatigue life equation such as the Coffin-Manson rule to calculate a reliability life value of the solder joint. Item 1. A method for predicting mounting reliability of an electronic component according to Item 1. 前記応答曲線又は応答曲面から求めたはんだ接合部の歪量をCoffin−Manson則等の疲労寿命式に当てはめて、当該はんだ接合部の信頼性寿命値を算出する工程は、
実験用の基板を用意して当該基板の対向する両面にはんだ接合部を介して前記電子部品をそれぞれ取りつけ、
前記電子部品が取り付けられた実験用の基板上でのはんだ接合部の歪量と信頼性寿命値とをそれぞれ求め、その後、
前記実験用の基板上で求められたはんだ接合部の歪量及び信頼性寿命値と、前記応答曲線又は応答曲面から算出された配線用の基板上でのはんだ接合部の歪量とを、前記Coffin−Manson則等の疲労寿命式に当てはめて、当該配線用の基板上でのはんだ接合部の信頼性寿命値を算出することを特徴とする請求項2に記載の電子部品の実装信頼性予測方法。
Applying the strain amount of the solder joint determined from the response curve or the response surface to a fatigue life formula such as the Coffin-Manson rule, and calculating the reliability life value of the solder joint,
Prepare a substrate for the experiment, attach each of the electronic components via solder joints to both opposing surfaces of the substrate,
Determine the strain amount and the reliability life value of the solder joint on the experimental substrate to which the electronic component is attached, and then,
The amount of solder joint distortion and reliability life value determined on the experimental substrate, and the amount of solder joint distortion on the wiring substrate calculated from the response curve or response surface, 3. The reliability prediction of electronic component mounting according to claim 2, wherein the reliability life value of the solder joint on the wiring board is calculated by applying a fatigue life formula such as the Coffin-Manson rule. Method.
前記はんだ接合部に生じる歪量を前記電子部品間の位置関係に対応させて求める工程では、
当該歪量を有限要素法を用いて算出することを特徴とする請求項1に記載の電子部品の実装信頼性予測方法。
In the step of determining the amount of strain generated in the solder joint in accordance with the positional relationship between the electronic components,
The method according to claim 1, wherein the amount of distortion is calculated using a finite element method.
前記応答曲線又は応答曲面を構成するパラメータ変数は、前記電子部品間の位置関係と、当該電子部品の形状及び材料特性と、前記はんだ接合部の形状及び材料特性であることを特徴とする請求項1に記載の電子部品の実装信頼性予測方法。The parameter variable constituting the response curve or the response surface is a positional relationship between the electronic components, a shape and a material property of the electronic component, and a shape and a material property of the solder joint. 2. The method for predicting mounting reliability of an electronic component according to item 1. 配線用の基板を有し当該基板の対向する両面にはんだ接合部を介して電子部品がそれぞれ取り付けられて成る電子機器の、当該基板に対する該電子部品の実装信頼性を予測するシステムであって、
前記はんだ接合部に生じる歪量を前記電子部品間の位置関係に対応させて表示する応答曲線又は応答曲面を格納するモデル格納部と、
前記電子部品間の任意の位置関係情報を格納する位置情報格納部と、
前記位置情報格納部に格納された位置関係情報を前記モデル格納部に格納された応答曲線又は応答曲面に入力して、はんだ接合部に生じる歪量を算出する演算処理部とを備えたことを特徴とする電子部品の実装信頼性予測システム。
A system for predicting the mounting reliability of an electronic component with respect to the substrate, wherein the electronic device includes a wiring substrate and has electronic components attached to opposite sides of the substrate via solder joints, respectively,
A model storage unit that stores a response curve or a response surface that displays the amount of strain generated in the solder joint in association with the positional relationship between the electronic components,
A position information storage unit for storing arbitrary positional relationship information between the electronic components,
An arithmetic processing unit that inputs the positional relationship information stored in the position information storage unit to a response curve or a response surface stored in the model storage unit, and calculates an amount of strain generated in the solder joint. Characteristic electronic component mounting reliability prediction system.
前記演算処理部を第1の演算処理部としたとき、
Coffin−Manson則等の疲労寿命式を格納する疲労寿命式格納部と、
前記第1の演算処理部によって算出されたはんだ接合部の歪量を、前記Coffin−Manson則等の疲労寿命式に入力して、該はんだ接合部の信頼性寿命値を算出する第2の演算処理部とを備えたことを特徴とする請求項6に記載の電子部品の実装信頼性予測システム。
When the arithmetic processing unit is a first arithmetic processing unit,
A fatigue life equation storage unit for storing a fatigue life equation such as Coffin-Manson rule;
A second calculation for calculating the reliability life value of the solder joint by inputting the strain amount of the solder joint calculated by the first arithmetic processing unit into a fatigue life formula such as the Coffin-Manson rule. 7. The system according to claim 6, further comprising a processing unit.
前記疲労寿命式格納部に格納されたCoffin−Manson則等の疲労寿命式に、前記はんだ接合部の所望の信頼性寿命値を入力してはんだ接合部の歪量を算出する第3の演算処理部を備えたことを特徴とする請求項6に記載の実装信頼性予測システム。A third arithmetic processing for calculating a distortion amount of a solder joint by inputting a desired reliability life value of the solder joint into a fatigue life equation such as the Coffin-Manson rule stored in the fatigue life equation storage unit The mounting reliability prediction system according to claim 6, further comprising a unit. 前記第3の演算処理部によって算出されたはんだ接合部の歪量を前記応答曲線又は応答曲面に入力して、前記信頼性寿命値を満足する電子部品間の位置関係情報を出力する第4の演算処理部を備えたことを特徴とする請求項8に記載の実装信頼性予測システム。A fourth step of inputting the distortion amount of the solder joint calculated by the third processing unit to the response curve or the response surface, and outputting positional relationship information between electronic components satisfying the reliability life value; The mounting reliability prediction system according to claim 8, further comprising an arithmetic processing unit. 前記電子部品間の位置関係情報及び、当該位置関係情報に対応する前記はんだ接合部の信頼性寿命値とを画面表示するモニタ部を備えたことを特徴とする請求項7に記載の実装信頼性予測システム。8. The mounting reliability according to claim 7, further comprising a monitor unit for displaying on a screen positional relationship information between the electronic components and a reliability life value of the solder joint corresponding to the positional relationship information. Forecasting system. 前記応答曲面を等高線で画面表示するモニタ部を備えたことを特徴とする請求項6に記載の実装信頼性予測システム。7. The mounting reliability prediction system according to claim 6, further comprising a monitor unit for displaying the response curved surface on a screen with contour lines. 電話回線、又は光ケーブル等の有線、或いは無線を介して、前記位置情報格納部及び前記演算処理部にアクセス可能になされたことを特徴とする請求項6に記載の実装信頼性予測システム。The mounting reliability prediction system according to claim 6, wherein the location information storage unit and the arithmetic processing unit are accessible via a telephone line, a cable such as an optical cable, or wireless.
JP2002241111A 2002-08-21 2002-08-21 Method and system for predicting mounting reliability of electronic components Expired - Fee Related JP3900042B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002241111A JP3900042B2 (en) 2002-08-21 2002-08-21 Method and system for predicting mounting reliability of electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002241111A JP3900042B2 (en) 2002-08-21 2002-08-21 Method and system for predicting mounting reliability of electronic components

Publications (2)

Publication Number Publication Date
JP2004079914A true JP2004079914A (en) 2004-03-11
JP3900042B2 JP3900042B2 (en) 2007-04-04

Family

ID=32023706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002241111A Expired - Fee Related JP3900042B2 (en) 2002-08-21 2002-08-21 Method and system for predicting mounting reliability of electronic components

Country Status (1)

Country Link
JP (1) JP3900042B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010079745A1 (en) * 2009-01-07 2010-07-15 新神戸電機株式会社 System for control of wind power electricity generation accumulator and method of control thereof
JP2012063279A (en) * 2010-09-16 2012-03-29 Toshiba Corp Solder joint part life prediction method, solder joint part life prediction device, and electronic apparatus
US8190378B2 (en) 2008-01-23 2012-05-29 Fujitsu Limited Crack growth evaluation apparatus, crack growth evaluation method, and recording medium recording crack growth evaluation program
CN107688708A (en) * 2017-08-31 2018-02-13 中国电子科技集团公司第二十九研究所 A kind of reliability prediction analysis system and method based on multi-platform data fusion
CN110069838A (en) * 2019-04-04 2019-07-30 成都摩尔环宇测试技术有限公司 A kind of horizontal method for predicting of electronic product reliability

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102116755B1 (en) * 2018-09-18 2020-05-29 조선대학교산학협력단 Structural Design of electronic package by evaluation of structural safety of solder joint based on PCB substrate strain

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8190378B2 (en) 2008-01-23 2012-05-29 Fujitsu Limited Crack growth evaluation apparatus, crack growth evaluation method, and recording medium recording crack growth evaluation program
WO2010079745A1 (en) * 2009-01-07 2010-07-15 新神戸電機株式会社 System for control of wind power electricity generation accumulator and method of control thereof
JP2010159661A (en) * 2009-01-07 2010-07-22 Shin Kobe Electric Mach Co Ltd Storage battery control system for wind power generation and method for controlling the same
JP2013231441A (en) * 2009-01-07 2013-11-14 Shin Kobe Electric Mach Co Ltd Life estimation system
US9124135B2 (en) 2009-01-07 2015-09-01 Shin-Kobe Electric Machinery Co., Ltd. System for control of wind power generation storage battery and method of control thereof
JP2012063279A (en) * 2010-09-16 2012-03-29 Toshiba Corp Solder joint part life prediction method, solder joint part life prediction device, and electronic apparatus
US8965712B2 (en) 2010-09-16 2015-02-24 Kabushiki Kaisha Toshiba Life predicting method for solder joint, life predicting apparatus for solder joint and electronic device
CN107688708A (en) * 2017-08-31 2018-02-13 中国电子科技集团公司第二十九研究所 A kind of reliability prediction analysis system and method based on multi-platform data fusion
CN110069838A (en) * 2019-04-04 2019-07-30 成都摩尔环宇测试技术有限公司 A kind of horizontal method for predicting of electronic product reliability

Also Published As

Publication number Publication date
JP3900042B2 (en) 2007-04-04

Similar Documents

Publication Publication Date Title
JP4500308B2 (en) Electronic package reliability prediction apparatus and electronic package reliability prediction program
KR20080113050A (en) Pcb design reliablility simulation method and system
JPH11220078A (en) Thermal resistance calculation method of semiconductor package, storage medium, and thermal resistance-calculating device
JP3900042B2 (en) Method and system for predicting mounting reliability of electronic components
Ham et al. Thermal deformations of CSP assembly during temperature cycling and power cycling
JPWO2007086120A1 (en) Information processing apparatus, simulation method, information processing program
Ren et al. Shell-based simplified electronic package model development and its application for reliability analysis
JP2006313127A (en) System for evaluating soldered joint section
WO2010021287A1 (en) Substrate warpage predicting method, substrate warpage predicting system, and substrate warpage predicting program
Ren et al. Application of ABAQUS/Explicit submodeling technique in drop simulation of system assembly
US8079012B2 (en) Method for acquiring basic characteristic of simultaneous switching noise in method for estimating simultaneous switching noise on semiconductor device
JP2006313800A (en) Method for predicting reliability on connection of mounting structure in semiconductor device and its semiconductor device
Wu Vibration-induced fatigue life estimation of ball grid array packaging
Rodgers Prediction of microelectronics thermal behavior in electronic equipment: status, challenges and future requirements
JP2006278803A (en) Method, system, and program for analyzing warpage of board
KR20150019936A (en) Method for fatigue life prediction of SMT solder joints
US20040186702A1 (en) Mounting process simulation program and method for the same and system implementing the same
Shetty Board level reliability assessment of thick FR-4 QFN assemblies under thermal cycling
Gomez et al. Damage mechanics modeling of concurrent thermal and vibration loading on electronics packaging
Thukral et al. Board level vibration test method of components for automotive electronics: State-of-the-art approaches and challenges
Bart et al. Coupled package-device modeling for microelectromechanical systems
Schingale et al. New methods help better evaluate risks via simulation
JP3356660B2 (en) Method and system for analyzing structural warpage using finite element method, recording medium storing program for analyzing structural warpage using finite element method
Otto et al. Prognostics and Health Management Features for Large Circuit Boards to Be Implemented Into Electric Drivetrain Applications
Braden et al. Investigation into the impact of component floor plan layout on the overall reliability of electronics systems in harsh environments

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050606

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060427

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060908

A131 Notification of reasons for refusal

Effective date: 20060919

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061113

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061205

A61 First payment of annual fees (during grant procedure)

Effective date: 20061218

Free format text: JAPANESE INTERMEDIATE CODE: A61

A521 Written amendment

Effective date: 20061113

Free format text: JAPANESE INTERMEDIATE CODE: A523

LAPS Cancellation because of no payment of annual fees