JP2004073735A - Signal processing circuit and ultrasonic diagnostic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of extracting a maximum value or a minimum value by a small-scale circuit and to downsize the circuit and to make it less costly by using the signal processing circuit. <P>SOLUTION: The maximum value is extracted by a comparison section at an nth stage from a window including data totaling to 2<SP>n</SP>. A comparison section of the kth stage has a shift register 72-k as a delay means holding data totaling to 2<SP>k-1</SP>or a comparator 70-k outputting a larger one of two input data to a comparison section of the subsequent stage. A comparator 70-1 of a comparison section at the first stage receives an entry of jth original data sequentially inputted and (j-1)th original data delayed by the shift register 72-1. A comparison section (k≥2) at the kth stage receives an entry of output data of a comparison section at a previous stage, and the jth data and the (j-2<SP>k-1</SP>)th data from the shift register 72-k are inputted to the comparator 70-k. A comparator 70-6 of a last stage sequentially outputs the maximum value of data in a window when an original data string is scanned in the window with 2<SP>6</SP>in width. <P>COPYRIGHT: (C)2004,JPO

Description

この表において、“ｉ”と記す左から１番目の列は、装置を駆動するクロックのカウントに相当し、時刻を表す。また“Ｄ_０（ｉ）”と記す左から２番目の列はｉ番目のクロックでの１段目の比較部への入力データであり、さらに各々、“Ｄ_１（ｉ）”、“Ｄ_２（ｉ）”、“Ｄ_３（ｉ）”と記す左から３番目、４番目、５番目の列はそれぞれ第１段比較部、第２段比較部、第３段比較部からのｉ番目のクロックでの出力を表している。ウィンドウに含まれるデータは１個ずつ第１段比較部に入力される。ウィンドウがＤ_０（１）〜Ｄ_０（８）（すなわち、表１に示すデータ“３０”，“３１”，“０”，“３３”，“３４”，“０”，“０”，“３７”）を含む場合、第１段比較部は、Ｄ_０（１）及びＤ_０（２）、Ｄ_０（２）及びＤ_０（３）、…、Ｄ_０（７）及びＤ_０（８）に対し、それぞれ大小比較を行い、いずれか大きい方の値（比較される２つのデータの値が等しい場合にはその値）を選択して、Ｄ_１（２）、Ｄ_１（３）、…、Ｄ_１（７）として“３１”，“３１”，“３３”，“３４”，“３４”，“０”，“３７”を出力する。第２段比較部は、Ｄ_１（２）及びＤ_１（４）、Ｄ_１（３）及びＤ_１（５）、…、Ｄ_１（６）及びＤ_１（８）に対し、それぞれ大小比較を行い、いずれか大きい方の値を選択して、Ｄ_２（４）、Ｄ_２（５）、…、Ｄ_２（８）として“３３”，“３４”，“３４”，“３４”，“３７”を出力する。ここで、例えばＤ_２（４）はＤ_１（２）及びＤ_１（４）のいずれか大きい方であり、さらにＤ_１（２）はＤ_０（１）及びＤ_０（２）のいずれか大きい方、またＤ_１（４）はＤ_０（３）及びＤ_０（４）のいずれか大きい方であるので、結局、Ｄ_２（４）は４個のデータＤ_０（１）〜Ｄ_０（４）のうちの最大値となる。同様に、Ｄ_２（８）は４個のデータＤ_０（５）〜Ｄ_０（８）のうちの最大値となる。また、第３段比較部は、Ｄ_２（４）及びＤ_２（８）の大小比較を行い、いずれか大きい方の値を選択して、Ｄ_３（８）として“３７”を出力する。上述のように、Ｄ_２（４）はＤ_０（１）〜Ｄ_０（４）のうちの最大値であり、Ｄ_２（８）はＤ_０（５）〜Ｄ_０（８）のうちの最大値であるので、結局、第３段比較部から出力されるＤ_３（８）はＤ_０（１）〜Ｄ_０（８）のうちの最大値となる。以上、例示したように２^３個のデータを含むウィンドウ内の最大値が、３段に接続された３個の比較部で抽出される。このことから理解されるように、ウィンドウ幅２^ｎのデータ列に対しては、ｎ段の比較部で最大値を抽出することができる。
【００１８】
またウィンドウ幅が２^ｎでなく、２^ｎ＋α（ここでα＜２^ｎ）である場合には、２^ｎ個中の最大値Ｖ_１を前記ｎ段の比較部で求め、残るα個中の最大値Ｖ_２を前記ｎ段の比較部とは別途に設けた付加的な比較部で求め、最後にＶ_１とＶ_２とのいずれか大きい方を選択するように構成される。この付加的な比較部は、周知の最大値抽出回路を用いて構成することもできるし、αを２^ｍ１＋２^ｍ２＋…（ｍ１，ｍ２＜ｎ）の形式に分解し、前記ｎ段の比較部と同様の構成であって、より段数が低い（すなわちｍ１段、ｍ２段、…の）比較部を用いて構成することもできる。
【００１９】
以上、最大値を抽出する信号処理回路を例にその構成を説明したが、最小値を抽出する本発明の他の好適な態様の信号処理回路も同様である。その場合には、前記選択条件が、比較される２つのデータのうち小さい方を選択することであり、これにより前記ｎ段の比較部は、前記第１段比較部に順次入力された２^ｎ個のデータ中の最小値を抽出する。
【００２０】
他の本発明に係る信号処理回路は、前記第ｋ段比較部が、前記第（ｋ−１）段比較部から出力された選択データを２^ｋ−１個分保持して遅延出力するデータ保持手段と、前記第（ｋ−１）段比較部から現在出力された選択データと、前記データ保持手段から遅延出力された２^ｋ−１個前の選択データとの大小を比較する比較器とを有する。
【００２１】
１組の２^ｎ個のデータ中の最大値又は最小値を抽出するだけならば、各段の比較部の出力データは全部は必要ではない。例えば、最大値の抽出に関する上記説明に基づいて述べれば、２^ｎ個のデータＤ_０（ｉ）（ｉ＝１〜２^ｎ）からなるウィンドウＷ（１）中の最大値を求める際に、第ｎ段比較部は第（ｎ−１）段比較部の一連の出力データのうちＤ_ｎ−１（２^ｎ）及びそれより２^ｎ−１クロック前に得られたＤ_ｎ−１（２^ｎ−１）を比較するだけで足りる。最大値の検出に必要なデータを順次、前段へ遡ると、第ｋ段比較部は第（ｋ−１）段比較部の一連の出力データのうち２^ｋ−１−１個おきのデータＤ_ｋ−１（２^ｎ−λ・２^ｋ−１）（λ＝０，１，…，２^ｎ−ｋ）のみを用いている。ここで、ウィンドウを順次ずらし、各ウィンドウ位置で、そのウィンドウに含まれる最大値又は最小値を抽出する場合には、各段の比較部にて必要とされるデータも順次シフトする。例えば、ウィンドウＷ（１）からデータ１個分シフトしたウィンドウＷ（２）、すなわちデータＤ_０（ｉ）（ｉ＝２〜２^ｎ＋１）からなるウィンドウに対する最大値を求める際には、各段の比較部で必要とされるデータもウィンドウＷ（１）に対する処理で必要とされたものから１個ずつずれる。第ｋ段比較部はウィンドウＷ（１）に対してはＤ_ｋ−１（２^ｎ−λ・２^ｋ−１）を用いたが、ウィンドウＷ（２）に対してはＤ_ｋ−１（２^ｎ−λ・２^ｋ−１＋１）を用いる。ここで述べる他の本発明に係る信号処理回路では、各段の比較部が前段比較部から出力されたデータを所定個数の過去分まで保持して遅延出力することで、順次シフトして設定されるウィンドウにおける最大値又は最小値を順次、抽出することができる。具体的には第ｋ段比較部は第（ｋ−１）段比較部から出力されたデータを２^ｋ−１個前のものまで、データ保持手段に保持する。例えば、第（ｋ−１）段比較部から現在出力されたデータをＤ_ｋ−１（ｊ）とすると、その時点でデータ保持手段にはＤ_ｋ−１（ξ）（ξ＝ｊ−２^ｋ−１〜ｊ−１）が保持される。そして第ｋ段比較部は新たに出力されたＤ_ｋ−１（ｊ）と、データ保持手段に保持されたもののうち最も古いＤ_ｋ−１（ｊ−２^ｋ−１）とを比較してＤ_ｋ（ｊ）を出力する一方、Ｄ_ｋ−１（ｊ）をデータ保持手段に格納する。ウィンドウを順次シフトする場合、この段階で最も古いＤ_ｋ−１（ｊ−２^ｋ−１）は不要となるのでデータ保持手段から削除することができる。データ保持手段は例えば、メモリで構成することができる。またウィンドウを順次シフトする場合、データ保持手段に保持されたデータは古いものから順番に使用されるので、データ保持手段は遅延回路で構成することができ、その遅延回路としては例えばシフトレジスタを用いることができる。
【００２２】
さらに他の本発明に係る信号処理回路は、二次元のデータアレイに対して二次元のウィンドウを設定し、その二次元のウィンドウ内の複数のデータの中から、所定の選択条件に従って最大値又は最小値を抽出するものであって、前記ウィンドウ内における各データ列ごとに、データ列を構成する複数のデータを順次入力して、それらの中から最大値又は最小値を抽出し、その抽出されたデータを出力する第１抽出部と、前記第１抽出部によって各データ列ごとに抽出された複数のデータを順次入力して、それらの中から最大値又は最小値を抽出し、その抽出されたデータを出力する第２抽出部とを有し、前記第１抽出部は、段階的に接続されたｎ段（ｎは２以上の整数である）の第１比較部を有し、第１段の第１比較部は、現在の入力データとそれよりも１つ前の入力データとの大小を比較して、いずれか一方を選択データとして出力し、第ｋ段の第１比較部（ｋは２≦ｋ≦ｎなる整数である）は、第（ｋ−１）段の第１比較部から出力された選択データとそれよりも２^ｋ−１個前の選択データとを比較して、いずれか一方を選択データとして出力し、前記ｎ段の第１比較部は、それら全体として、前記第１段の第１比較部に順次入力された複数のデータ中の最大値又は最小値を抽出して、その抽出されたデータを出力し、前記第２抽出部は、段階的に接続されたｍ段（ｍは２以上の整数である）の第２比較部を有し、第１段の第２比較部は、現在の入力データとそれよりも１つ前の入力データとの大小を比較して、いずれか一方を選択データとして出力し、第ｋ段の第２比較部（ｋは２≦ｋ≦ｍなる整数である）は、第（ｋ−１）段の第２比較部から出力された選択データとそれよりも２^ｋ−１個前の選択データとを比較して、いずれか一方を選択データとして出力し、前記ｍ段の比較部は、それら全体として、前記第１段の第２比較部に順次入力された複数のデータ中の最大値又は最小値を抽出する。
【００２３】
本発明に係る超音波診断装置は、超音波の送受波によって得られた受信データ列に対してウィンドウを設定し、前記ウィンドウ内の複数の受信データの中から、最大値又は最小値を抽出して、その抽出された受信データを出力する抽出部と、前記抽出部から順次出力される受信データを用いて超音波画像を生成する画像生成部とを有し、前記抽出部は、所定の選択条件に従って動作する段階的に接続されたｎ段（ｎは２以上の整数である）の比較部を有し、第１段比較部は、現在の入力受信データとそれよりも１つ前の入力受信データとの大小を比較して、いずれか一方を選択受信データとして出力し、第ｋ段比較部（ｋは２≦ｋ≦ｎなる整数である）は、第（ｋ−１）段比較部から出力された選択受信データとそれよりも２^ｋ−１個前の選択受信データとを比較して、いずれか一方を選択受信データとして出力し、前記ｎ段の比較部は、それら全体として、前記第１段比較部に順次入力された２^ｎ個の受信データ中の最大値又は最小値を抽出する。
【００２４】
本発明によれば、一連の受信データに沿って、所定のウィンドウを順次シフトさせて設定する。そして上述の最大値又は最小値を抽出する本発明に係る信号処理回路を用いて各ウィンドウ位置での、そのウィンドウに含まれるデータの最大値又は最小値が抽出され、その抽出値を用いて超音波画像が生成される。
【００２５】
本発明の好適な態様の超音波診断装置においては、前記選択条件が、比較される２つのデータのうち大きい方を選択する条件であり、これにより前記ｎ段の比較部は、前記第１段比較部に順次入力された２^ｎ個のデータ中の最大値を抽出する。また本発明の他の好適な態様の超音波診断装置においては、前記選択条件が、比較される２つのデータのうち小さい方を選択する条件であり、これにより前記ｎ段の比較部は、前記第１段比較部に順次入力された２^ｎ個のデータ中の最小値を抽出する。
【００２６】
他の本発明に係る超音波診断装置は、超音波の送受波によって得られた受信データ列に対して第１ウィンドウを設定し、前記第１ウィンドウ内の複数の受信データの中から、最大値又は最小値の一方を抽出して、その抽出された選択データを出力する第１抽出部と、前記第１抽出部から得られる選択データ列に対して第２ウィンドウを設定し、前記第２ウィンドウ内の複数の選択データの中から、最大値又は最小値の他方を抽出して、その抽出された選択受信データを出力する第２抽出部と、前記第２抽出部から順次出力される選択受信データを用いて超音波画像を生成する画像生成部とを有し、前記第１抽出部は、所定の第１選択条件に従って動作する段階的に接続されたｎ段（ｎは２以上の整数である）の第１比較部を有し、第１段の前記第１比較部は、現在の入力受信データとそれよりも１つ前の入力受信データとの大小を比較して、いずれか一方を選択データとして出力し、第α段の前記第１比較部（αは２≦α≦ｎなる整数である）は、第（α−１）段の前記第１比較部から出力された選択データとそれよりも２^{α −１}個前の選択データとの大小を比較して、いずれか一方を選択データとして出力し、前記第２抽出部は、所定の第２選択条件に従って動作する段階的に接続されたｍ段（ｍは２以上の整数である）の第２比較部を有し、第１段の前記第２比較部は、現在入力された選択データとそれよりも１つ前に入力された選択データとの大小を比較して、いずれか一方を選択データとして出力し、第β段の前記第２比較部（βは２≦β≦ｍなる整数である）は、第（β−１）段の前記第２比較部から出力された選択データとそれより２^{β −１}個前の選択データとの大小を比較して、いずれか一方を選択データとして出力し、前記第１選択条件は、比較される２つのデータのうち大きい方又は小さい方のいずれか一方を選択する条件であり、前記第２選択条件は、比較される２つのデータのうち大きい方又は小さい方のいずれか他方を選択する条件であることである。
【００２７】
本発明によれば、例えば、第１抽出部が一連の受信データに対して順次シフトしてウィンドウ（第１ウィンドウ）を設定し、各ウィンドウ位置にてそのウィンドウに含まれる受信データの最大値を抽出する。一方、第２抽出部は第１抽出部から出力される最大値データの列に対して順次シフトしてウィンドウ（第２ウィンドウ）を設定し、各ウィンドウ位置にてそのウィンドウに含まれる最大値データのうちの最小値を抽出する。すなわち、第１抽出部及び第２抽出部は受信データに対するクロージングフィルタを構成する。また第１抽出部が最小値を抽出し、第２抽出部が最大値を抽出する構成では、それらは受信データに対するオープニングフィルタを構成する。これら第１抽出部、第２抽出部がそれぞれ上述の本発明に係る最大値又は最小値を抽出する信号処理回路により、簡素な構成で実現される。
【００２８】
【発明の実施の形態】
次に、本発明の実施形態について図面を参照して説明する。
【００２９】
図１は、本発明の実施形態である超音波診断装置の概略のブロック構成図である。本装置は、被検体内を三次元表示するものであり、特に血管を三次元表示する機能を有する。
【００３０】
超音波探触子２０は、例えばリニアアレイ型の超音波振動子を有し、その超音波振動子を電子走査（リニア走査、セクタ走査）することによって、走査面が形成される。この走査面を当該面の法線方向へ例えば機械的に走査することによって、三次元空間でのエコーデータが取得される。ここで、超音波探触子２０の機械的な走査は図示しない駆動部によって行われている。
【００３１】
送信器２２は超音波探触子２０に対して送信信号を供給する。振動子アレイを構成する個々の振動子が発する超音波の合成により超音波ビームが形成されるように、送信器２２は各振動子へ位相をずらして励振パルスを供給する。
【００３２】
受信器２４は超音波探触子２０の各振動子から出力された受信信号を整相加算し、被検体の表面から深さ方向に延びる音線に沿った受信信号を出力する。
【００３３】
検波器２６は、受信器２４から出力される受信信号を検波して、ベースバンドの受信信号を抽出する。受信信号は、受信器２４又は検波器２６にてＡＤ（Ａｎａｌｏｇ−ｔｏ−Ｄｉｇｉｔａｌ）変換され、検波器２６からは受信信号がデジタルデータとして出力される。
【００３４】
モルフォロジーフィルタ部２８は、検波器２６から入力された受信信号に対し、その時間軸方向に関する一次元のクロージング処理又はオープニング処理を行うモルフォロジーフィルタを備えている。
【００３５】
メモリ部３０は、モルフォロジーフィルタ部２８から音線に沿って出力されるデータを記憶する。メモリ部３０には、超音波探触子２０により走査された三次元空間に対応したデータが格納される。
【００３６】
三次元画像構築部３２は、メモリ部３０に格納された三次元のデータ空間に対して、複数の視線を設定する。そして、各視線に沿ってボリュームレンダリング法などによる三次元画像生成処理を行い、視線ごとに三次元画像の画素値が求められる。
【００３７】
フレームバッファ３４は、三次元画像構築部３２から視線ごとに出力される画素値を順次記憶する。これによりフレームバッファ３４には、一画面分の三次元画像が格納される。
【００３８】
表示部３６は、フレームバッファ３４に格納された画像データを所定の順序・速度で読み出し、画像表示する。
【００３９】
図２はモルフォロジーフィルタ部２８の概略構成を示すブロック図である。モルフォロジーフィルタ５０は、入力された所定幅のデータ列において最大値を検出する最大値演算回路５２と、入力された所定幅のデータ列において最小値を検出する最小値演算回路５４とから構成される。ここでは、最大値演算回路５２の後に最小値演算回路５４を直列接続し、これらの直列接続体がモルフォロジーフィルタ５０を構成する。この構成のモルフォロジーフィルタ５０は、ウィンドウ幅の谷部を埋めるクロージング処理を行う。さらに、モルフォロジーフィルタ部２８は、モルフォロジーフィルタ５０での処理時間に応じた遅延を生じる遅延回路５６及び減算回路５８を備える。
【００４０】
検波器２６から入力されたデータ列は、モルフォロジーフィルタ５０及び遅延回路５６にそれぞれ入力される。そして、減算回路５８は、モルフォロジーフィルタ５０の出力データから、遅延回路５６の出力データを減算し、これをモルフォロジーフィルタ部２８から出力する。
【００４１】
ここで血管内部は血液であり、このほぼ一様な液体からのエコーは非常に微弱である。そのため血管部位での受信信号の波形は急峻に落ち込んで谷部を形成し、その谷部の幅は血管のサイズに対応して比較的狭い。モルフォロジーフィルタ５０のウィンドウ幅をこの谷部の幅に応じて設定することにより、その谷部が埋められた信号がモルフォロジーフィルタ５０から出力される。
【００４２】
遅延回路５６は検波器２６から出力された元の受信信号と、モルフォロジーフィルタ５０の出力信号とを同期させる。しかる後、減算回路５８にて、モルフォロジーフィルタ５０の出力信号から元の受信信号を減算して差分信号を生成することで、その差分信号には血管部位に対応する谷部の信号波形が反転された形で抽出される。すなわち、血管部位にて大きな信号値を有する信号が生成され、これを用いて超音波画像を生成することにより、血管が見やすく表示された画像が得られる。
【００４３】
図３は、最大値演算回路５２又は最小値演算回路５４となる信号処理回路の模式的なブロック構成図である。この信号処理回路は、ウィンドウ幅２^ｎのデータ列中の最大値又は最小値を抽出するものであり、図３に示す例ではｎ＝６である。この信号処理回路は、比較器７０及びシフトレジスタ７２からなる比較部が多段に接続されて構成される。その段数はｎ＝６に対応して６段である。第ｋ段比較部（ｋ＝１〜６）は比較器７０−ｋとシフトレジスタ７２−ｋとで構成される。各比較器７０は２個のデータを入力され、それらの大小関係を比較し、いずれか一方のデータを出力する。最大値演算回路５２では各比較器７０は２個の入力データのうち大きい方（２個のデータが同じ値である場合には、その値）を出力する。一方、最小値演算回路５４では各比較器７０は２個の入力データのうち小さい方（２個のデータが同じ値である場合には、その値）を出力する。またシフトレジスタ７２−ｋは２^ｋ−１段のビットで構成され、入力されるデータを順に２^ｋ−１個保持することができる。シフトレジスタ７２中の最も古いデータは新たなデータの入力に同期して出力され、シフトレジスタ７２の記憶内容は順次更新される。このようにシフトレジスタ７２は入力データ２^ｋ−１個分の遅延を生じる遅延回路として機能する。
【００４４】
以下、当該信号処理回路が最大値演算回路５２を構成する場合を説明する。以下の説明において、ｉは装置のクロックカウントを表す変数である。このクロックカウントは時刻に対応付けられ、以下の説明で“時刻ｉ”は“クロックカウントがｉとなる時刻”を意味する。そして、カウント値ｉにおけるこの信号処理回路への入力データをＤ_０（ｉ）、また各段の比較器７０−ｋの出力データをＤ_ｋ（ｉ）と表記する。
【００４５】
時刻ｊにおいて、データＤ_０（ｊ）は第１段比較部を構成する比較器７０−１及びシフトレジスタ７２−１にそれぞれ入力される。ｊ≧２なる時刻ｊでは、シフトレジスタ７２−１は先行して入力された１個のデータＤ_０（ｊ−１）を保持している。そして、シフトレジスタ７２−１はデータＤ_０（ｊ）の入力に同期して、保持しているデータＤ_０（ｊ−１）を出力する。比較器７０−１は最大値演算回路５２に入力されるデータＤ_０（ｊ）と、シフトレジスタ７２−１から出力される遅延されたデータＤ_０（ｊ−１）とを入力される。比較器７０−１は入力されたＤ_０（ｊ−１）とＤ_０（ｊ）との大小を比較して、いずれか大きい方を、時刻ｊにおける出力データＤ_１（ｊ）とする。すなわち、第１段比較部は、Ｄ_０（ｉ）（ｉ＝１，２，３，…２^ｎ−１，２^ｎ，…）を入力されると、Ｄ_０（１）及びＤ_０（２）、Ｄ_０（２）及びＤ_０（３）、…、Ｄ_０（２^ｎ−１）及びＤ_０（２^ｎ）、…に対し、それぞれ大小比較を行い、いずれか大きい方の値を選択して、Ｄ_１（２）、Ｄ_１（３）、…、Ｄ_１（２^ｎ）、…を出力する。
【００４６】
時刻ｊにて比較器７０−１から出力されたデータＤ_１（ｊ）は第２段比較部を構成する比較器７０−２及びシフトレジスタ７２−２にそれぞれ入力される。ｊ≧４なる時刻ｊでは、シフトレジスタ７２−２は先行して入力された２個のデータＤ_１（ｊ−２）、Ｄ_１（ｊ−１）を保持している。シフトレジスタ７２−２は、データＤ_１（ｊ）の入力タイミングに同期して、最先に格納されたデータＤ_１（ｊ−２）を出力する。比較器７０−２は、比較器７０−１から出力されるデータＤ_１（ｊ）と、シフトレジスタ７２−２から出力される遅延されたデータＤ_１（ｊ−２）とを入力される。比較器７０−２は入力されたＤ_１（ｊ）とＤ_１（ｊ−２）との大小を比較して、いずれか大きい方を、時刻ｊにおける出力データＤ_２（ｊ）とする。すなわち、第２段比較部は、Ｄ_１（ｉ）（ｉ＝２，３，４，…）を入力されると、Ｄ_１（２）及びＤ_１（４）、Ｄ_１（３）及びＤ_１（５）、…に対し、それぞれ大小比較を行い、いずれか大きい方の値を選択して、Ｄ_２（４）、Ｄ_２（５）、…を出力する。
【００４７】
以上、第１段比較部及び第２段比較部に関して説明したのと同様の処理が、第３〜６段比較部においても行われる。一般化して、第ｋ段比較部（ｋ＝２〜６）に関して述べれば、時刻ｉ≧２^ｋ−１にて比較器７０−（ｋ−１）から出力されるデータ列Ｄ_ｋ−１（ｉ）は第ｋ段比較部を構成する比較器７０−ｋ及びシフトレジスタ７２−ｋにそれぞれ入力される。ある時刻ｊにおいて、シフトレジスタ７２−ｋは２^ｋ−１個のデータＤ_ｋ−１（ξ）（ξ＝ｊ−２^ｋ−１〜ｊ−１）を保持し、データＤ_ｋ−１（ｊ）の入力タイミングに同期して、最先に格納されたデータＤ_ｋ−１（ｊ−２^ｋ−１）を出力する。例えば、第（ｋ−１）段比較部から第ｋ段比較部へのデータ入力をｋ＝４の場合について具体的に述べれば、時刻ｊでは、第３段比較部の比較器７０−３から第４段比較部の比較器７０−４にデータＤ_３（ｊ）が入力されると共に、シフトレジスタ７２−４からは最先に格納されたデータＤ_３（ｊ−２^３）が出力される（図３参照）。このように、比較器７０−ｋは、比較器７０−（ｋ−１）から順次出力されるデータＤ_ｋ−１（ｊ）と、シフトレジスタ７２−ｋから順次出力される遅延されたデータＤ_ｋ−１（ｊ−２^ｋ−１）とを入力される。比較器７０−ｋはこれら入力された２つのデータの大小を比較して、いずれか大きい方を時刻ｊにおける出力データＤ_ｋ（ｊ）とする。すなわち、第ｋ段比較部は、Ｄ_ｋ−１（ｉ）（ｉ＝２^ｋ−１，２^ｋ−１＋１，２^ｋ−１＋２，…）を入力されると、Ｄ_ｋ−１（２^ｋ−１）及びＤ_ｋ−１（２^ｋ）、Ｄ_ｋ−１（２^ｋ−１＋１）及びＤ_ｋ−１（２^ｋ＋１）、…に対し、それぞれ大小比較を行い、いずれか大きい方の値を選択して、Ｄ_ｋ（２^ｋ）、Ｄ_ｋ（２^ｋ＋１）、…を出力する。
【００４８】
以上の構成により、第１段比較部にウィンドウを構成する６４個のＤ_０（ξ）（ξ＝ｊ−２^６＋１〜ｊ）が入力されると、最終段である第６段比較部からは、当該ウィンドウ内のデータＤ_０のうちの最大値がＤ_６（ｊ）として出力される。また、第１段比較部に次のデータＤ_０（ｊ＋１）が入力されると、ウィンドウ位置は１データずれることとなり、そのウィンドウに含まれる６４個のＤ_０（ξ）（ξ＝ｊ−２^６＋２〜ｊ＋１）のうちの最大値がＤ_６（ｊ＋１）として出力される。このようにして最大値演算回路５２へのデータの入力に同期して、ウィンドウが順次シフトされ、その各ウィンドウ内の最大値が最大値演算回路５２から順次出力される。
【００４９】
上述の最大値演算回路５２及び最小値演算回路５４を構成する信号処理回路は、一次元のデータ列に設定された一次元のウィンドウ内でのデータの最大値又は最小値を抽出するものであった。しかしながら、この信号処理回路を用いて、二次元のウィンドウ内でのデータの最大値又は最小値を抽出するフィルタを構成することもできる。
【００５０】
例えば、本発明の信号処理回路である最大値演算回路を用いて構成される二次元最大値抽出フィルタの構成を説明する。ここで述べる二次元最大値抽出フィルタの例は、３段（すなわちｎ＝３）の比較部で構成された最大値演算回路を用いて、８×８の大きさを有する二次元ウィンドウ内での最大値を抽出する。この二次元最大値抽出フィルタは、元の二次元データ群Ｄ_０（ｘ，ｙ）（ｘ＝１，２，３，…；ｙ＝１，２，３，…）から、例えば、まず行方向（ｘが変化する方向）に並ぶデータ群を読み出して、最大値演算回路に入力する。この処理を、行の位置ｙを変えて、各行データ群について実行する。これにより得られた二次元データ群をＤ_１（ｘ，ｙ）としてメモリに格納する。Ｄ_１（ｘ，ｙ’）は第ｙ’行に並ぶ８個のデータＤ_０（η，ｙ’）（η＝ｘ〜ｘ＋７）のうちの最大値である。次にＤ_１（ｘ，ｙ）から列方向（ｙが変化する方向）に並ぶデータ群を読み出して、最大値演算回路に入力する。この処理を、列の位置ｘを変えて、各列データ群について実行する。これにより得られた二次元データ群がＤ_２（ｘ，ｙ）としてメモリに格納される。Ｄ_２（ｘ’，ｙ）はＤ_１（ｘ，ｙ）の第ｘ’列に並ぶ８個のデータＤ_１（ｘ’，ξ）（ξ＝ｙ〜ｙ＋７）のうちの最大値である。このように生成されたＤ_２（ｘ，ｙ）が８×８のウィンドウ内のデータＤ_０（η，ξ）（η＝ｘ〜ｘ＋７；ξ＝ｙ〜ｙ＋７）のうちの最大値からなる二次元データ群として、二次元最大値抽出フィルタから出力される。同様の原理で、二次元最小値抽出フィルタも構成することができる。これら二次元最大値抽出フィルタと二次元最小値抽出フィルタとを組み合わせて、二次元のモルフォロジーフィルタを構成し、超音波画像に対して、クロージング処理やオープニング処理を施すことができる。
【００５１】
【発明の効果】
本発明の信号処理回路によれば、小さな回路規模で最大値又は最小値の抽出を行うことができる。またそれを用いた超音波診断装置の小型化、低コスト化が図られる。
【図面の簡単な説明】
【図１】本発明の実施形態である超音波診断装置の概略のブロック構成図である。
【図２】モルフォロジーフィルタ部の概略構成を示すブロック図である。
【図３】最大値演算回路又は最小値演算回路となる信号処理回路の模式的なブロック構成図である。
【図４】クロージングフィルタの概略構成を示すブロック図である。
【図５】従来の第１の最大値抽出回路の模式的な構成図である。
【図６】従来の第２の最大値抽出回路の模式的な構成図である。
【図７】図６の最大値抽出回路に用いられる最大値記憶回路のブロック構成図である。
【符号の説明】
２０　超音波探触子、２２　送信器、２４　受信器、２６　検波器、２８　モルフォロジーフィルタ部、３０　メモリ部、３２　三次元画像構築部、３４　フレームバッファ、３６　表示部、５０　モルフォロジーフィルタ、５２　最大値演算回路、５４　最小値演算回路、５６　遅延回路、５８　減算回路、７０　比較器、７２　シフトレジスタ。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal processing circuit for extracting a maximum value or a minimum value from a data sequence, and an ultrasonic diagnostic apparatus using the signal processing circuit.
[0002]
[Prior art]
Conventionally, various filters have been used to remove unnecessary noise and signals from observed time-series data. Smoothing filters are the most typical and are used very often. This smoothing filter sequentially outputs the average value of the data in the window while moving the window along the data sequence.
[0003]
A smoothing filter is a typical example of a linear filter. Although the smoothing filter has excellent characteristics, it is not preferable to extract a rapidly changing signal portion because the signal waveform is largely deformed. A morphological filter, which is a non-linear filter, has attracted attention as a filter having a characteristic of removing an unnecessary signal while suppressing the deformation of a signal waveform at such a sharply changing edge portion. The morphological filter, for example, does not change the basic waveform of an input signal waveform that is convex upwards, but fills in the signal portion that is concave downwards. Has been devised. Also, an opening filter (Opening @ Filter) has been devised as a morphology filter having the opposite characteristic. This filter does not change the basic waveform of a portion where the waveform of the input signal is depressed downward. Thus, there is a characteristic that an upwardly convex signal portion is cut off.
[0004]
The closing filter and the opening filter can be configured by combining a maximum value extraction circuit and a minimum value extraction circuit. Here, the maximum value extracting circuit moves the window along the input data sequence and sequentially outputs the maximum value in the window, while the minimum value extracting circuit moves the window along the input data sequence. And sequentially outputs the minimum value within the window. FIG. 4 is a block diagram showing a schematic configuration of the closing filter. The closing filter 100 includes a maximum value extraction circuit 102 to which an input data sequence is input, and a minimum value extraction circuit 104 to which an output data sequence of the maximum value extraction circuit is input. On the other hand, the opening filter has a configuration in which the connection order of the maximum value extraction circuit and the minimum value extraction circuit is opposite to that of the closing filter. The characteristics of the closing filter and the opening filter can be largely changed by changing the size of the window.
[0005]
FIG. 5 is a schematic configuration diagram of a conventional first maximum value extraction circuit. This circuit includes a shift register 110 capable of holding data of a number corresponding to the size of a window, and a plurality of comparators 112. The shift register 110 has a configuration in which storage circuits called “bits” each capable of storing one data are connected in multiple stages, and data sequentially input to the shift register 110 sequentially shifts each bit in one direction in synchronization with a clock. (Rightward in FIG. 5).
[0006]
The data stored in the shift register can be read from each bit. A group of comparators 112 detects and outputs the maximum value by a tournament method from a plurality of data read out simultaneously from each bit of the shift register 110. That is, the first stage comparator 112-1 is provided for every two adjacent bits of the shift register 110, reads out the data held in the two bits, compares their data values, Output large value data. The second-stage comparator 112-2 compares the data output from the two first-stage comparators 112-1, and outputs a larger value. As described above, a large value is sequentially selected in each stage of the comparator group, and one value finally left is the maximum value. Each time data is input to the shift register 110, a maximum value detection process is performed in the comparator group and output from the filter output terminal.
[0007]
For example, if the window is 2^kIf the data is composed of a plurality of data, the comparator 112 is formed in a k-stage tournament configuration, and a total of 2^k1 is required.
[0008]
FIG. 6 is a schematic configuration diagram of a conventional second maximum value extraction circuit. This circuit controls a maximum value storage circuit 120 of a number corresponding to the size of the window, a selection circuit 122 for selecting an output of the maximum value storage circuit 120, and resetting of the maximum value storage circuit 120 and switching of the selection circuit. It comprises a control circuit 124. FIG. 7 is a block diagram of the maximum value storage circuit 120. The maximum value storage circuit 120 includes a comparator 130 and a shift register 132. The shift register 132 has a one-stage configuration, and functions as a delay circuit that holds output data of the comparator 130 and outputs the data one clock later. The comparator 130 receives the data input to the maximum value storage circuit 120 for each clock and the data output from the shift register 132, compares the data, and compares the two data as a comparison result. Whichever is greater is retained and output. With this configuration, the content held in the comparator 130 is gradually updated with the maximum value of the data input after the previous reset, and the maximum value is output from the maximum value storage circuit 120.
[0009]
The control circuit 124 resets each of the maximum value storage circuits 120 at a time interval at which the number of data constituting the window is input. The reset cycle is set so as to be shifted by one clock from each of the maximum value storage circuits 120, and the control circuit 124 controls the selection circuit 122 to select and output the output data of the maximum value storage circuit 120 immediately before the reset. Control. Thus, the maximum value in each window shifted by one data is sequentially output.
[0010]
The conventional configuration of the maximum value extracting circuit has been described above. However, if the comparators 112 and 130 are configured to output the smaller of the two input data, the minimum value extracting circuits are obtained.
[0011]
[Problems to be solved by the invention]
The above-mentioned conventional first maximum value (or minimum value) extraction circuit requires approximately the same number of comparators 112 as the number of data constituting the window, and the second maximum value (or minimum value) extraction circuit requires Requires the same number of maximum value storage circuits 120 (or minimum value storage circuits) as the number of data constituting the window, and in any case, the circuit scale increases with the window size. Further, in the first conventional circuit, it is necessary to perform k-stage comparison operation by the comparator group in synchronization with one input / output clock to the shift register 110. Therefore, there is a problem that the comparator group is operated with a clock that is k times the drive clock of the shift register.
[0012]
In addition, the ultrasonic diagnostic apparatus also has a problem in that the size of the apparatus is increased by adopting the above-described conventional maximum value (or minimum value) extraction circuit for the signal processing filter.
[0013]
The present invention has been made to solve the above problems, and a signal processing circuit capable of extracting a maximum value or a minimum value with a small-scale circuit, and miniaturization and cost reduction by using the signal processing circuit. It is an object of the present invention to provide an ultrasonic diagnostic apparatus.
[0014]
[Means for Solving the Problems]
A signal processing circuit according to the present invention includes n stages (n is an integer of 2 or more) of comparators connected in stages operating in accordance with a predetermined selection condition. The input data and the immediately preceding input data are compared in magnitude and one of them is output as selected data, and the k-th stage comparison unit (k is an integer satisfying 2 ≦ k ≦ n) The selection data output from the (k-1) th stage comparison unit and the selection data^k-1The selected data is compared with the previous selected data, and either one of the data is output as selected data. The n-stage comparison units as a whole are sequentially input to the first-stage comparison unit.ⁿThe maximum value or the minimum value among the data is extracted.
[0015]
In the signal processing circuit according to a preferred aspect of the present invention, the selection condition is to select a larger one of the two data to be compared, whereby the n-stage comparison unit performs the first-stage comparison. 2 sequentially input toⁿExtract the maximum value of the data.
[0016]
According to the mode of extracting the maximum value, the signal processing device of the present inventionⁿThe extraction of the maximum value among the data can be performed by n comparison units. That is, the width of the window that is the search range of the maximum value is 2ⁿIn the case of, the maximum value can be extracted with only n comparison units. This will be described for the case where n = 3 (that is, the width of the window is 8), using a specific example shown in Table 1 below.
[0017]
[Table 1]

In this table, the first column from the left labeled "i" corresponds to the count of the clock for driving the device and represents the time. "D₀The second column from the left, denoted by (i) ", is the input data to the first stage comparison unit at the i-th clock, and further, each column is" D₁(I) "," D₂(I) "," D₃The third, fourth, and fifth columns from the left, denoted by (i) ", represent outputs at the i-th clock from the first-stage comparator, the second-stage comparator, and the third-stage comparator, respectively. The data contained in the window is input one by one to the first stage comparing unit.₀(1) -D₀(8) (that is, if the data includes “30”, “31”, “0”, “33”, “34”, “0”, “0”, “37” shown in Table 1), The comparison unit is D₀(1) and D₀(2), D₀(2) and D₀(3), ..., D₀(7) and D₀For (8), a magnitude comparison is performed for each, and the larger value (if the values of the two data to be compared are equal, the value is selected) is selected, and D is selected.₁(2), D₁(3), ..., D₁As (7), “31”, “31”, “33”, “34”, “34”, “0”, and “37” are output. The second-stage comparison unit uses D₁(2) and D₁(4), D₁(3) and D₁(5), ..., D₁(6) and D₁For (8), a magnitude comparison is performed, and the larger value is selected.₂(4), D₂(5), ..., D₂As (8), “33”, “34”, “34”, “34”, “37” are output. Here, for example, D₂(4) is D₁(2) and D₁(4) whichever is greater, and D₁(2) is D₀(1) and D₀The larger of (2) and D₁(4) is D₀(3) and D₀(4), whichever is greater, so after all, D₂(4) is four data D₀(1) -D₀It becomes the maximum value of (4). Similarly, D₂(8) is four data D₀(5) -D₀It becomes the maximum value of (8). In addition, the third-stage comparison unit calculates D₂(4) and D₂Performing the magnitude comparison of (8), selecting the larger one,₃"37" is output as (8). As mentioned above, D₂(4) is D₀(1) -D₀The maximum value of (4), D₂(8) is D₀(5) -D₀Since it is the maximum value of (8), the D output from the third stage comparing unit is eventually obtained.₃(8) is D₀(1) -D₀It becomes the maximum value of (8). As described above, 2³The maximum value in the window including the data is extracted by three comparison units connected in three stages. As can be seen from this, the window width 2ⁿThe maximum value can be extracted with respect to the data string by the n-stage comparison unit.
[0018]
If the window width is 2ⁿNot 2ⁿ+ Α (where α <2ⁿ), 2ⁿMaximum value V₁Is obtained by the n-stage comparison unit, and the maximum value V among the remaining α values is obtained.₂Is obtained by an additional comparison unit provided separately from the n-stage comparison unit.₁And V₂Is configured to select whichever is greater. This additional comparison unit can be configured using a well-known maximum value extraction circuit, or if α is 2^m1+2^m2+ ... (m1, m2 <n), having the same configuration as the n-stage comparison unit, and using a comparison unit with a smaller number of stages (that is, m1 stages, m2 stages,...) You can also.
[0019]
The configuration of the signal processing circuit for extracting the maximum value has been described above as an example, but the same applies to the signal processing circuit of another preferred embodiment of the present invention for extracting the minimum value. In that case, the selection condition is to select the smaller one of the two data to be compared, whereby the n-stage comparison unit sequentially selects the two data sequentially input to the first-stage comparison unit.ⁿExtract the minimum value from the data.
[0020]
In the signal processing circuit according to another aspect of the present invention, the k-th stage comparing section may select the selection data output from the (k-1) -th stage comparing section by two.^k-1A data holding unit that holds the data and outputs the delayed data; a selection data that is currently output from the (k−1) th comparing unit;^k-1And a comparator for comparing the magnitude with the previous selected data.
[0021]
One set of twoⁿIf only the maximum value or the minimum value in the data is extracted, not all of the output data of the comparison units in each stage is necessary. For example, based on the above description regarding the extraction of the maximum value, 2ⁿData D₀(I) (i = 1 to 2ⁿ)), The n-th stage comparing section determines the maximum value in the series of output data of the (n-1) -th stage comparing section when calculating the maximum value in the window W (1)._n-1(2ⁿ) And 2 more^n-1D obtained before clock_n-1(2^n-1) Is sufficient. When the data necessary for detecting the maximum value is sequentially traced back to the preceding stage, the k-th stage comparing unit outputs two of a series of output data of the (k-1) -th stage comparing unit.^k-1Every other data D_k-1(2ⁿ−λ · 2^k-1) (Λ = 0,1, ..., 2^nk) Only. Here, when the windows are sequentially shifted and the maximum value or the minimum value included in the window is extracted at each window position, the data required in the comparison unit of each stage is also sequentially shifted. For example, the window W (2) shifted by one data from the window W (1), that is, the data D₀(I) (i = 2-2)ⁿWhen obtaining the maximum value for the window consisting of +1), the data required in the comparison unit of each stage is also shifted one by one from the data required in the processing for the window W (1). The k-th stage comparison unit outputs D for window W (1)._k-1(2ⁿ−λ · 2^k-1), But D for window W (2)_k-1(2ⁿ−λ · 2^k-1+1). In the signal processing circuit according to another embodiment of the present invention described here, the comparison unit of each stage holds the data output from the previous stage comparison unit up to a predetermined number of past times and outputs the data in a delayed manner, so that the data is sequentially shifted and set. The maximum value or the minimum value in a given window can be sequentially extracted. Specifically, the k-th stage comparator compares the data output from the (k-1) -th stage comparator with 2^k-1Up to the previous one is held in the data holding means. For example, the data currently output from the (k−1) th stage comparing unit is_k-1(J), at that point, the data holding means has D_k-1(Ξ) (ξ = j-2^k-1To j-1) are held. Then, the k-th stage comparing section outputs the newly output D_k-1(J) and the oldest D among the data held in the data holding means._k-1(J-2^k-1) And D_k(J) while D_k-1(J) is stored in the data holding means. When shifting windows sequentially, the oldest D at this stage_k-1(J-2^k-1) Becomes unnecessary and can be deleted from the data holding means. The data holding means can be constituted by a memory, for example. When the windows are sequentially shifted, the data held in the data holding means is used in order from the oldest data, so that the data holding means can be constituted by a delay circuit, and a shift register is used as the delay circuit, for example. be able to.
[0022]
Still another signal processing circuit according to the present invention sets a two-dimensional window for a two-dimensional data array, and among a plurality of data in the two-dimensional window, a maximum value or a maximum value according to a predetermined selection condition. Extracting a minimum value, for each data string in the window, sequentially inputting a plurality of data constituting the data string, extracting a maximum value or a minimum value from among them, and extracting the extracted data. A first extraction unit that outputs the extracted data, and a plurality of data extracted for each data string by the first extraction unit are sequentially input, and a maximum value or a minimum value is extracted from them, and the extracted A second extraction unit that outputs the data obtained by the first extraction unit, wherein the first extraction unit includes n stages (n is an integer of 2 or more) of first comparison units connected in a stepwise manner. The first comparison unit of the column is the current input data The input data before that is compared with the previous input data, and either one is output as selection data, and the first comparison unit at the k-th stage (k is an integer satisfying 2 ≦ k ≦ n) The selection data output from the first comparison unit of the (k-1) th stage and the selection data^k-1The n-th stage first comparison unit compares the selected data with the previous selection data and outputs one of the selection data as the selection data. Extract the maximum value or the minimum value from the data, and output the extracted data. The second extraction unit determines the m-th stage (m is an integer of 2 or more) connected stepwise. A second comparing unit, the second comparing unit of the first stage compares the magnitude of the current input data with the immediately preceding input data, and outputs one of them as selection data; The k-th stage second comparison unit (k is an integer satisfying 2 ≦ k ≦ m) selects the selection data output from the (k−1) -th stage second comparison unit and the selected data by 2^k-1Compares the selected data with the previous one and outputs one of them as selection data, and the m-stage comparison unit as a whole outputs a plurality of data sequentially input to the second comparison unit of the first stage The maximum or minimum value is extracted.
[0023]
The ultrasonic diagnostic apparatus according to the present invention sets a window for a received data sequence obtained by transmitting and receiving ultrasonic waves, and extracts a maximum value or a minimum value from a plurality of pieces of received data in the window. An extraction unit that outputs the extracted reception data, and an image generation unit that generates an ultrasound image using the reception data sequentially output from the extraction unit, wherein the extraction unit performs a predetermined selection. An n-stage (n is an integer of 2 or more) stage-by-stage comparison unit that operates in accordance with a condition, wherein the first-stage comparison unit includes the current input received data and the input data immediately before it. The magnitude of the received data is compared with that of the received data, and one of them is output as the selected received data, and the k-th stage comparator (k is an integer satisfying 2 ≦ k ≦ n) is compared with the (k−1) -th stage comparator. Received data output from^k-1The selected reception data is compared with the previous selection reception data, and one of them is output as the selection reception data, and the n-stage comparison units as a whole are sequentially inputted to the first-stage comparison unit.ⁿThe maximum value or the minimum value among the received data is extracted.
[0024]
According to the present invention, a predetermined window is sequentially shifted and set along a series of received data. Then, the maximum value or the minimum value of the data included in the window at each window position is extracted using the signal processing circuit according to the present invention for extracting the maximum value or the minimum value, and the extracted value is used to determine the maximum value. A sound image is generated.
[0025]
In the ultrasonic diagnostic apparatus according to a preferred aspect of the present invention, the selection condition is a condition for selecting a larger one of the two data to be compared, whereby the n-stage comparison unit performs the first-stage comparison. 2 sequentially input to the comparison unitⁿExtract the maximum value of the data. In the ultrasonic diagnostic apparatus according to another preferred aspect of the present invention, the selection condition is a condition for selecting a smaller one of the two data to be compared. 2 sequentially input to the first stage comparatorⁿExtract the minimum value from the data.
[0026]
Another ultrasonic diagnostic apparatus according to the present invention sets a first window for a received data sequence obtained by transmitting and receiving ultrasonic waves, and sets a maximum value among a plurality of received data in the first window. Or a first extractor for extracting one of the minimum values and outputting the extracted selected data, and setting a second window for the selected data sequence obtained from the first extractor, A second extraction unit that extracts the other of the maximum value or the minimum value from the plurality of selection data items and outputs the extracted selection reception data; and a selection reception unit that is sequentially output from the second extraction unit. An image generation unit that generates an ultrasonic image using data, wherein the first extraction unit is configured to operate in accordance with a predetermined first selection condition and to be connected in stages (n is an integer of 2 or more). A) the first comparison unit, before the first stage The first comparing unit compares the current input received data with the immediately preceding input received data and outputs one of them as selection data, and outputs the selected data as the selected data. α is an integer satisfying 2 ≦ α ≦ n) is the selected data output from the first comparison unit in the (α-1) th stage and the selected data^{α -1}The second extraction unit compares the magnitude with the previous selection data and outputs one of them as the selection data, and the second extracting unit operates stepwise connected m stages (m is The second comparison unit of the first stage, the second comparison unit of the first stage determines the magnitude of the currently input selection data and the selection data input immediately before it. In comparison, one of them is output as selection data, and the second comparison unit (β is an integer satisfying 2 ≦ β ≦ m) in the β-th stage is used for the second comparison unit in the (β−1) -th stage. Selection data output from the unit and 2^{β -1}Compare the magnitude of the previous selection data and output one of them as selection data, and the first selection condition selects either the larger or the smaller of the two data to be compared. And the second selection condition is a condition for selecting the larger one or the smaller one of the two data to be compared.
[0027]
According to the present invention, for example, the first extractor sequentially shifts a series of received data to set a window (first window), and sets a maximum value of the received data included in the window at each window position. Extract. On the other hand, the second extractor sets a window (second window) by sequentially shifting the column of the maximum value data output from the first extractor, and sets the maximum value data included in the window at each window position. Is extracted. That is, the first extractor and the second extractor constitute a closing filter for the received data. In a configuration in which the first extractor extracts the minimum value and the second extractor extracts the maximum value, they constitute an opening filter for the received data. Each of the first extraction unit and the second extraction unit is realized with a simple configuration by the above-described signal processing circuit for extracting the maximum value or the minimum value according to the present invention.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings.
[0029]
FIG. 1 is a schematic block diagram of an ultrasonic diagnostic apparatus according to an embodiment of the present invention. The present apparatus three-dimensionally displays the inside of a subject, and particularly has a function of three-dimensionally displaying blood vessels.
[0030]
The ultrasonic probe 20 has, for example, a linear array type ultrasonic transducer, and a scanning surface is formed by electronically scanning (linear scanning, sector scanning) the ultrasonic transducer. Echo data in a three-dimensional space is acquired by, for example, mechanically scanning the scanning surface in the normal direction of the surface. Here, the mechanical scanning of the ultrasonic probe 20 is performed by a driving unit (not shown).
[0031]
The transmitter 22 supplies a transmission signal to the ultrasonic probe 20. The transmitter 22 supplies an excitation pulse to each of the transducers with a phase shift such that an ultrasonic beam is formed by combining the ultrasonic waves emitted from the individual transducers constituting the transducer array.
[0032]
The receiver 24 delays and adds the received signals output from the transducers of the ultrasonic probe 20, and outputs a received signal along a sound ray extending in the depth direction from the surface of the subject.
[0033]
The detector 26 detects the received signal output from the receiver 24 and extracts a baseband received signal. The received signal is subjected to AD (Analog-to-Digital) conversion by the receiver 24 or the detector 26, and the received signal is output from the detector 26 as digital data.
[0034]
The morphology filter unit 28 includes a morphology filter that performs one-dimensional closing processing or opening processing on the received signal input from the detector 26 in the time axis direction.
[0035]
The memory unit 30 stores data output from the morphology filter unit 28 along the sound ray. The memory unit 30 stores data corresponding to the three-dimensional space scanned by the ultrasonic probe 20.
[0036]
The three-dimensional image construction unit 32 sets a plurality of lines of sight in the three-dimensional data space stored in the memory unit 30. Then, a three-dimensional image generation process by a volume rendering method or the like is performed along each line of sight, and a pixel value of the three-dimensional image is obtained for each line of sight.
[0037]
The frame buffer 34 sequentially stores pixel values output from the three-dimensional image construction unit 32 for each line of sight. Thus, a three-dimensional image for one screen is stored in the frame buffer 34.
[0038]
The display unit 36 reads out the image data stored in the frame buffer 34 in a predetermined order and speed, and displays the image.
[0039]
FIG. 2 is a block diagram showing a schematic configuration of the morphology filter unit 28. The morphology filter 50 includes a maximum value operation circuit 52 for detecting a maximum value in an input data string of a predetermined width, and a minimum value operation circuit 54 for detecting a minimum value in an input data string of a predetermined width. . Here, the minimum value operation circuit 54 is connected in series after the maximum value operation circuit 52, and these serially connected components constitute the morphology filter 50. The morphological filter 50 having this configuration performs a closing process for filling a valley of the window width. Further, the morphology filter unit 28 includes a delay circuit 56 and a subtraction circuit 58 that generate a delay according to the processing time in the morphology filter 50.
[0040]
The data sequence input from the detector 26 is input to the morphological filter 50 and the delay circuit 56, respectively. Then, the subtraction circuit 58 subtracts the output data of the delay circuit 56 from the output data of the morphology filter 50, and outputs the result from the morphology filter unit 28.
[0041]
Here, the inside of the blood vessel is blood, and the echo from this almost uniform liquid is very weak. Therefore, the waveform of the received signal at the blood vessel site drops sharply to form a valley, and the width of the valley is relatively narrow in accordance with the size of the blood vessel. By setting the window width of the morphology filter 50 according to the width of the valley, a signal in which the valley is filled is output from the morphology filter 50.
[0042]
The delay circuit 56 synchronizes the original received signal output from the detector 26 with the output signal of the morphological filter 50. Thereafter, the subtraction circuit 58 subtracts the original received signal from the output signal of the morphology filter 50 to generate a difference signal, and the signal waveform of the valley corresponding to the blood vessel region is inverted in the difference signal. Extracted in the form. That is, a signal having a large signal value is generated at a blood vessel site, and an ultrasonic image is generated using the signal, thereby obtaining an image in which blood vessels are displayed in a legible manner.
[0043]
FIG. 3 is a schematic block diagram of a signal processing circuit serving as the maximum value operation circuit 52 or the minimum value operation circuit 54. This signal processing circuit has a window width of 2ⁿIs to extract the maximum value or the minimum value in the data sequence of FIG. 3. In the example shown in FIG. 3, n = 6. This signal processing circuit is configured such that a comparison unit including a comparator 70 and a shift register 72 is connected in multiple stages. The number of stages is six corresponding to n = 6. The k-th comparing section (k = 1 to 6) includes a comparator 70-k and a shift register 72-k. Each comparator 70 receives two pieces of data, compares their magnitudes, and outputs one of them. In the maximum value calculation circuit 52, each comparator 70 outputs the larger one of the two input data (if the two data have the same value, the value thereof). On the other hand, in the minimum value calculation circuit 54, each comparator 70 outputs the smaller one of the two input data (if the two data have the same value, the value thereof). The shift register 72-k is 2^k-1The input data is composed of two bits in order.^k-1Can be held individually. The oldest data in the shift register 72 is output in synchronization with the input of new data, and the stored contents of the shift register 72 are sequentially updated. Thus, the shift register 72 stores the input data 2^k-1It functions as a delay circuit that generates a delay corresponding to the number.
[0044]
Hereinafter, a case where the signal processing circuit forms the maximum value calculation circuit 52 will be described. In the following description, i is a variable representing the clock count of the device. This clock count is associated with time, and in the following description, “time i” means “time at which the clock count becomes i”. The input data to the signal processing circuit at the count value i is represented by D₀(I) Further, the output data of the comparator 70-k at each stage is represented by D_k(I).
[0045]
At time j, data D₀(J) is input to the comparator 70-1 and the shift register 72-1 which constitute the first stage comparison unit. At time j where j ≧ 2, the shift register 72-1 stores one data D which has been input in advance.₀(J-1). The shift register 72-1 stores the data D₀Data D held in synchronization with the input of (j)₀(J-1) is output. The comparator 70-1 outputs the data D input to the maximum value arithmetic circuit 52.₀(J) and the delayed data D output from the shift register 72-1.₀(J-1) is input. The comparator 70-1 receives the input D₀(J-1) and D₀(J) is compared with the output data D at time j.₁(J). That is, the first-stage comparison unit outputs D₀(I) (i = 1, 2, 3,... 2ⁿ-1,2ⁿ, ...), D₀(1) and D₀(2), D₀(2) and D₀(3), ..., D₀(2ⁿ-1) and D₀(2ⁿ),... Are compared, and the larger value is selected.₁(2), D₁(3), ..., D₁(2ⁿ), ... are output.
[0046]
Data D output from comparator 70-1 at time j₁(J) is input to the comparator 70-2 and the shift register 72-2 which constitute the second stage comparison unit. At time j when j ≧ 4, the shift register 72-2 stores the two data D that have been input earlier.₁(J-2), D₁(J-1). The shift register 72-2 stores the data D₁In synchronization with the input timing of (j), the data D stored first₁(J-2) is output. The comparator 70-2 outputs the data D output from the comparator 70-1.₁(J) and the delayed data D output from the shift register 72-2.₁(J-2) is input. The comparator 70-2 receives the input D₁(J) and D₁(J-2) and compare the larger one with the output data D at time j.₂(J). That is, the second-stage comparison unit outputs D₁(I) When (i = 2, 3, 4,...) Is input, D₁(2) and D₁(4), D₁(3) and D₁(5) For..., A magnitude comparison is performed, and the larger value is selected.₂(4), D₂(5), ... are output.
[0047]
As described above, the same processing as described for the first-stage comparison unit and the second-stage comparison unit is also performed in the third to sixth-stage comparison units. Generally speaking, regarding the k-th stage comparison unit (k = 2 to 6), time i ≧ 2^k-1A data string D output from the comparator 70- (k-1)_k-1(I) is input to each of the comparator 70-k and the shift register 72-k that constitute the k-th stage comparison unit. At a certain time j, the shift register 72-k stores 2^k-1Data D_k-1(Ξ) (ξ = j-2^k-1~ J-1) and the data D_k-1In synchronization with the input timing of (j), the data D stored first_k-1(J-2^k-1) Is output. For example, when the data input from the (k-1) th comparator to the kth comparator is specifically described as k = 4, at time j, the comparator 70-3 of the third comparator compares The data D is supplied to the comparator 70-4 of the fourth stage comparing section.₃(J) is input, and the data D stored first is output from the shift register 72-4.₃(J-2³) Is output (see FIG. 3). Thus, the comparator 70-k outputs the data D sequentially output from the comparator 70- (k-1)._k-1(J) and the delayed data D sequentially output from the shift register 72-k._k-1(J-2^k-1) Is entered. The comparator 70-k compares the magnitudes of the two input data, and determines which one is greater, the output data D at time j._k(J). That is, the k-th stage comparison unit_k-1(I) (i = 2^k-1, 2^k-1+1 and 2,^k-1+2, ...), D_k-1(2^k-1) And D_k-1(2^k), D_k-1(2^k-1+1) and D_k-1(2^k+1),... Are compared, and the larger value is selected._k(2^k), D_k(2^k+1), ... are output.
[0048]
With the above configuration, 64 Ds constituting a window in the first-stage comparison unit₀(Ξ) (ξ = j-2⁶+1 to j) are input, the sixth stage comparison unit, which is the last stage, outputs data D in the window.₀The maximum value of D is₆(J) is output. Further, the next data D is stored in the first stage comparing section.₀When (j + 1) is input, the window position is shifted by one data, and 64 Ds included in the window are shifted.₀(Ξ) (ξ = j-2⁶+2 to j + 1) is D₆Output as (j + 1). In this way, the windows are sequentially shifted in synchronization with the input of data to the maximum value calculation circuit 52, and the maximum value in each window is sequentially output from the maximum value calculation circuit 52.
[0049]
The signal processing circuits constituting the above-described maximum value operation circuit 52 and minimum value operation circuit 54 extract the maximum value or the minimum value of data within a one-dimensional window set in a one-dimensional data sequence. Was. However, a filter that extracts the maximum value or the minimum value of the data within the two-dimensional window can be configured using this signal processing circuit.
[0050]
For example, a configuration of a two-dimensional maximum value extraction filter configured using a maximum value calculation circuit which is a signal processing circuit of the present invention will be described. The example of the two-dimensional maximum value extraction filter described here uses a maximum value operation circuit composed of three stages (that is, n = 3) of comparison units and uses a maximum value operation circuit having a size of 8 × 8 in a two-dimensional window. Extract the maximum value. This two-dimensional maximum value extraction filter is based on the original two-dimensional data group D₀From (x, y) (x = 1, 2, 3,..., Y = 1, 2, 3,...), For example, first, a data group arranged in a row direction (a direction in which x changes) is read, Input to the arithmetic circuit. This process is executed for each row data group while changing the row position y. The obtained two-dimensional data group is represented by D₁It is stored in the memory as (x, y). D₁(X, y ') is the eight data D arranged in the y'th row.₀(Η, y ′) is the maximum value of (η = x to x + 7). Then D₁A data group arranged in the column direction (the direction in which y changes) from (x, y) is read and input to the maximum value calculation circuit. This processing is executed for each column data group while changing the column position x. The two-dimensional data group obtained by this is D₂It is stored in the memory as (x, y). D₂(X ', y) is D₁Eight data D arranged in the x'th column of (x, y)₁(X ', ξ) (ξ = y to y + 7). D generated in this way₂(X, y) is data D in an 8 × 8 window₀(Η, 次 元) (η = x to x + 7; ξ = y to y + 7) is output from the two-dimensional maximum value extraction filter as a two-dimensional data group including the maximum value. With the same principle, a two-dimensional minimum value extraction filter can also be configured. The two-dimensional maximum value extraction filter and the two-dimensional minimum value extraction filter are combined to form a two-dimensional morphological filter, and a closing process and an opening process can be performed on the ultrasonic image.
[0051]
【The invention's effect】
According to the signal processing circuit of the present invention, the maximum value or the minimum value can be extracted with a small circuit scale. Further, the size and cost of the ultrasonic diagnostic apparatus using the same can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of an ultrasonic diagnostic apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of a morphology filter unit.
FIG. 3 is a schematic block diagram of a signal processing circuit serving as a maximum value operation circuit or a minimum value operation circuit.
FIG. 4 is a block diagram illustrating a schematic configuration of a closing filter.
FIG. 5 is a schematic configuration diagram of a conventional first maximum value extraction circuit.
FIG. 6 is a schematic configuration diagram of a conventional second maximum value extraction circuit.
FIG. 7 is a block diagram of a maximum value storage circuit used in the maximum value extraction circuit of FIG. 6;
[Explanation of symbols]
20 ultrasonic probe, 22 transmitter, 24 receiver, 26 detector, 28 morphology filter unit, 30 memory unit, 32 three-dimensional image construction unit, 34 frame buffer, 36 display unit, 50 morphology filter, 52 maximum value Arithmetic circuit, 54 minimum value arithmetic circuit, 56 delay circuit, 58 subtraction circuit, 70 comparator, 72 shift register.

Claims (9)

An n-stage (n is an integer equal to or greater than 2) stage-by-stage comparison unit that operates in accordance with a predetermined selection condition;
The first-stage comparison unit compares the magnitude of the current input data with the immediately preceding input data, and outputs one of them as selected data,
The k-th stage comparison unit (k is an integer satisfying 2 ≦ k ≦ n) compares the selection data output from the (k−1) -th stage comparison unit with the selection data 2 ^k−1 before the selection data. Compare and output one of them as selection data,
The signal processing circuit according to claim 1, wherein the n-stage comparison unit extracts a maximum value or a minimum value of ²ⁿ pieces of data sequentially input to the first-stage comparison unit. The signal processing circuit according to claim 1,
The predetermined selection condition is a condition for selecting a larger one of two data to be compared,
The signal processing circuit according to claim 1, wherein the n-stage comparison units as a whole extract the maximum value of the ²ⁿ data sequentially input to the first-stage comparison unit. The signal processing circuit according to claim 1,
The predetermined selection condition is a condition for selecting a smaller one of two data to be compared,
The signal processing circuit according to claim 1, wherein the n-stage comparison unit extracts a minimum value from ²ⁿ data sequentially input to the first-stage comparison unit. In the signal processing circuit according to any one of claims 1 to 3,
The k-th comparing section includes:
Data holding means for holding 2 ^k-1 pieces of selected data output from the (k-1) -th stage comparing section and delay-outputting the selected data;
A comparator for comparing the magnitude of the selected data currently output from the (k-1) th comparing section with the ^2k-1 previous selected data delayed and output from the data holding means;
A signal processing circuit comprising: A signal processing circuit that sets a two-dimensional window for the two-dimensional data array, and extracts a maximum value or a minimum value according to a predetermined selection condition from a plurality of data in the two-dimensional window,
A first extraction unit for sequentially inputting a plurality of data constituting a data string for each data string in the window, extracting a maximum value or a minimum value from the plurality of data, and outputting the extracted data; ,
A second extraction unit for sequentially inputting a plurality of data extracted for each data string by the first extraction unit, extracting a maximum value or a minimum value from among them, and outputting the extracted data;
Has,
The first extraction unit includes n stages (n is an integer of 2 or more) of first comparison units connected in stages,
The first comparison unit of the first stage compares the magnitude of the current input data with the immediately preceding input data, and outputs one of them as selection data,
The k-th first comparison unit (k is an integer satisfying 2 ≦ k ≦ n) includes the selection data output from the (k−1) -th first comparison unit and 2 ^k−1 pieces of selection data Compare with the previous selection data, output either one as selection data,
The n-stage first comparison unit as a whole extracts a maximum value or a minimum value from a plurality of data sequentially input to the first stage first comparison unit, and outputs the extracted data. And
The second extraction unit includes m stages (m is an integer of 2 or more) of second comparison units connected in stages,
The second comparison unit in the first stage compares the magnitude of the current input data with the immediately preceding input data and outputs one of them as selection data,
The k-th second comparison unit (k is an integer satisfying 2 ≦ k ≦ m) includes the selection data output from the (k−1) -th second comparison unit and 2 ^k−1 pieces of selection data. Compare with the previous selection data, output either one as selection data,
The m-stage comparison unit as a whole extracts a maximum value or a minimum value from a plurality of data sequentially input to the first stage second comparison unit.
A signal processing circuit, characterized in that: A window is set for a received data sequence obtained by transmitting and receiving ultrasonic waves, and a maximum value or a minimum value is extracted from a plurality of received data in the window, and the extracted received data is output. An extraction unit,
An image generation unit that generates an ultrasonic image using reception data sequentially output from the extraction unit,
Has,
The extraction unit has n stages (n is an integer of 2 or more) of comparison units connected in a stepwise manner that operates according to a predetermined selection condition,
The first-stage comparing unit compares the magnitude of the current input received data with the immediately preceding input received data, and outputs one of them as selected received data,
The k-th stage comparing section (k is an integer satisfying 2 ≦ k ≦ n) selects the selected received data output from the (k−1) th stage comparing section and the selected received data 2 ^k−1 before the selected received data. And output either one as selected reception data,
The n-stage comparison unit as a whole extracts a maximum value or a minimum value from 2 ⁿ reception data sequentially input to the first-stage comparison unit,
An ultrasonic diagnostic apparatus, comprising: The ultrasonic diagnostic apparatus according to claim 6,
The predetermined selection condition is a condition for selecting a larger one of the two received data to be compared,
The ultrasonic diagnostic apparatus according to claim 1, wherein the n-stage comparison unit extracts the maximum value of ²ⁿ pieces of reception data sequentially input to the first-stage comparison unit. The ultrasonic diagnostic apparatus according to claim 6,
The predetermined selection condition is a condition for selecting a smaller one of two received data to be compared,
The ultrasonic diagnostic apparatus according to claim 1, wherein the n-stage comparison unit extracts a minimum value of ²ⁿ pieces of reception data sequentially input to the first-stage comparison unit. A first window is set for a reception data sequence obtained by transmission and reception of ultrasonic waves, and one of a maximum value or a minimum value is extracted from a plurality of reception data in the first window, and the extraction is performed. A first extraction unit that outputs the selected data,
A second window is set for the selected data string obtained from the first extraction unit, and the other of the maximum value or the minimum value is extracted from among the plurality of selection data in the second window, and the extracted data is extracted. A second extraction unit that outputs the selected reception data,
An image generation unit that generates an ultrasonic image using the selected reception data sequentially output from the second extraction unit,
Has,
The first extracting unit includes an n-stage (n is an integer of 2 or more) first comparing units that are connected in stages and operate according to a predetermined first selection condition;
The first comparing section of the first stage compares the magnitude of the current input received data with the immediately preceding input received data and outputs one of them as selected data,
The first comparison unit in the α-th stage (α is an integer satisfying 2 ≦ α ≦ n) is configured to output the selected data output from the first comparison unit in the (α−1) -th stage and 2 ^{α −} by comparing the magnitudes of the ^one previous selection data, and outputs one as selected data,
The second extraction unit includes m-staged (m is an integer equal to or greater than 2) second comparison units that are connected stepwise and operate according to a predetermined second selection condition;
The second comparison unit of the first stage compares the magnitude of the currently input selection data with the selection data input immediately before the selected data, and outputs one of them as selection data,
The second comparison unit (β is an integer satisfying 2 ≦ β ≦ m) in the β-th stage is configured to output the selected data output from the second comparison unit in the (β−1) -th stage and 2 ^{β −1} therefrom. Compare the size with the previous selection data, output either one as selection data,
The first selection condition is a condition for selecting either the larger one or the smaller one of the two data to be compared,
The second selection condition is a condition for selecting either the larger one or the smaller one of the two data to be compared;
An ultrasonic diagnostic apparatus characterized by the above-mentioned.

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