JP2004072683A - Image processing apparatus, print system, and control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus or the like in which performance is improved by simultaneously developing, compressing and transferring images. <P>SOLUTION: The image processing apparatus is provided with an image developing means for dividing an image into a plurality of areas and developing the image for each divided area, an image transfer means for transferring the developed image for each area for each area, an image compressing means for compressing image data transferred by the image transfer means, and an external transfer means for transferring the image data compressed by the image compressing means to the outside. While the image is developed for each area by the image developing means, the developed image is successively transferred to the image compressing means by the image transfer means, and the image compressing means compresses the successively transferred images while coupling a series of a plurality of divided areas. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing apparatus and the like that generates compressed image data and transfers the generated image data to a printer or the like.
[0002]
[Prior art]
In recent years, in order to share the resources of various electronic devices used in offices and the like, these devices have been connected via a network. For example, a conventional printer is generally a local printer connected to one device, but is increasingly used as a network printer shared by devices in a network.
[0003]
In recent years, a multifunction printer that incorporates various functions into one apparatus has been developed, and a printer controller having an image processing function has been incorporated in a copier, and a multifunction printer having both functions of a copier and a printer has been installed. Machine is on the market. Facsimile functions and the like have been further added to such multifunction peripherals, and multifunction has been advanced.
[0004]
Since it is assumed that such a multifunction peripheral is used while being connected to a network, a configuration capable of responding to various user needs from various users is required. In order to respond to this, for example, there has been proposed a multifunction peripheral in which internal functional units are connected by a shared bus, and expandability is provided to meet various user needs.
In order to exchange data efficiently without each unit occupying the shared bus, a device for reducing the amount of data by, for example, data compression or the like has been devised.
[0005]
In such a system, when transferring data, particularly image data, etc., the transfer is performed by DMA without directly involving the CPU. In many cases, the DMA transfer detects the amount of data to be transferred from a transfer source and performs control processing such as securing a memory buffer at a transfer destination and generating a DMA end timing.
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional system, when data is compressed and transferred, the compression ratio is not constant due to the compression method or the data configuration. Data amount may change. For example, in the printer controller unit, even if the data amount of each page is the same, the data amount of each page changes after compression depending on the image to be created even if the data amount of each page is the same. .
[0007]
As described above, since the transfer data amount is unknown unless the compression is completed, when performing the transfer by the DMA, after performing the control processing such as detecting the data amount after the completion of the compression and securing the memory buffer of the transfer destination, , DMA is activated to perform the transfer.
[0008]
In a printer controller mounted inside such a multifunction device, when transferring a developed image, after decompressing one page of image, compression is continuously performed, and after completion of compression, the data amount is detected and DMA is started. Thus, since the compressed data for one page is transferred and this operation is performed for each page, the system has a poor performance.
[0009]
SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described conventional problems, and has as its object to provide an image processing apparatus and the like that can perform image expansion, compression, and transfer at the same time and have improved performance.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, an image processing apparatus of the present invention divides an image into a plurality of regions, and develops an image for each of the divided regions. Image transfer means for transferring the image data transferred by the image transfer means, and an external transfer means for transferring the image data compressed by the image compression means to the outside, While the image is expanded for each region by the image expanding unit, the expanded image is sequentially transferred to the image compressing unit by the image transfer unit, and the image compressing unit is configured to sequentially transfer a plurality of divided regions into a plurality of regions. The image is compressed while being combined.
[0011]
A print system according to the present invention includes an image processing apparatus that generates and transfers compressed image data, and a print output processing apparatus that performs print output processing based on the compressed image data transferred from the image processing apparatus. In the image processing apparatus, the image processing device divides an image into a plurality of regions, and develops an image for each of the divided regions, and an image transfer unit that transfers a developed image for each of the regions to each region An image compression unit for compressing the image data transferred by the image transfer unit; and a print transfer unit for transferring the compressed image data compressed by the image compression unit to the print output processing device, While the image is expanded for each region by the means, the developed image is sequentially transferred to the image compression means by the image transfer means, and the image compression means An image of the divided series of multiple regions are sequentially transferred, and wherein the compressing while bonding.
[0012]
In the control method of the image processing apparatus of the present invention, an image is divided into a plurality of areas, and while the image is developed for each of the divided areas, an image transfer step of sequentially transferring the developed image is performed. An image compression step of compressing a series of images in a plurality of regions that are sequentially transferred while combining the images, and an external transfer step of transferring the image data compressed in the image compression step to the outside. I do.
[0013]
A control program according to the present invention is a computer-readable control program for executing a control method of an image processing apparatus that generates and transfers compressed image data, and divides an image into a plurality of areas, Image transfer step of sequentially transferring the developed image while expanding the image for each of the divided areas, and image compression for compressing while combining a series of images of a plurality of areas sequentially transferred in the image transfer step. And an external transfer step of transferring the image data compressed in the image compression step to the outside.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0015]
[Overall configuration of MFP]
FIG. 1 is a schematic block diagram illustrating an overall configuration of a multifunction peripheral according to an embodiment of the present invention.
[0016]
The multifunction peripheral of this embodiment has functions of a scanner, a printer, and a facsimile. In FIG. 1, reference numeral 101 denotes a PDL unit that develops a raster image in an image memory based on a file described in a page description language.
[0017]
The PDL unit 101 functions as an image processing unit, and is configured to download a control program in a page description language. By downloading a control program of a desired page description language to the PDL unit 101, a plurality of page description languages can be handled.
[0018]
These control programs are stored in the hard disk unit 103 connected to the system bus 105, are appropriately selected by the CPU 115 in the master control block 106, and are transferred to the PDL unit 101 by the DMA controller in the PDL unit 101. .
[0019]
A network I / F 102 transmits and receives various commands and a page description language file to be printed to and from a host computer (not shown) via a network 107. A FAX unit 104 transmits and receives image data to and from another facsimile or the like connected to the public line 109 via a TEL cable 108. A master control block 106 connects and controls each of the units 101 to 104 with the scanner unit 110 and the printer unit 111.
[0020]
Each of the units 101 to 104 is connected by a system bus 105. Various units other than the above-described units can be connected to the system bus 105, and a multifunction peripheral having various functions can be configured according to user needs.
[0021]
Although shown separately in the figure, together with the system bus 105, CLK112, REQ-P, GNT-P, REQ-N, GNT-N, REQ-HD, GNT-HD, REQ-F, GNT-F is connected to the corresponding unit.
[0022]
The CLK 112 is generated by the clock generator 117 in the master control block 106, and is supplied to the PDL unit 101, the network I / F 102, the bus arbiter 113, the hard disk unit 103, the FAX unit 104, and the scanner / printer I / F 118.
[0023]
REQ-P, REQ-N, REQ-HD, and REQ-F are bus exclusive request signals output from the PDL unit 101, the network I / F 102, the hard disk unit 103, and the FAX unit 104, respectively. Is input to the bus arbiter 113 in the terminal.
[0024]
In the bus arbiter 113 to which the bus exclusive request signal is input, the bus exclusive permission signals GNT-P, GNT-N and GNT- are sequentially and efficiently stored so that the units 101 to 104 do not monopolize the system bus 105 for a predetermined period or more. By transmitting the HD and the GNT-F to the PDL unit 101, the network I / F 102, the hard disk unit 103, and the FAX unit 104, use of the system bus 105 is permitted. Generation of these bus occupation permission signals GNT-P, GNT-N, GNT-HD, and GNT-F will be described later.
[0025]
Reference numerals 110 and 111 denote a scanner unit and a printer unit, respectively, which are connected to a scanner / printer I / F 118 in the master control block 106 via a video I / F 119. Further, the scanner / printer I / F 118 and the system bus 105 are connected to the PDL unit 101, the network I / F 102, the hard disk unit 103, and the facsimile unit 104, and scan images read by the scanner unit 110 and record by the printer unit 111. A print image to be transmitted is transmitted and received.
[0026]
In the video I / F 119, in addition to a signal for transferring a read image or an image to be printed, a SLEEP signal 124 to be described later, and a command (not shown) for transmitting / receiving a command to / from a scanner / printer I / F 118 are transmitted and received. Command communication signal for performing the command.
[0027]
In the master control block 106, a local bus 114 connects the CPU 115 with the bus arbiter 113, the scanner / printer I / F 118, and the operation unit 120. The CPU 115 controls each unit in the master control block 106 based on a control program stored in the ROM / RAM 121.
[0028]
For example, an outline of the operation when a scanner command is issued will be described. When a scanner command is issued from a host computer (not shown) connected to the network 107, the network I / F 102 receives the command and issues a bus occupation request REQ-N to the bus arbiter 113 to request bus occupation. As described above, the bus arbiter 113 efficiently and sequentially issues the bus occupation permission signals GNT-N so as not to monopolize the bus.
[0029]
The network I / F 102 secures the bus by receiving the bus occupation permission signal GNT-N, and transfers the command received from the host computer to the scanner / printer I / F 118.
[0030]
When receiving a notification from the scanner / printer I / F 118 by, for example, an interrupt signal (not shown) in the local bus 114, the CPU 115 interprets the received command via the local bus 114, and further interprets the received command. The CPU 115 issues a command to the scanner unit 110 via a command communication signal in the video I / F 119 to activate the scanner. At the same time, it activates the DMA control circuit 122 in the scanner / printer I / F 118 to transfer the scanned image.
[0031]
The scanner unit 110 transfers the scanned image to the scanner / printer I / F 118 via the video I / F 119 according to the received command. The DMA control circuit 122 in the scanner / printer I / F 118 that has received the scanned image outputs the bus exclusive request REQ-M to the bus arbiter 113. The bus arbiter 113 does not monopolize the bus as described above. The scanner image is DMA-transferred to the network I / F 102 by efficiently and sequentially issuing the bus occupation permission signal GNT-M to open the bus between the scanner / printer I / F 118 and the network I / F 102, Further, the scanned image can be transferred to the host computer via the network 107.
[0032]
[DMA transfer procedure]
FIG. 2A is a timing chart showing the state of the DMA at this time.
[0033]
All signals are running in synchronization with CLK112. It is also included in the system bus 105. The DMA control circuit 122 outputs REQ-M at the timing of (1) when the DMA is activated and the image data is transferred from the scanner unit 110. After arbitrating the bus occupation request from each unit, the bus arbiter 113 that has received the REQ-M issues a bus occupation permission signal GNT-M at the timing of (2). The timing from (1) to (2) may fluctuate depending on the arbitration of bus occupation with other units.
[0034]
Upon receiving the bus occupation permission signal GNT-M, the DMA control circuit 122 outputs the bus occupation signal FRAMEX at timing {circle around (3)}, and notifies other units that they are occupied. At the same time, a command and an address are output. The command is a command for notifying the transfer destination unit of the read mode / write mode. In this case, since the transfer is from the scanner / printer I / F 118 to the network I / F unit 102, a write mode is notified.
[0035]
At the timing of {circle around (4)}, IRDYX notifying that the data to be transferred is ready in the DMA control circuit 122 is issued. At the timing of (5), the network I / F unit 102 detects that the transfer to itself starts from the address output at the timing of (3), and outputs the detection signal DEVSELX. At the same time, it issues a TRDYX signal notifying that preparation for receiving data is completed.
[0036]
The DMA control circuit 122 that has received DEVSELX and TRDYX sequentially outputs transfer data in synchronization with CLK112. At the time of DMA transfer, burst transfer is performed in units of 32 words per word in units of 8 words, that is, in units of 32 bytes, using D1 to D8 as transfer units as shown in FIG. At timing (6), the eight-word transfer ends.
[0037]
When the next data is transferred again from the scanner unit 110, the bus exclusive request REQ-M (timing {circle around (7)}) is output to the bus arbiter 113 again, and the DMA transfer is performed by repeating these.
[0038]
To end the DMA, the amount of data to be transferred is set in advance, and when the amount reaches the value, the DMA control circuit 122 interrupts the CPU 115, notifies the end of the transfer, and terminates the DMA itself.
[0039]
The DMA transfer procedure described above applies to all units.
[0040]
In the above description, means for transferring an image scanned by the scanner unit 110 to the network I / F 102 without performing compression processing has been described. However, in response to a command from the host computer, the scan image is compressed by the compression / expansion circuit 123. The DMA transfer can be performed after the compressed data is secured in the RAM area 121 secured as a buffer in advance.
[0041]
As described above, the DMA control circuit 122 is provided in the scanner / printer I / F 118, and the CPU 115 can control the start and stop of the local bus 114 via the local bus 114. Upon activation of the DMA control circuit 122, the control program stored in the hard disk unit 103, the communication data temporarily stored in the ROM / RAM 121, various parameters, or the compressed image data are transferred to each unit connected to the system bus 105. High-speed transmission, and high-speed reception of communication data and various parameters from each unit. Of course, the CPU 110 can directly access each unit without using the DMA control circuit 122.
[0042]
In the present embodiment, since the bus arbiter 113 and the scanner / printer I / F 118 are in the same block, the bus exclusive request signal REQ-M and the bus exclusive permission signal GNT-M are separate from the system bus 105. However, they may be connected together with the system bus 105 according to the configuration.
[0043]
The scanner / printer units 110 and 111 can independently operate as a copying machine by using a copy button of the operation unit 120.
[0044]
[Configuration of Bus Arbiter 113]
FIG. 3 is an internal block diagram showing the configuration of the bus arbiter 113.
[0045]
Reference numeral 301 denotes a bus monitoring circuit that monitors the usage status of the system bus 105. For example, when detecting that a certain device uses the system bus 105 (referred to as a bus busy), the timer reset signal 305 is enabled and the timer 303 is reset.
[0046]
When it is detected that no device uses the system bus 105 (referred to as a bus idle), the timer reset signal 305 is disabled, and the timer 303 starts operating.
[0047]
After that, when a certain time elapses, that is, when no device uses the system bus 105, that is, when the bus idle elapses to some extent, a Hit signal 307 notifies the SLEEP circuit 304 of the CLK disable, and furthermore, If a certain amount of bus idle has elapsed while the device is not using the system bus 105, the SLEEP circuit 304 is notified of the SLEEP by the Hit signal 307.
[0048]
Although not shown, the timer is connected to the local bus 114, and the timing of disabling CLK and the timing of SLEEP can be set by the CPU 115 in a programmable manner.
[0049]
When receiving the CLK disable notification by the Hit signal 307, the SLEEP circuit 304 disables the signal CLKEN116 and notifies the clock generator 117. When the signal CLKEN116 is disabled, the clock generator 117 stops supplying the clock signal CLK112 and keeps the logic level at High. This state is called a standby state. Each unit is notified that the master control block 106 is in the standby state by the logic level High of CLK112.
[0050]
In this manner, when the bus idle of the system bus 105 continues, the clock is stopped in a high state to be in a standby state, thereby suppressing power consumption. Further, when time elapses in the state of the bus idle of the system bus 105 and the SLEEP notification is received by the Hit signal 307, the signal SLEEP 124 is enabled, and the CPU 115, the scanner unit 110, and the printer unit 111 are notified of the SLEEP.
[0051]
The CPU 110 notified of the SLEEP causes all the blocks except the bus arbiter 113 in the master control block 106 to execute a procedure for turning off the power (referred to as a shutdown process). For the clock generator 117, the logic level of the CLK 112 is set to Low. Similarly, the scanner unit 110 and the printer unit 111 also execute a shutdown process via the video I / F, and the power of all the blocks except the bus arbiter 113 and the CPU 115 in the master control block 106 is turned off. . Thereafter, the CPU 115 also shifts to the low power consumption mode. This state is called a sleep state. The logic level Low of CLK 112 notifies each unit that the master control block 106 is in the sleep state.
[0052]
In this way, when the bus idle of the system bus 114 continues further, the clock is stopped in a low state, and a sleep state is set, so that power consumption is suppressed.
[0053]
The release of the standby state and the sleep state is that any one of the exclusive request signals REQ-P, REQ-N, REQ-HD, REQ-F, and REQ-M of the system bus 105 is issued to the arbitration circuit 302. Done by
[0054]
In this case, the release signal 306 is sent to the SLEEP circuit 304. In the SLEEP circuit 304, in the standby state, the CLKEN 116 is enabled so that the clock can be supplied immediately from the clock generator 117. In the sleep state, CLKEN 116 is enabled and SLEEP 124 is disabled.
[0055]
When notified that the SLEEP 124 is disabled, the CPU 115 returns from the sleep mode to the normal mode, starts supplying power to each block, and performs an initialization operation. Similarly, the scanner unit 110 and the printer unit 111 are supplied with power from the notification of disabling the SLEEP 124 and are initialized.
[0056]
When detecting that all the initializations have been completed, the CPU 110 performs a program to supply a clock to the clock generator 117 (hereinafter referred to as a startup program).
[0057]
[Configuration of PDL unit 101]
FIG. 4 is a schematic block diagram showing the configuration of the PDL unit 101.
[0058]
The PDL unit 101 has a function of receiving a page description language and developing an image based on the page description language.
[0059]
The CPU 601 controls the entire PDL unit 101 via the local bus 602, and the RAM 603 stores a control program executed by the CPU 601. The control program stored here can support various page description languages. For example, if a PS control program is stored, the PDL unit 101 is used for the PS. If a LIPS control program is stored, the PDL unit 101 is used for the LIPS.
[0060]
Initial settings of these control programs are determined when the entire system is started up, and the program codes determined by the settings are downloaded. Of course, PS and LIPS can be selected according to user needs.
[0061]
Further, information on the resources of the PDL unit 101, for example, the performance of a mounted CPU, the capacity of the memory 603, and the like are obtained from configuration information and the like, and a control program to be downloaded is selected based on the information. Is also good.
[0062]
For example, in the PDL unit 101, when the performance of the CPU 601 causes the PS to have a higher ability to develop images than the LIPS, or when a file transmitted from a user connected to the network 107 uses the PS as a page description language. In the case where there is a large number of programs, the control program of the PS having the higher ability is downloaded to the PDL unit 101, so that the user who uses the PS more frequently can be made more convenient.
[0063]
Further, as described above, even if the PS program code has been downloaded, for example, if there is a user who wants to print a document file described in LIPS, the PDL unit 101 receives a command from the user who wants to print the document. , A necessary control program can be downloaded.
[0064]
These program codes are stored in the hard disk unit 103 in advance, and start the DMA of the hard disk unit 103 based on the control of the CPU 115 in the master control block 106, and output a REQ-HD, receive a GNT-HD, etc. The bus is acquired from the above operation, and is transferred to the RAM 603 via the bus I / F 607 and the local bus 602 via the system bus 105.
[0065]
The work RAM 605 stores various types of parameter information and also functions as a work area for the CPU 601. The ASIC 604 has a function of expanding a raster image on the image memory 606 based on a file described in a page description language, and a function of transferring the expanded image to the image compression circuit 612 by DMA via the local bus 602. ing.
[0066]
Reference numeral 607 denotes a bus I / F, which interfaces the system bus 105 and the local bus 602, and includes a DMA control circuit 609 therein, which directly includes a memory work RAM 605, an image memory 606, or a hard disk unit without passing through the CPU 601. Data can be transmitted and received from the system 103 via the system bus 105. Further, an image compression circuit 612 for transferring the developed image while compressing it is built in, and the compressed image can be transferred to the scanner / printer I / F 118 by the DMA control circuit 609.
[0067]
The control signal RES 611 is output from the bus I / F 607 in response to a command from the CPU 115 in the master control block 106. When the reset control signal RES611 is input to the reset terminal of the CPU 601, the CPU 601 is reset. While the reset control signal RES511 is in the enable state, the CPU 601 is in the hold state, and the signal connected to the local bus 602 is in the high impedance state. It becomes.
[0068]
When downloading the control program, the CPU 115 enables the reset control signal RES 611 by a command, activates the DMA of the hard disk unit 103, and downloads the necessary control program to the RAM 603 via the system bus 105 and the local bus 602. Then, after the download, the reset control signal RES611 is disabled from enabled by a command, the reset of the CPU 601 is released, and the CPU 601 is started.
[0069]
Reference numeral 608 denotes a CLK detection circuit which can detect whether the CLK 112 is supplied and whether the logic level is High or Low.
[0070]
Next, the operation of the PDL unit 101 will be described.
[0071]
The document file described in the page description language received by the network I / F 102 is transferred via the system bus 105 and the bus I / F 607 and temporarily stored in the work RAM 605 as described above.
[0072]
The CPU 601 refers to the page description language data temporarily stored in the work RAM 605, converts the data into an intermediate language that can be used by the ASIC 604, and sequentially stores the intermediate language in the work RAM 605 again.
[0073]
When the conversion processing into the intermediate language for one page is completed, the CPU 601 sends an image development start command to the ASIC 604, and the ASIC 604 refers to the intermediate language stored in the work RAM 605 to the image memory 606 at a high speed. Develop image images.
[0074]
In the present embodiment, the rasterization image development processing (rendering processing) and transfer processing by the ASIC 604 are performed in units of bands to perform high-speed rendering processing in a small image memory and to transfer images while compressing. That makes it possible.
[0075]
Further, by compressing the image data, the bus occupancy of the system bus 105 during data transfer from the PDL unit 101 is reduced, thereby improving the performance of the entire system.
[0076]
[Operations Characterizing the Present Embodiment]
FIG. 5 is a timing processing diagram illustrating rendering, transfer, and compression processing in the PDL unit 101, which is a feature of the present embodiment. The following control method can be realized by storing a program for performing the operation according to the timing processing diagram of FIG. 5 in the RAM 603 in the PDL unit 101 and operating the program.
[0077]
As shown in the drawing, the PDL unit 101 divides one page of image data into five regions, and performs rendering processing while alternately using the divided regions α and β of the image memory 606. The image data is transferred to the image compression circuit 612 at the same time. Hereinafter, a specific description will be given.
[0078]
Upon receiving the image development start command from the CPU 601, the ASIC 604 responds to the command by referring to the intermediate language data stored in the work RAM 605 and processing the raster image image to the α-side area of the image memory 606 at high speed. (Rendering process).
[0079]
Further, the CPU 601 simultaneously performs a conversion process to the next page of intermediate language data, and sequentially stores the converted data in the work RAM 605. At this time, although not shown, an arbitration circuit (arbitration circuit) for acquiring the local bus 602 built in the ASIC 604 so that the CPU 601 and the ASIC 604 do not simultaneously access the work RAM 605 via the local bus 602. Circuit).
[0080]
When the rendering of the band 1 in the α area of the image memory 606 ends, the ASIC 604 generates an interrupt signal (INT) 610 to the CPU 601 to notify the occurrence of the event. When detecting the interruption, the CPU 601 accesses an event register (not shown) in the ASIC 604 and detects the contents of the event. In the present embodiment, the types of events of the interrupt signal (INT) 610 from the ASIC 604 include the end of rendering and the end of DMA which is performing image transfer to the image compression circuit 612.
[0081]
When the CPU 601 detects the end of the rendering of the band 1, the CPU 601 activates the DMA control circuit 613 in the ASIC 604 and instructs the band 1, that is, the transfer of the rendering image expanded in the α area of the image memory 606 to the image compression circuit 612. I do. At the same time, the image compression circuit 612 clears the parameters for compression and the learning memory for compression, and activates the compression circuit 612.
[0082]
Further, the CPU 601 causes the bus I / F 607 to issue the exclusive request signal REQ-P for the system bus 105. At the same time, the state of CLK112 is detected by the CLK detection circuit 608. At this time, for example, when it is detected that the logic level of the CLK 112 is High, it is determined that the master control block 106, the scanner unit 110, and the printer unit 111 are in a standby state. In this case, the CPU 601 sets a transfer command, a transfer destination address, and a transfer byte number to the DMA control circuit 609 in the bus I / F 607, and transfers the compressed image to the scanner / printer I / F 118 via the system bus 105. Prepare to transfer to.
[0083]
At this time, since the exclusive request signal REQ-P has already been issued, the supply of CLK112 from the bus arbiter 113 and the supply of CLK112 from the clock generator 117 are started immediately. When the DMA control circuit 609 receives the bus occupation permission signal GNT-P from the bus arbiter 113, it starts transferring the compressed data to the scanner / printer I / F 118.
[0084]
Next, the CPU 601 instructs the ASIC 604 to render the band 2 on the β area of the image memory 606, and waits for an event by an interrupt signal. For example, the rendering end event to the β area corresponding to band 2 is detected first, and if the transfer end event of band 1 is not detected yet, the α area of the image memory 606 is still being transferred. Wait for the transfer end event to occur. When the transfer end event of the α area of the band 1 occurs, the CPU 601 instructs the ASIC 604 to render the band 3 in the α area of the image memory 606, and simultaneously activates the DMA control circuit 613 to activate the β area corresponding to the band 2. Is transferred to the image compression circuit 612. Again, it waits for an event by the interrupt signal.
[0085]
The process proceeds, for example, first, the DMA transfer end event of the rendering image of the β area corresponding to band 2 is detected, and if the rendering end event of the α area corresponding to band 3 is not detected, α in the image memory 606 is detected. Since the region is still being rendered, wait for the band 3 rendering end event. When the rendering end event of the α region corresponding to band 3 occurs, the CPU 601 activates the DMA control circuit 613 in the ASIC 604 to transfer the rendered image of the α region corresponding to band 3 to the image compression circuit 612. And at the same time, rendering to the β region corresponding to band 4.
[0086]
As described above, rendering and DMA transfer are sequentially and repeatedly performed on the α area and the β area of the image memory 606, and by detecting the transfer end event of the rendering image of the α area corresponding to the band 5, rendering for one page is performed. The transfer of the image to the compression circuit 612 is completed. As will be described later, the end of compression of one page is detected by an event interrupt (INT) 614.
[0087]
In this way, the compressed data is transferred to the scanner / printer I / F 118 while rendering and compression are performed simultaneously, and temporarily stored in the memory 121 of the master control block 106.
[0088]
At this time, the compression is performed in units of one page, not in each band obtained by dividing one page into five. This is because, in the case of band units, it is necessary to set parameters for each band, clear the learning memory used for compression, etc., and after compression, a large number of small-sized compressed image data files are generated and managed. Is complicated.
[0089]
The data amount of the compressed data, that is, the data amount transferred to the memory 121 of the master control block 106 is unknown because it varies depending on the image data. However, it is necessary to reserve a buffer area in the memory 121, and the CPU 115 in the master control block 106 reserves an area of a predetermined value, for example, 256 Kbytes. That is, the transfer amount of the compressed data by the DMA is set to 256 Kbytes, and the DMA is stopped after the transfer of the 256 Kbytes. When the DMA stops, an event interrupt (INT) 614 notifies the CPU 601 by an interrupt.
[0090]
When receiving the event interrupt (INT) 614, the CPU 601 detects an event by referring to an event register in the bus I / F 607 (not shown). As described above, the types of events include the stop of DMA, the end of image data compression, and the interrupt event for communication with the CPU 115 in the master control block 106.
[0091]
For example, after referring to the event, if the DMA is stopped, the CPU 601 instructs the CPU 115 in the master control block 106 to secure 256 Kbytes again, sets the transfer byte number 256 Kbytes to the DMA control circuit 609, and starts up. multiply. Since the compression operation has not been completed, the transfer of the compressed data is resumed by DMA activation.
[0092]
When receiving the interrupt of the event interrupt (INT) 614 again, the CPU 601 detects an event by referring to an event register in the bus I / F 607 (not shown). For example, when the event is the end of the image data compression, the DMA control circuit 609 is stopped, and the communication with the CPU 115 in the master control block 106 notifies the end of the image data compression.
[0093]
As described with reference to FIG. 2A, the transfer unit of the DMA occupying the system bus 105 is a unit of 8 words (32 bytes), and the transfer is performed most efficiently by repeating this unit. However, since the amount of compressed data varies depending on the image, the transfer cannot always be completed in units of 8 words (32 bytes). When the last transfer unit is less than eight words, the DMA control circuit 609 creates data in units of eight words by repeating the end code of the compressed data, for example, and contrives to efficiently transfer data to the end. ing. FIG. 2B shows this state. Since the data below the end code is ignored as the compressed data, the data need not always be the end code.
[0094]
As shown in FIG. 5, for example, when the data amount after compression is 256 Kbytes for the first time and 200 Kbytes for the second time as a result of two DMAs, the total amount is 456 Kbytes, and the page image is a monochrome page of 600 dpi A4 size black and white. In this case, the compression rate is about 11% because the size is 4 Mbytes. In FIG. 5, when the vertical axis is the time axis, rendering, compression, and transfer are performed simultaneously, so that the performance can be made advantageous.
[0095]
As described above, image compression can be performed efficiently by processing rendering by band and compressing by page.
[0096]
The compressed data stored in the memory 121 of the master control block 106 is expanded to the original image by the compression / expansion circuit 123 when printing, and the image is obtained by the printer unit 111. Also, for example, when temporarily stored in the hard disk unit 103, it is transferred and stored as it is.
[0097]
[Operation at system startup]
Hereinafter, the operation at the time of starting the system and the operation when selecting a control file to be downloaded will be described with reference to the flowchart of FIG.
[0098]
In step S801, a pre-input system initial setting is loaded. These are stored, for example, in the hard disk unit 103 or the like. Here, it is assumed that the initial setting is such that the LIPS control program is loaded into the PDL unit 101. These can be appropriately changed by the user.
[0099]
In step S802, the RES 611 in the PDL unit 101 is enabled, and the CPU 601 is set in a hold state. In step S803, the DMA control circuit 609 is activated to start downloading a control program necessary for the PDL unit 101 stored in the hard disk unit 103. Here, the LIPS control program is downloaded to the PDL unit 101, for example.
[0100]
If the end of the download is detected in step S804, the RES 611 in the PDL unit 101 is disabled in step S805. As a result, the hold state of the CPU 601 of the PDL unit 101 is released, and the CPU 601 is activated according to the program.
[0101]
In step S806, information regarding resources, for example, the capacity of a mounted CPU, the capacity of a memory, and the like are detected as information regarding the performance of the PDL unit 101 by communication performed first after activation.
[0102]
In step S807, the information about the acquired performance of the PDL unit 101 is notified to the network I / F. The network I / F 102 notifies this information to a host computer (not shown) connected to the network 107. The host computer can efficiently print by selecting a system connected to the network 107 based on the information. Commands are issued as needed.
[0103]
In step S808, the CPU 115 in the master control block 106 waits for a command from the network I / F 102, and in step S809, performs processing on the received command, for example, processing such as downloading a new control program.
[0104]
[Configuration of FAX Unit 104]
FIG. 7 is a schematic block diagram illustrating the configuration of the FAX unit 104.
[0105]
A CPU 404 controls the entire FAX unit 104 via a local bus 402. The FAX circuit 403 controls transmission and reception via the public line 109 and the TEL cable 108, performs direct drawing on the memory 405 from the received data by the memory control bus 410, or sends the data to the memory 405 and stores the data. This is a circuit for compressing a scanned image and transmitting the compressed image to the public line 109.
[0106]
The scan image stored in the memory 405 is transmitted from the scanner unit 110 to the memory 405 via the scanner / printer I / F 118 and the system bus 105, and is transmitted to and stored in the memory 405 via the bus I / F 408 and the local bus 402. You. Reference numeral 401 denotes a hard disk, which is used to temporarily store an image developed and drawn in the memory 405.
[0107]
External operations such as registration of a telephone number of a transmission destination and start of operation by a start button can be performed by the operation unit 120 connected to the master control block 106. The data is interpreted by the CPU 115 via the local bus 114, and is transferred to the FAX unit 104 via the scanner / printer I / F 118 and the system bus 105 by the DMA control circuit 122 or the CPU 115.
[0108]
A bus I / F 408 interfaces the system bus 105 and the local bus 402. A DMA control circuit 407 is provided inside the bus I / F, and transfers data from the memory 405 to the system bus 105 directly without using the CPU 404. Or receive.
[0109]
Reference numeral 406 denotes a CLK detection circuit, which can detect whether or not the CLK 112 is supplied and can detect whether the logic level is High or Low. That is, the master control block 106 can detect whether it is in the sleep state or the standby state from the state of the CLK 112.
[0110]
Next, the operation of the facsimile unit 104 will be described below, taking as an example a case where a facsimile document is received and a print output is obtained by the scanner / printer unit 113.
[0111]
The FAX circuit 403 receives data via the public line 109 and the TEL cable 108. In many cases, the data is compressed data. Therefore, the received data is directly expanded from the memory control bus 410 to the memory 405 while being expanded. Is drawn. At the same time, the CPU 404 detects the reception by the interrupt signal from the FAX circuit 403 in the local bus 402, issues the exclusive request signal REQ-F of the system bus 105 to the bus I / F 408, Is detected.
[0112]
For example, when it is detected that the logic level of the CLK 112 is Low, it is known that the master control block 106, the scanner unit 110, and the printer unit 111 are in the SLEEP state. At this time, since the exclusive request signal REQ-F has already been issued, the above-described startup program is operating in the master control block 106, the scanner unit 110, and the printer unit 111.
[0113]
Since the start-up program initializes each block, it takes time until the start-up program ends, and the image developed in the memory 405 is in a transfer waiting state until the CLK 112 is supplied. Will cause reception failure. To prevent this, when the CLK detection circuit 406 detects that the logic level of CLK 112 is Low, the CPU 404 saves the received and expanded image data stored in the memory 405 to the temporary hard disk 401 and temporarily saves the next image. To prevent the reception of the message.
[0114]
When the CLK detection circuit 406 detects that the CLK 112 is being supplied, the CPU 404 sends a transfer command to the DMA control circuit 407 in the bus I / F 408, and transmits the bus exclusive use permission signal GNT-F from the bus arbiter 113. Wait for issuance.
[0115]
Upon receiving the bus exclusive use permission signal GNT-F, the DMA control circuit 407 transfers the received image temporarily stored in the hard disk 401 to the scanner / printer I / F 118 via the local bus 402 and the system bus 105. . Thus, an image is obtained from the printer unit 111.
[0116]
As described above, the SLEEP state of the master control block 106, the scanner unit 110, and the printer unit 111 is detected from the state of the CLK 112, and if the state is the SLEEP state, the received image is saved by the internal processing of the FAX unit 104. In order to improve the efficiency of the processing, it is possible to receive the image.
[0117]
[Configuration of Network I / F 102]
FIG. 8 is a schematic block diagram illustrating the configuration of the network I / F 102.
[0118]
A CPU 501 controls the entire network I / F 102 via a local bus 507. A network circuit 502 automatically controls a protocol of the network 107. A memory 503 temporarily stores a PDL file and image data transferred from a host computer (not shown) connected to the network 107 via the network circuit 502.
[0119]
A bus I / F 504 interfaces the system bus 105 and the local bus 507. A DMA control circuit 505 is provided inside the bus I / F, and data is directly transmitted from the memory 503 to the system bus 105 without passing through the CPU 501. Can send and receive. Reference numeral 506 denotes a CLK detection circuit, which can detect whether the CLK 112 is supplied and can detect whether the logic level is High or Low.
[0120]
Next, the operation of the network I / F 102 will be described by taking as an example a case where a print output is obtained in accordance with data transmitted from an external host computer connected to the network 107.
[0121]
The host computer (not shown) converts the edited document into a file described in a page description language, and transfers the file to the network I / F 102 via the network 107. The transmitted image file described in the page description language is received by the network circuit 502, and is temporarily stored in the memory 503 via the CPU 501.
[0122]
Upon receiving the file, the CPU 501 causes the bus I / F 504 to issue an exclusive request signal REQ-N for the system bus 105. At the same time, CLK 112 is detected by the CLK detection circuit 506.
[0123]
For example, when it is detected that the logic level of the CLK 112 is High, it is determined that the master control block 106, the scanner unit 110, the printer unit 111, and the standby state are set.
[0124]
The CPU 501 sends a transfer command to the DMA control circuit 505 in the bus I / F 504, and transfers the image file described in the page description language temporarily stored in the memory 503 to, for example, a PDL via the system bus 105. Prepare to transfer to unit 101. At this time, since the exclusive request signal REQ-F has already been issued, the clock generator 117 starts supplying the CLK 112 immediately after receiving the CLKEN 116 from the bus arbiter 113. When receiving the bus occupation permission signal GNT-N from the bus arbiter 113, the DMA control circuit 505 starts the transfer. The image developed by the PDL unit 101 is transferred to the printer unit 111 via the scanner / printer I / F 118 and recorded.
[0125]
As described above, the states of the master control block 106, the scanner unit 110, and the printer unit 111 are detected from the state of the CLK 112, and if the state is the standby state, the file transfer using the system bus 105 is sequentially advanced. We are trying to improve efficiency.
[0126]
The present invention is not limited to the device of the above-described embodiment, and may be applied to a system including a plurality of devices or an apparatus including one device. A storage medium storing software program codes for realizing the functions of the above-described embodiments is supplied to a system or apparatus, and a computer (or CPU or MPU) of the system or apparatus reads and executes the program code stored in the storage medium. It goes without saying that it will be completed by doing so.
[0127]
In this case, the program code itself read from the storage medium realizes the function of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. As a storage medium for supplying the program code, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, or ROM is used. Can be. When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also an OS or the like running on the computer performs actual processing based on the instruction of the program code. It goes without saying that a case where some or all of the functions are performed and the functions of the above-described embodiments are realized by the processing is also included.
[0128]
Further, after the program code read from the storage medium is written to a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the expansion is performed based on the instruction of the next program code. It goes without saying that a CPU or the like provided in an expansion board or an expansion unit performs processing and performs a part or all of actual processing, and the processing realizes the functions of the above-described embodiments.
[0129]
【The invention's effect】
As described in detail above, according to the present invention, image expansion, compression, and transfer can be performed simultaneously, and the performance of the device or system can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram illustrating an overall configuration of a multifunction peripheral according to an embodiment of the present invention.
FIG. 2 is a timing chart showing a state of DMA.
FIG. 3 is an internal block diagram showing a configuration of a bus arbiter 113.
FIG. 4 is a schematic block diagram illustrating a configuration of a PDL unit 101.
FIG. 5 is a timing processing diagram illustrating rendering, transfer, and compression processing according to the embodiment.
FIG. 6 is a flowchart showing an operation at the time of starting the system.
FIG. 7 is a schematic block diagram illustrating a configuration of the FAX unit 104.
FIG. 8 is a schematic block diagram illustrating a configuration of a network I / F 102.
[Explanation of symbols]
101 PDL unit
103 Hard Disk
105 System bus
106 Master control block
107 Network
110 Scanner unit
111 Printer unit
112 CLK
115 CPU
118 Scanner / Printer I / F
601 CPU
603 RAM
604 ASIC
605 Work RAM
606 Image memory
608 CLK detection circuit
609 DMA control circuit
612 Image compression circuit

Claims (8)

Image developing means for dividing an image into a plurality of regions and developing an image for each of the divided regions;
Image transfer means for transferring the developed image for each area for each area,
Image compression means for compressing the image data transferred by the image transfer means,
External transfer means for transferring the image data compressed by the image compression means to the outside,
While the image is expanded for each region by the image expanding unit, the expanded image is sequentially transferred to the image compressing unit by the image transfer unit, and the image compressing unit is configured to sequentially transfer a plurality of divided regions into a plurality of regions. An image processing apparatus characterized in that images are compressed while being combined. 2. The image processing apparatus according to claim 1, wherein the external transfer unit performs a plurality of transfers with a predetermined data amount set in advance. An image processing apparatus that generates and transfers compressed image data, and a print system that includes a print output processing apparatus that performs print output processing based on the compressed image data transferred from the image processing apparatus,
The image processing device includes:
Image developing means for dividing an image into a plurality of regions and developing an image for each of the divided regions;
Image transfer means for transferring the developed image for each area for each area,
Image compression means for compressing the image data transferred by the image transfer means,
Print transfer means for transferring the compressed image data compressed by the image compression means to the print output processing device,
While the image is expanded for each region by the image expanding unit, the expanded image is sequentially transferred to the image compressing unit by the image transfer unit, and the image compressing unit is configured to sequentially transfer a plurality of divided regions into a plurality of regions. A printing system characterized in that images are compressed while being combined. 4. The print system according to claim 3, wherein the print transfer unit performs the transfer a plurality of times with a predetermined data amount set in advance. Dividing the image into a plurality of regions, and developing the image for each of the divided regions, sequentially transferring the developed image;
An image compression step of compressing while combining images of a series of divided areas sequentially transferred in the image transfer step;
An external transfer step of transferring the image data compressed in the image compression step to the outside. 6. The method according to claim 5, wherein in the external transfer step, the transfer is performed a plurality of times with a predetermined data amount set in advance. A computer-readable control program for executing a method of controlling an image processing apparatus that generates and transfers compressed image data, comprising:
An image transfer step of dividing the image into a plurality of regions and sequentially transferring the developed image while developing the image for each of the divided regions;
An image compression step of compressing a series of divided images sequentially transferred in the image transfer step while combining the images.
An external transfer step of transferring the image data compressed in the image compression step to the outside. 8. The control program according to claim 7, wherein in the external transfer step, the transfer is performed a plurality of times with a predetermined data amount set in advance.

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