JP2004072022A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2004072022A
JP2004072022A JP2002232629A JP2002232629A JP2004072022A JP 2004072022 A JP2004072022 A JP 2004072022A JP 2002232629 A JP2002232629 A JP 2002232629A JP 2002232629 A JP2002232629 A JP 2002232629A JP 2004072022 A JP2004072022 A JP 2004072022A
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Prior art keywords
temperature
furnace
relationship
obtaining
processing
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JP2002232629A
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Japanese (ja)
Inventor
Fusayuki Nakao
中尾 総之
Takeo Hanashima
花島 建夫
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Hitachi Kokusai Electric Inc
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Hitachi Kokusai Electric Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which is capable of reducing the number of conditioning process for obtaining the set temperature of a heater through dummy-less processing. <P>SOLUTION: The method of manufacturing a semiconductor device comprises a first process of carrying out batch processing of a plurality of times as the number n of processing substrates is varied and obtaining a relation between lnx and 1/y in each batch processing when thickness uniformity is below a reference value, wherein y denotes a temperature at an optional position x in the direction of a gas flow in an oven; a second process of obtaining a first approximate expression linearly approximating the relation between lnx and 1/y; a third process of obtaining a relation between the tilt a<SB>1</SB>of the first approximate expression and the number n of the processing substrates and a relation between the intercept b<SB>1</SB>of the first approximate expression and the number of processing substrates; a fourth process of obtaining a second and a third approximate expression linearly approximating the above relations; a fifth process of obtaining a relation between x and y on the basis of the first to the third approximate expression when the number of processing substrates is represented by n and obtaining a furnace temperature gradient; a sixth process of calculating a set temperature of each heater zone. so as to form a furnace temperature gradient; and a seventh process of setting the temperature of each heater zone to the calculated set temperature and carrying out batch processing. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関し、特に縦型バッチ式装置におけるダミーレス処理に関するものである。
【0002】
【従来の技術】
現在のCVDプロセスにおいては、プロダクトウェハが規定枚数に満たない場合、フィルダミーウェハを投入することで対応している。フィルダミーウェハを用いない場合、ウェハの無い空間領域の影響により、バッチ内におけるウェハ間での膜厚均一性が低下する。具体的には、空間に最も近い部分のモニタウェハの膜厚がフィルダミーウェハを用いた状態と比較して大きく増加する。これを制御するために、プロダクトウェハを処理ガスの流れ方向の上流側に寄せた状態で保持し、すぐ下流側にダミーウェハを置き空間に最も近いモニタの領域に入るヒータの設定温度を下げる方法がとられている。
【0003】
【発明が解決しようとする課題】
しかしながら、上述した従来の半導体装置の製造方法においては、フィルダミーウェハを用いて処理を行うようにしているため、ヒータの設定温度を求めるのが複雑になるという問題があった。
【0004】
本発明は上述した点に鑑みてなされたもので、フィルダミーウェハを用いず処理を行うことができ、ヒータの設定温度を求めるための条件出し回数を低減することができる炉内の温度傾斜設定に特徴を有する半導体装置の製造方法を提供することを目的とする。
【0005】
【課題を解決するための手段】
前記目的を達成するために、本発明に係る半導体装置の製造方法は、複数のゾーンに分割されたヒータを有する反応炉内でn枚の基板をボートに支持し、ガス流上流側に詰めた状態で加熱してバッチ処理する工程を有する半導体装置の製造方法であって、炉内のガス流方向の任意位置xにおける炉内温度をyとし、処理枚数nを変化させて複数回バッチ処理し、膜厚均一性が基準値以下となったときのそれぞれのバッチ処理におけるlnxと1/yとの関係を求める工程と、前記lnxと1/yとの関係を直線で近似し、第1の近似式(lnx=a×1/y+b)を得る工程と、第1の近似式の傾きaと処理枚数nとの関係、および第1の近似式の切片bと処理枚数nとの関係を求める工程と、前記第1の近似式の傾きaと処理枚数nとの関係、および第1の近似式の切片bと処理枚数nとの関係を直線で近似し、第2の近似式(a=aa1×n+ba1)および第3の近似式(b=ab1×n+bb1)を得る工程と、前記第1〜第3の近似式により、処理枚数をnとしたときの炉内の任意位置xと炉内温度yとの関係を求め、処理枚数をnとしたときの炉内温度傾斜を求める工程と、前記炉内温度傾斜を形成するように各ヒータゾーンの設定温度を算出する工程と、各ヒータゾーンの温度を、前記算出した設定温度に設定して前記反応炉内でn枚の基板をバッチ処理する工程とを有することを特徴とするものである。
【0006】
この構成によれば、フィルダミーウェハを用いず処理を行うことができ、ヒータの設定温度を求めるための条件出し回数を低減することができる。
【0007】
なお、上記構成において、各ヒータゾーンの設定温度を変化させたときの炉内の任意位置における温度変化量を求めて行列Mを得る工程を有し、前記各ヒータゾーンの設定温度を算出する工程では、この行列Mを用いて前記炉内温度傾斜を形成するような各ヒータゾーンの設定温度を算出するようにすることができる。
【0008】
【発明の実施の形態】
以下、本発明の実施の形態について説明する。図1は、本発明に実施の形態に係る反応炉を示す構成図である。図1に示す反応室は、U、CU、C、CL、Lの5ゾーンに分割されたヒータ1により加熱される。反応室はアウターチューブ2の内部にインナーチューブ3を有し、インナーチューブ3の内側には複数のウェハ4を装填できるボート5を有している。このボート5の下部には断熱板6を保持できる。また、炉内温度制御のための5対のカスケード制御TC7と連続した炉内温度分布を測定でき、脱着可能なプロファィルTC8を有している。
【0009】
ガスはノズル9から供給され、インナーチューブ3の内側を通り、インナーチューブ3上部からインナーチューブ3とアウターチューブ2の間を通って排気口10から排出される。ヒータ1とカスケード制御TC7の位置関係は、図2に示す通りであり、カスケード制御TC7の位置を上からUc、CUc、Cc、CLc、Lcとする。
【0010】
ウェハの処理は次の手順により行う。ボート5上に装填したウェハ4を反応室へと投入し、反応室を減圧する。十分減圧した後、反応室を窒素でパージし、所定の圧力に安定させる。温度、圧力が十分安定した後、プロセスガスを供給し、成膜を行う。成膜が終了したら、反応室に窒素を供給しながら大気圧に戻し、ボート5を降下させる。ウェハ4を冷却した後回収する。
【0011】
ボート5上のウェハの配置は、図3に示すように、サイドダミーウェハ11でプロダクトウェハ12を挟むようにし、モニタウェハ13をプロダクトウェハ12の任意の位置に挿入する。これらを処理ガスの流れ方向の上流側に寄せた状態で保持する。例えば、フルチャージで150枚のウェハを処理できるボート5を用いて100枚のウェハを処理する場合、図4に示すように、ガス流の上流側に詰めた状態で保持する。
【0012】
実際に、SiNの成膜をフルチャージ150枚、ダミーレス100枚、ダミーレス50枚のウェハで行い、ウェハ間の膜厚均一性を合わせたときのウェハ配置は、図5に示す通りであり、サイドダミーウェハ11は、プロダクトウェハ12上部に5枚、下部に10枚、モニタウェハ13をプロダクトウェハ25枚毎に1枚設置した。各処理におけるモニタウェハ13の成膜速度均一性が1%以下となったときの設定温度は図6のようになった。この設定温度を各モニタ位置の温度へと変換するために干渉行列を用いる。
【0013】
干渉行列を作成するために次の測定を行った。まず、炉内を基準となる温度に設定し、十分安定させた後、プロファイルTC8を一定速度で降下させ、炉内の温度分布を測定する。その後、各ゾーンにおいて、それぞれ任意温度に上昇させ安定させた後、再びプロファイルTC8による炉内温度の測定を行う。これにより、各ゾーンを+1℃としたときの炉内の連続した温度分布を求める。オートプロファイラの移動距離をボートのスロット位置へと変換し、これを干渉行列Mと定義すると、炉内位置x点での温度Tをカスケード制御TC7の設定温度TUc、TCUc、TCc、TCLc、TLcと基準温度Tを用いて次式(1)のように表すことができる。
【0014】
【数1】

Figure 2004072022
ここで、a、b、c、d、eは、TUc、TCUc、TCc、TCLc、TLcの温度を1℃変化させたときの位置xにおける温度変化である。すなわち、炉内温度は制御温度を用いて次式(2)のようにして表すことができる。
【0015】
【数2】
Figure 2004072022
【0016】
最下部を基準としたボートスロットのモニタ位置167、141、115、89、63、37、11の炉内の温度を求める干渉行列は、7×5の行列となり、150枚処理時のモニタ位置での温度は図7のようになる。同様に、100枚、50枚処理時のモニタ位置の温度も図7に示す。
【0017】
ここで、モニタウェハの位置(ボートスロット)をx、その部分の温度をy(絶対温度)としたとき、lnx対1/yでプロットすると、図8に示したようになる。これを直線で近似し、傾きをa、切片をbとすると、それぞれの処理枚数において、a、bの値は図9となる。
【0018】
次に、このa、bを処理枚数の関数としてプロットすると図10となり、これを直線近似したときの係数をaa1、ba1およびab1、bb1とする。すなわち、プロダクト75枚を処理する場合の係数a、bは、a=75×aa1+ba1、b=75×ab1+bb1によって求められる。したがって、このとき、炉内温度の傾斜は、y=a×lnx+bにそれぞれのモニタ位置を入力することよって計算できる。具体的には、図8および図10に示すような結果があると、75枚処理時には図11のような温度傾斜となる。
【0019】
一方、炉内温度を制御温度へ変換する際には、転置行列Mtを用いて次式(3)により変換を行う。
【数3】
Figure 2004072022
図11の温度傾斜を用いた場合、式(3)を用いて計算した設定温度は図12になる。この温度傾斜を用いて実際に成膜を行うと、モニタウェハ膜厚の面間均一性が1.4%となった。
【0020】
以上説明した本発明における半導体装置の製造方法を要約すると次の通りである。本発明における半導体装置の製造方法は、複数のゾーンに分割されたヒータを有する反応炉内でn枚の基板をボートに支持し、ガス流上流側に詰めた状態で加熱してバッチ処理する工程を有する半導体装置の製造方法であって、
炉内のガス流方向の任意位置(ガス流の最上流にあるスロットを基準としたボートスロット位置)xにおける炉内温度をyとし、処理枚数nを変化させて(150枚、100枚、50枚)複数回バッチ処理し、膜厚均一性が基準値以下(1%以下)となったときのそれぞれのバッチ処理におけるlnxと1/yとの関係を求める工程と(図8参照)、
前記lnxと1/yとの関係を直線で近似し、第1の近似式(lnx=a×1/y+b)を得る工程と(図8、図9参照)、
第1の近似式の傾きaと処理枚数nとの関係、および第1の近似式の切片bと処理枚数nとの関係を求める工程と(図10参照)、
前記第1の近似式の傾きaと処理枚数nとの関係、および第1の近似式の切片bと処理枚数nとの関係を直線で近似し、第2の近似式(a=aa1×n+ba1)および第3の近似式(b=ab1×n+bb1)を得る工程と、
前記第1〜3の近似式により、処理枚数をnとしたときの炉内の任意位置xと炉内温度yとの関係を求め、処理枚数をnとしたときの炉内温度傾斜を求める工程と、
前記炉内温度傾斜を形成するよう各ヒータゾーンの設定温度を算出する工程と(ここで干渉行列を用いる)、
各ヒータゾーンの温度を、前記算出した設定温度に設定して前記反応炉内でn枚の基板をバッチ処理する工程と
を有する。
【0021】
また、各ヒータゾーンの設定温度を変化させたときの炉内の任意位置における温度変化量を求めて行列Mを得る工程を有し、前記各ヒータゾーンの設定温度を算出する工程では、この行列Mを用いて前記炉内温度傾斜を形成するような各ヒータゾーンの設定温度を算出する。
【0022】
【発明の効果】
したがって、本発明によれば、フィルダミーウェハを用いず処理を行うことができ、ヒータの設定温度を求めるための条件出し回数を低減することができる。また、フィルダミーに要するコストが必要なくなるだけでなく、ウェハ搬送時間を従来と比較して短縮することもできる。
【図面の簡単な説明】
【図1】本発明に実施の形態に係る反応炉を示す構成図である。
【図2】図1のヒータ1とカスケード制御TC7の位置関係を示す図である。
【図3】ボート上のフルチャージ時のウェハ配置を示す図である。
【図4】フルチャージで150枚のウェハを処理できるボートを用いて100枚のウェハを処理する場合のウェハ配置を示す図である。
【図5】SiNの成膜をフルチャージ150枚、ダミーレス100枚、ダミーレス50枚のウェハで行い、ウェハ間の膜厚均一性を合わせたときのウェハ配置を示す図である。
【図6】面間均一性1%以下となったときの設定温度の説明図である。
【図7】面間均一性1%以下となったときのモニタウェハ位置における炉内温度の説明図である。
【図8】モニタ位置xと炉内温度yの関係を示す図である。
【図9】各処理枚数における傾きと切片の説明図である。
【図10】処理枚数と係数a,bの関係を示す図である。
【図11】75枚処理時の炉内温度計算結果を示す図である。
【図12】干渉行列を用いた炉内温度から設定温度への変換の説明図である。
【符号の説明】
1 5ゾーン分割ヒータ
2 アウターチューブ
3 インナーチューブ
4 ウェハ
5 ボート
6 断熱板
7 カスケード制御TC
8 プロファイルTC
9 ノズル
10 排気口
11 サイドダミーウェハ
12 プロダクトウェハ
13 モニタウェハ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a dummyless process in a vertical batch type device.
[0002]
[Prior art]
In the current CVD process, when the number of product wafers is less than a specified number, a fill dummy wafer is inserted to cope with the problem. When a fill dummy wafer is not used, the uniformity of film thickness between wafers in a batch is reduced due to the effect of a space region where no wafer exists. Specifically, the film thickness of the monitor wafer in the portion closest to the space is greatly increased as compared with the state using the fill dummy wafer. In order to control this, a method of holding the product wafer in the state of being brought to the upstream side in the flow direction of the processing gas, placing a dummy wafer immediately downstream, and lowering the set temperature of the heater entering the monitor area closest to the space is used. Has been taken.
[0003]
[Problems to be solved by the invention]
However, in the above-described conventional method for manufacturing a semiconductor device, since processing is performed using a fill dummy wafer, there has been a problem in that obtaining a set temperature of a heater becomes complicated.
[0004]
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and can perform processing without using a fill dummy wafer, and can reduce the number of conditions for obtaining a set temperature of a heater. It is an object of the present invention to provide a method for manufacturing a semiconductor device having the following features.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, in a method for manufacturing a semiconductor device according to the present invention, n substrates are supported on a boat in a reactor having a heater divided into a plurality of zones, and are packed on a gas flow upstream side. A method of manufacturing a semiconductor device having a step of performing batch processing by heating in a state, wherein the furnace temperature at an arbitrary position x in the gas flow direction in the furnace is set to y, and the number n of processed wafers is changed to perform batch processing a plurality of times. Obtaining the relationship between lnx and 1 / y in each batch process when the film thickness uniformity is equal to or less than the reference value, and approximating the relationship between lnx and 1 / y with a straight line, The step of obtaining the approximate expression (lnx = a 1 × 1 / y + b 1 ), the relationship between the slope a 1 of the first approximate expression and the number of processed sheets n, and the intercept b 1 and the number of processed sheets n of the first approximate expression treatment and process, the gradient a 1 in the first approximation formula for obtaining the relationship Relationship between the number n, and a first approximation equation relationship between the intercept b 1 and the processing number n of approximated by a straight line, the second approximation formula (a 1 = a a1 × n + b a1) and the third approximate expression (B 1 = a b1 × n + b b1 ) and the relationship between an arbitrary position x in the furnace and the temperature y in the furnace when the number of substrates to be processed is n is determined by the first to third approximate expressions. Calculating the furnace temperature gradient when the number of processed sheets is n; calculating the set temperature of each heater zone so as to form the furnace temperature gradient; and calculating the temperature of each heater zone. Setting a set temperature and batch-processing n substrates in the reaction furnace.
[0006]
According to this configuration, the processing can be performed without using the fill dummy wafer, and the number of conditions for obtaining the set temperature of the heater can be reduced.
[0007]
In the above configuration, a step of obtaining a matrix M by obtaining a temperature change amount at an arbitrary position in the furnace when the set temperature of each heater zone is changed, and calculating the set temperature of each heater zone Then, the set temperature of each heater zone that forms the furnace temperature gradient can be calculated using the matrix M.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described. FIG. 1 is a configuration diagram illustrating a reactor according to an embodiment of the present invention. The reaction chamber shown in FIG. 1 is heated by a heater 1 divided into five zones U, CU, C, CL, and L. The reaction chamber has an inner tube 3 inside the outer tube 2 and a boat 5 on which a plurality of wafers 4 can be loaded inside the inner tube 3. A heat insulating plate 6 can be held below the boat 5. Further, it has five pairs of cascade control TC7 for furnace temperature control and a removable profile TC8 which can measure the furnace temperature distribution continuously.
[0009]
The gas is supplied from the nozzle 9, passes through the inside of the inner tube 3, and is discharged from the upper part of the inner tube 3 through the space between the inner tube 3 and the outer tube 2 from the exhaust port 10. The positional relationship between the heater 1 and the cascade control TC7 is as shown in FIG. 2, and the positions of the cascade control TC7 are Uc, CUc, Cc, CLc and Lc from the top.
[0010]
Wafer processing is performed according to the following procedure. The wafer 4 loaded on the boat 5 is charged into the reaction chamber, and the pressure in the reaction chamber is reduced. After sufficiently reducing the pressure, the reaction chamber is purged with nitrogen and stabilized at a predetermined pressure. After the temperature and pressure are sufficiently stabilized, a process gas is supplied to form a film. When the film formation is completed, the pressure is returned to the atmospheric pressure while supplying nitrogen to the reaction chamber, and the boat 5 is lowered. After the wafer 4 is cooled, it is collected.
[0011]
As shown in FIG. 3, the wafers on the boat 5 are arranged such that the product wafer 12 is sandwiched between the side dummy wafers 11, and the monitor wafer 13 is inserted into an arbitrary position of the product wafer 12. These are held in a state of being brought to the upstream side in the flow direction of the processing gas. For example, when processing 100 wafers using a boat 5 capable of processing 150 wafers at full charge, as shown in FIG. 4, the wafer is held in a state of being packed upstream of the gas flow.
[0012]
Actually, the SiN film is formed on 150 wafers of full charge, 100 wafers of dummyless, and 50 wafers of dummyless, and the wafer arrangement when the film thickness uniformity between wafers is matched is as shown in FIG. Five dummy wafers 11 were placed above the product wafer 12, ten were placed below the product wafer 12, and one monitor wafer 13 was placed for every 25 product wafers. The set temperature when the uniformity of the film forming speed of the monitor wafer 13 in each process became 1% or less was as shown in FIG. An interference matrix is used to convert the set temperature into the temperature at each monitor position.
[0013]
The following measurements were made to create an interference matrix. First, the inside of the furnace is set to a reference temperature and, after sufficiently stabilized, the profile TC8 is lowered at a constant speed to measure the temperature distribution in the furnace. After that, in each zone, after the temperature is raised to an arbitrary temperature and stabilized, the furnace temperature is measured again by the profile TC8. Thus, a continuous temperature distribution in the furnace when each zone is set to + 1 ° C. is obtained. The moving distance of the auto profiler converted into slot positions of the boat, by defining it as interference matrix M, setting the temperature T x at the furnace position x point cascade control TC7 temperature T Uc, T CUc, T Cc , Using T CLc and T Lc and the reference temperature T 0 , it can be expressed as the following equation (1).
[0014]
(Equation 1)
Figure 2004072022
Here, a x, b x, c x, d x, e x is the temperature change at the position x when the T Uc, T CUc, T Cc , T CLc, the temperature of T Lc is 1 ℃ changed . That is, the furnace temperature can be represented by the following equation (2) using the control temperature.
[0015]
(Equation 2)
Figure 2004072022
[0016]
The interference matrix for calculating the temperature in the furnace at the monitor positions 167, 141, 115, 89, 63, 37, and 11 of the boat slots with respect to the bottom is a 7 × 5 matrix. Is as shown in FIG. Similarly, FIG. 7 also shows the temperature at the monitor position when processing 100 sheets and 50 sheets.
[0017]
Here, assuming that the position of the monitor wafer (boat slot) is x and the temperature of that portion is y (absolute temperature), plotting lnx vs. 1 / y is as shown in FIG. If this is approximated by a straight line and the slope is a 1 and the intercept is b 1 , the values of a 1 and b 1 for each number of processed sheets are as shown in FIG.
[0018]
Then, next to FIG. 10 A plot of this a 1, b 1 as a function of the processed sheets, which the modulus of linear approximation to a a1, b a1 and a b1, b b1. That is, the coefficients a 1 and b 1 when processing 75 products are obtained from a 1 = 75 × a a1 + b a1 and b 1 = 75 × a b1 + b b1 . Accordingly, at this time, the inclination of the furnace temperature can be calculated by inputting each monitor position to y = a 1 × lnx + b 1 . Specifically, if there are the results shown in FIGS. 8 and 10, the temperature gradient will be as shown in FIG. 11 when 75 sheets are processed.
[0019]
On the other hand, when converting the in-furnace temperature into the control temperature, the conversion is performed by the following equation (3) using the transposed matrix Mt.
[Equation 3]
Figure 2004072022
When the temperature gradient shown in FIG. 11 is used, the set temperature calculated using Expression (3) is as shown in FIG. When film formation was actually performed using this temperature gradient, the inter-surface uniformity of the monitor wafer film thickness was 1.4%.
[0020]
The manufacturing method of the semiconductor device according to the present invention described above is summarized as follows. A method of manufacturing a semiconductor device according to the present invention includes a step of supporting n substrates on a boat in a reaction furnace having a heater divided into a plurality of zones, and heating and batch-treating the substrate in a state where the substrate is packed upstream of a gas flow. A method for manufacturing a semiconductor device having
The temperature in the furnace at an arbitrary position in the gas flow direction in the furnace (boat slot position with reference to the slot at the uppermost stream of the gas flow) x is set to y, and the number n of processed wafers is changed (150, 100, 50 (B) a plurality of batch processes, and a process of obtaining the relationship between lnx and 1 / y in each batch process when the film thickness uniformity is equal to or less than a reference value (1% or less) (see FIG. 8);
A process of approximating the relationship between lnx and 1 / y with a straight line to obtain a first approximation formula (lnx = a 1 × 1 / y + b 1 ) (see FIGS. 8 and 9);
Obtaining a relationship between the slope a 1 of the first approximate expression and the number n of processed sheets and a relationship between the intercept b 1 of the first approximate expression and the number n of processed sheets (see FIG. 10);
Said first approximate equation relationship between the gradient a 1 and the processing number n, and a first approximation equation relationship between the intercept b 1 and the processing number n of approximated by a straight line, the second approximation formula (a 1 = a a1 × n + b a1 ) and a third approximate expression (b 1 = a b1 × n + b b1 );
A step of obtaining a relationship between an arbitrary position x in the furnace and a furnace temperature y when the number of processed pieces is n and a furnace temperature gradient when the number of processed pieces is n by the first to third approximate expressions When,
Calculating a set temperature of each heater zone to form the furnace temperature gradient (using an interference matrix here);
Setting the temperature of each heater zone to the calculated set temperature and batch processing n substrates in the reaction furnace.
[0021]
In addition, the method includes a step of obtaining a matrix M by calculating a temperature change amount at an arbitrary position in the furnace when the set temperature of each heater zone is changed, and calculating the set temperature of each heater zone by using the matrix Using M, the set temperature of each heater zone that forms the furnace temperature gradient is calculated.
[0022]
【The invention's effect】
Therefore, according to the present invention, processing can be performed without using a fill dummy wafer, and the number of conditions for obtaining the set temperature of the heater can be reduced. Further, not only is the cost required for the fill dummy unnecessary, but also the wafer transfer time can be reduced as compared with the conventional case.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a reactor according to an embodiment of the present invention.
FIG. 2 is a diagram showing a positional relationship between a heater 1 and a cascade control TC7 in FIG.
FIG. 3 is a diagram showing a wafer arrangement when a boat is fully charged.
FIG. 4 is a diagram showing a wafer arrangement when processing 100 wafers using a boat capable of processing 150 wafers with full charge.
FIG. 5 is a diagram showing a wafer arrangement when the film formation of SiN is performed on 150 wafers of full charge, 100 dummyless wafers, and 50 dummyless wafers, and the film thickness uniformity between the wafers is adjusted.
FIG. 6 is an explanatory diagram of a set temperature when the inter-surface uniformity is 1% or less.
FIG. 7 is an explanatory diagram of a furnace temperature at a monitor wafer position when the inter-plane uniformity is 1% or less.
FIG. 8 is a diagram showing a relationship between a monitor position x and a furnace temperature y.
FIG. 9 is an explanatory diagram of a slope and an intercept for each number of processed sheets.
FIG. 10 is a diagram showing a relationship between the number of processed sheets and coefficients a 1 and b 1 .
FIG. 11 is a diagram showing a furnace temperature calculation result when processing 75 sheets.
FIG. 12 is an explanatory diagram of conversion from a furnace temperature to a set temperature using an interference matrix.
[Explanation of symbols]
1 5 zone divided heater 2 outer tube 3 inner tube 4 wafer 5 boat 6 heat insulating plate 7 cascade control TC
8 Profile TC
9 Nozzle 10 Exhaust port 11 Side dummy wafer 12 Product wafer 13 Monitor wafer

Claims (1)

複数のゾーンに分割されたヒータを有する反応炉内でn枚の基板をボートに支持し、ガス流上流側に詰めた状態で加熱してバッチ処理する工程を有する半導体装置の製造方法であって、
炉内のガス流方向の任意位置xにおける炉内温度をyとし、処理枚数nを変化させて複数回バッチ処理し、膜厚均一性が基準値以下となったときのそれぞれのバッチ処理におけるlnxと1/yとの関係を求める工程と、
前記lnxと1/yとの関係を直線で近似し、第1の近似式(lnx=a×1/y+b)を得る工程と、
第1の近似式の傾きaと処理枚数nとの関係、および第1の近似式の切片bと処理枚数nとの関係を求める工程と、
前記第1の近似式の傾きaと処理枚数nとの関係、および第1の近似式の切片bと処理枚数nとの関係を直線で近似し、第2の近似式(a=aa1×n+ba1)および第3の近似式(b=ab1×n+bb1)を得る工程と、
前記第1〜第3の近似式により、処理枚数をnとしたときの炉内の任意位置xと炉内温度yとの関係を求め、処理枚数をnとしたときの炉内温度傾斜を求める工程と、
前記炉内温度傾斜を形成するように各ヒータゾーンの設定温度を算出する工程と、
各ヒータゾーンの温度を、前記算出した設定温度に設定して前記反応炉内でn枚の基板をバッチ処理する工程と
を有することを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device, comprising: a step of supporting n substrates on a boat in a reaction furnace having a heater divided into a plurality of zones, and heating and batch-treating the substrates in a state of being packed on an upstream side of a gas flow. ,
The furnace temperature at an arbitrary position x in the gas flow direction in the furnace is set to y, batch processing is performed a plurality of times while changing the number n of processed sheets, and lnx in each batch processing when the film thickness uniformity becomes equal to or less than a reference value. Determining the relationship between and 1 / y;
A step of approximating the relationship between lnx and 1 / y with a straight line to obtain a first approximate expression (lnx = a 1 × 1 / y + b 1 );
Obtaining a relationship between the slope a 1 of the first approximate expression and the number n of processed sheets, and a relationship between the intercept b 1 of the first approximate expression and the number n of processed sheets;
Said first approximate equation relationship between the gradient a 1 and the processing number n, and a first approximation equation relationship between the intercept b 1 and the processing number n of approximated by a straight line, the second approximation formula (a 1 = a a1 × n + b a1 ) and a third approximate expression (b 1 = a b1 × n + b b1 );
The relationship between the arbitrary position x in the furnace and the furnace temperature y when the number of processed pieces is n is obtained by the first to third approximate expressions, and the furnace temperature gradient when the number of processed pieces is n is obtained. Process and
Calculating a set temperature of each heater zone so as to form the furnace temperature gradient,
Setting the temperature of each heater zone to the calculated set temperature and batch processing n substrates in the reaction furnace.
JP2002232629A 2002-08-09 2002-08-09 Method of manufacturing semiconductor device Withdrawn JP2004072022A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7517141B2 (en) 2004-05-04 2009-04-14 Texas Instruments Incorporated Simultaneous control of deposition time and temperature of multi-zone furnaces

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7517141B2 (en) 2004-05-04 2009-04-14 Texas Instruments Incorporated Simultaneous control of deposition time and temperature of multi-zone furnaces

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