JP2004071957A - Methods for developing and manufacturing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide methods for attaining the development/manufacture of semiconductor integrated circuits in a short period by easily reflecting an element model devised by a user of a circuit simulator to the circuit simulator and performing accurate circuit verification suited to an integrated circuit in developing. <P>SOLUTION: In performing the circuit verification of a power IC having a PNP bipolar transistor Q1 comprising lateral structure, the transistor Q1 is defined as a circuit block obtained by connecting a main transistor Tr0 to parasitic transistors Tr1, Tr2 by using a circuit block definition function included in a simulation device to simulate the transistor Q1. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for developing a semiconductor integrated circuit using a circuit simulator, for example, a technology useful for application to the development and production of a high-output semiconductor integrated circuit used for power control of automobile electric components and various electric devices. About.
[0002]
[Prior art]
Generally, in the development of a semiconductor integrated circuit, operation verification is performed by simulation to determine whether a designed circuit operates normally. A circuit simulator is composed of, for example, a computer such as a workstation and software operating on the computer.A user inputs circuit information and simulation conditions and causes the circuit simulator to perform calculations. Various operations can be verified, such as displaying the current / voltage characteristics of the nodes. The circuit information input to the circuit simulator includes information on each element constituting the circuit and a netlist indicating a connection relationship between the elements.
[0003]
In the program of the circuit simulator, an element model expression expressing the characteristic of each element by a mathematical expression or the like is described in advance. By setting parameters included in this element model expression by a user, the characteristic represented by the element model expression is set. Adjustment can be made closer to actual element specification. The values of the parameters of the element model are determined, for example, by first forming a sample of the element under the same semiconductor process conditions as those used in the product, measuring the characteristics of the element, and matching the measured values.
[0004]
[Problems to be solved by the invention]
Conventionally, many types of models have been devised as models of transistors used in circuit simulation, and have been adopted in various circuit simulators. However, none of the currently used device models can express characteristics so as to completely match the actual device, so using the device model provided in the circuit simulator reflects the required characteristics in the simulation. May not be.
[0005]
For example, in a power IC (semiconductor integrated circuit) that performs power control of electric components of an automobile or various electric devices, a transistor operates in a saturation region because a high voltage of 100 V or more may be input. There is a demand to accurately verify the substrate current flowing at this time, but there is no conventional transistor model that accurately represents the operating characteristics in such a saturation region. For example, in a power semiconductor IC that does not involve high-frequency operation, a PNP transistor having a lateral structure that can be formed at low cost is often used. However, in an element model used in a conventional circuit simulator, a parasitic element generated in the PNP transistor is used. The effect of the transistor is not considered, and as a result, there is a problem that the operation of an integrated circuit using such an element cannot be accurately simulated.
[0006]
In a circuit simulator, an element model used in a simulation is usually predetermined, and a designer who is a user of the circuit simulator cannot change the element model. Therefore, even if the designer has devised an element model suitable for the integrated circuit under development, in order to incorporate this element model into the circuit simulator and use it, for example, request the circuit simulator developer to modify the software. Such a process requires time and cost, and is not an easy means to perform.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to make it possible to easily reflect an element model devised by a user of a circuit simulator in a circuit simulator and to perform accurate circuit verification suitable for an integrated circuit under development, thereby shortening a period of time. It is an object of the present invention to provide a method capable of achieving development and production of a semiconductor integrated circuit.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be described as follows.
That is, one element is defined as a circuit block in which a plurality of elements are connected using a circuit block definition function provided in the simulation apparatus, a simulation is performed, and a design circuit is verified.
As a result, even if an element whose necessary characteristics cannot be expressed using the circuit model provided in the simulator device is defined as a circuit block in which the required characteristics are expressed, an accurate design circuit can be obtained. Verification can be performed, thereby shortening the total development period of the semiconductor integrated circuit.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a circuit simulator used in the development stage of the semiconductor integrated circuit according to the present embodiment.
The circuit simulator 10 used in the embodiment of the present invention is similar to a conventional general circuit simulator, and includes circuit connection information (net list) in which the contents and connection information of elements constituting a circuit are described. , Control information necessary for executing a simulation such as operating conditions of the circuit and what characteristics of which element or at which contact point are to be output, and model information in which parameters of an element model representing the characteristics of each element are described. And simulates the design circuit in accordance with the information. Then, the output result of the simulation is output by displaying a data file F4 or a characteristic graph.
[0010]
The above-described circuit connection information, control information, and model information can be input as one data file according to a predetermined format, or can be input separately as separate data files F1 to F3. The data file in which the circuit connection information is described is generally called a circuit description data file F1.
[0011]
The circuit simulator 10 is provided in advance with element model expressions representing the characteristics of various elements, and the user selects an element model expression to be used and determines values of model parameters included in the element model expression. The characteristics of the element on the simulator device can be determined. Model parameters are, for example, prototype each element under the same conditions as the manufacturing process when manufacturing a design circuit, measure the characteristics of these elements, and determine to match the characteristic values indicated by the element model formula By doing so, an element model having characteristics close to those of an element actually manufactured can be obtained.
[0012]
The values of the model parameters are generally described together with the name of the element model (called a model name) in a data file F3 storing model information. Can be specified for each element of the circuit by including it in the description representing the content of each element. In the former case, in the circuit description data file F1 representing the content of the circuit to be simulated, the model name is described in the description representing the content of each element, so that the value of the model parameter of this element becomes the data of the model information. It will be called and used from the file F3.
[0013]
Since the element size changes frequently, the model information data file F3 registers model parameters representing characteristics when the element size is defined as a unit area, while each of the circuit parameters in the circuit description data file F1 is registered. In general, when representing an element, a model name and an element size are designated so that characteristics according to the element size are calculated.
[0014]
The circuit simulator 10 used in this embodiment has a circuit block registration function capable of registering a circuit block in which a plurality of elements are connected and treating the circuit block as one unit. Here, the circuit block is generally called a sub-circuit, and can be defined in the circuit description data file F1 in which the circuit connection information is described, or in the data file F3 of the model information. It can also be described and defined. Alternatively, only the definition description of the sub-circuit may be combined into one data file.
[0015]
The format of the definition description of the sub-circuit is almost the same as that of the description of the circuit to be simulated. For example, in the description of the first row, the notation indicating the sub-circuit and the name of the sub-circuit (sub-circuit Is called). The model parameters of each element constituting the sub-circuit can be all described in the definition statement of the sub-circuit, or can be described as a function of a user-defined parameter in the definition statement, and the circuit description By referring to the value of the user-defined parameter when calling the sub-circuit in the circuit connection information of the data file F1, the model parameter of each element constituting the sub-circuit can be determined.
[0016]
In the present invention, although it is originally one element constituting a circuit, it is more appropriate to treat it as a circuit block than to treat it as a single element in consideration of parasitic elements such as transistors and diodes that are parasitic on this element. It was determined that there was a certain element.
[0017]
Next, some examples of elements which are treated as circuit blocks in a simulation process of a design circuit performed in a development stage of the semiconductor integrated circuit of this embodiment will be described.
FIG. 2 is a longitudinal sectional view showing the element structure of a lateral PNP bipolar transistor constituting a circuit block, and FIG. 3 is a circuit configuration diagram in a case where the bipolar transistor is defined as a sub-circuit.
[0018]
Regarding the characteristics of the lateral structure PNP bipolar transistor Q1, when the element model of the bipolar transistor provided in the circuit simulator is used, the characteristic in the saturation region greatly deviates from the actual element characteristic no matter what value is set to the model parameter. Will happen. The present inventors have considered that the reason is that the action of the parasitic transistor accompanying the PNP bipolar transistor Q1 having the lateral structure is not considered.
[0019]
The PNP bipolar transistor Q1 having a lateral structure includes a PNP-type main transistor Tr0 including an n-type base region BA and a p-type collector region CA and an emitter region EA formed on the surface thereof, as well as PNP-type parasitic transistors Tr1 and Tr2. Contains. The parasitic transistor Tr1 exists between the emitter region EA and the base region BA of the main transistor Tr0 and the substrate SUB, while the parasitic transistor Tr2 exists between the collector region CA and the base region BA of the main transistor Tr0 and the substrate SUB. Exists.
[0020]
Therefore, in the development method of the semiconductor integrated circuit of this embodiment, as a handling of the design circuit in the simulation, one lateral structure PNP bipolar transistor Q1 is used as the parasitic transistors Tr1 and Tr2 as shown in FIG. Circuit block, which is defined as a sub-circuit and handled.
The main transistor Tr0 and the parasitic transistors Tr1 and Tr2 constituting the sub-circuit can be represented by using a bipolar transistor element model provided in the circuit simulator.
[0021]
Next, how to handle model parameters of each element will be described.
Since the main transistor Tr0 and the parasitic transistors Tr1 and Tr2 cannot be individually measured for each element, a method of extracting a model parameter value applied to a normal element model cannot be used as it is. Also, if an attempt is made to extract an accurate parameter value more than necessary to match the actual device characteristics, the extraction of the parameter value becomes extremely complicated. It is better to narrow down to the minimum necessary. The following method of extracting model parameters focuses on the basic characteristics of the transistor and the substrate current characteristics not represented by the basic characteristics as the minimum necessary characteristics for the simulation, focusing on these two characteristics. It is a thing.
[0022]
The method of extracting the model parameters of each element of the sub-circuit is as shown in the following (1) to (5).
(1) As shown by the main transistor Tr0, the basic characteristics of the lateral structure PNP bipolar transistor Q1 are used to extract the values of all the model parameters of the main transistor Tr0 based on the measured values of the basic characteristics in the same manner as in the related art. However, as described in (5) below, the parameters “CJS, VJS, MJS” regarding the capacitance between the collector and the substrate can be represented by the parasitic transistors Tr1 and Tr2. .
The model parameters vary depending on the element model, but for example, 40 to 50 other parameters such as transport saturation current, ideal maximum forward β, forward current emission coefficient, forward early voltage, etc. are predetermined. .
[0023]
(2) A forward substrate current flowing from the emitter terminal E of the main transistor Tr0 to the substrate terminal Sub is represented by a parameter of a forward current characteristic of the parasitic transistor Tr1.
That is, based on the graph showing the measurement result of the base-emitter voltage Vbe-the forward substrate current ISub of the lateral structure PNP bipolar transistor Q1 shown in FIG. 4, the transport saturation current “IS” of the parasitic transistor Tr1 and the forward current The emission coefficient “NF”, the forward β high current roll-off corner “IKF” representing the current value at which the first inflection point of the characteristic line is located, and the emitter resistance “RE” are determined.
[0024]
(3) A reverse substrate current flowing from the collector terminal C to the substrate terminal Sub is represented by a parameter of a forward current characteristic of the parasitic transistor Tr2. Specifically, the method (2) may be performed for the reverse substrate current.
[0025]
(4) The forward base current is the sum of the respective base currents of the main transistor Tr0 and the parasitic transistors Tr1 and Tr2. Since the forward base current is already expressed by the model parameters of the main transistor Tr0 in (1), the forward base current of the parasitic transistors Tr1 and Tr2 is The value of the ideal maximum forward direction β of the parasitic transistors Tr1 and Tr2 is extracted so that the base current can be ignored. For example, the ideal maximum forward direction β of the parasitic transistors Tr1 and Tr2 is set to about 10,000.
[0026]
(5) Extract the value of a parameter related to the base-substrate capacitance so that the capacitance between the base and the substrate is equally divided into the two parasitic transistors Tr1 and Tr2. Here, the transistor model provided in the circuit simulator of the embodiment is an element model (for example, a Gummel-Poon model) in which the substrate capacitance is provided between the collector and the collector. However, in the lateral structure PNP bipolar transistor, since the substrate capacitance is generated between the base terminal B and the substrate capacitance, the measured base-substrate capacitance is adjusted by the base-collector zero bias depletion capacitance “CJC” of the parasitic transistors Tr1 and Tr2.
[0027]
That is, based on the graph showing the measurement result of the base-substrate voltage Vbs-base-substrate capacitance Cbs of the lateral structure PNP bipolar transistor Q1 shown in FIG. 5, the parasitic transistor Tr1 is expressed by the following equations (1) to (3). , Tr2 are set.
CJC (base-collector zero-bias depletion capacitance) = CJS (zero-bias collector substrate capacitance) / 2 (1)
VJC (base-collector internal diffusion potential) = VJS (substrate junction internal diffusion potential) (2)
MJC (base-collector junction index coefficient) = MJS (substrate junction index coefficient) (3)
[0028]
Here, CJC, VJC, and MJC on the left side are model parameters of the parasitic transistors Tr1 and Tr2, and CJS, VJC, and MJC on the right side are values obtained from the graph of FIG.
Note that, depending on the transistor model used in the circuit simulator, the parameters “CJS, VJS, MJS” relating to the collector substrate capacitance of the main transistor Tr0 are set based on the actually measured values, and the parameters “related to the base-collector capacitance of the parasitic transistors Tr1 and Tr2”. CJC, VJC, MJC "may be set to a value that can be ignored.
[0029]
FIG. 6 is a graph showing a comparison between a simulation result and an actually measured value of the characteristic of the lateral structure PNP bipolar transistor. 2A shows a simulation performed as the sub-circuit of FIG. 2, and FIG. 2B shows a simulation performed as a single element model.
As shown in FIG. 6B, when the simulation is performed with the lateral structure PNP bipolar transistor Q1 represented by a single element model, the effect of the parasitic transistor is considered regardless of how the model parameters are set. Therefore, the characteristics in the saturation region are greatly different from the measured values. However, as shown in FIG. 6A, by adding the action of the parasitic transistor as a sub-circuit, the characteristics in the saturation region can be changed to the measured values. You can see they can be approached.
[0030]
Next, a description will be given of a second example of an element that enables accurate simulation by defining it as a circuit block.
FIG. 7 is a longitudinal sectional view showing the element structure of an NPN bipolar transistor having a vertical structure constituting this circuit block, and FIG. 8 is a circuit configuration diagram in a case where the bipolar transistor is defined as a sub-circuit.
As shown in FIG. 7, the vertical bipolar transistor Q2 includes an NPN-type main transistor Tr10 including an n-type collector region CA2, a p-type base region BA2, and an n-type emitter region EA2, a base region BA2, and a collector region. There is a parasitic PNP transistor Tr11 composed of CA2 and substrate SUB.
[0031]
For example, in the field of power ICs, since the current flowing through the circuit increases, it is necessary to accurately analyze the influence of the parasitic transistor Tr11 on the NPN bipolar transistor Q2 having a vertical structure. However, such an analysis cannot be performed with an element model in which the action of the parasitic transistor Tr11 is not considered.
[0032]
Therefore, in this embodiment, as the handling of the design circuit in the simulation process, the NPN bipolar transistor Q2 is regarded as a circuit block having the parasitic transistor Tr11 and the resistors RCX and RBX as constituent elements as shown in FIG. Treated as defined.
The main transistor Tr10 and the parasitic transistor Tr11 constituting the sub-circuit can be represented by using an element model of a bipolar transistor provided in the circuit simulator.
[0033]
Next, a method of extracting model parameters of each element will be described. In this extraction method as well, the parameters to be extracted are narrowed down to the minimum necessary parameters so that the characteristics of the substrate current appear in the simulation. The extraction method is as shown in the following (1) to (5).
[0034]
(1) As shown by the main transistor Tr10, the basic characteristics of the NPN bipolar transistor Q2 extract all model parameter values of the main transistor Tr10 based on the measured values of the basic characteristics by a conventional method. The model parameters are the same as those of the main transistor Tr0 constituting the lateral structure PNP transistor of FIG. However, in (3) to (5), some model parameters of the main transistor Tr10 are changed.
[0035]
(2) A substrate current flowing through the substrate terminal Sub of the NPN bipolar transistor Q2 is represented by a parameter of a forward DC characteristic of the parasitic transistor Tr11.
Specifically, from the graph showing the measurement result of the base-collector voltage Vbc-substrate current Isub in FIG. 9, the transport saturation current “IS” of the parasitic transistor Tr11, the forward current emission coefficient “NF”, the forward β Each of the high current roll-off corners "IKF" is extracted.
[0036]
(3) Extract parameters “CJC, VJC, MJC” regarding the base-collector capacitance of the parasitic transistor Tr11 from the bias characteristics of the collector-substrate capacitance of the NPN bipolar transistor Q2. At this time, the parameters “CJS, VJS, MJS” relating to the substrate capacitance of the main transistor Tr10 are changed to negligible values.
Specifically, the method shown in (5) of the above-mentioned parameter extraction method of the lateral structure PNP bipolar transistor and the graph of the actually measured value to be used are obtained from the bias characteristic curve of the base-substrate capacitance based on the collector-substrate capacitance. Others are almost the same except for the change to the bias characteristic curve.
[0037]
(4) Assuming that the forward current gain of the parasitic transistor Tr11 is infinite (emitter injection efficiency γ = 1 of the parasitic transistor Tr11), the parameter relating to the reverse DC characteristics of the main transistor Tr10 is changed.
Specifically, first, the ideal maximum forward direction β “BF” of the parasitic transistor Tr11 is set to a value (about 10,000) that can be regarded as infinite, and the parasitic transistor Tr11 operates with this setting, and the main transistor Tr10 Is calculated. That is, since the base current of the parasitic transistor Tr11 can be regarded as a negligible value by the above setting, the base current Ib_int flowing to the main transistor Tr10 is calculated from the measured value of the current Ib flowing to the base terminal B to the measured value of the current Is flowing to the substrate terminal Sub. Is subtracted.
[0038]
FIG. 10 is a graph showing the base current Ib_int of the main transistor Tr10.
Then, from the graph of the base current Ib_int, the ideal maximum reverse direction β “BR” relating to the reverse DC characteristic of the main transistor Tr10, the corner “IKR” of the reverse β high current roll-off, the reverse current emission coefficient “NR”, Extract parameters such as collector leakage saturation current “ISC” and base-collector leakage emission coefficient “NC”.
[0039]
(5) The resistance values of the external collector resistance RCX and the external base resistance RBX are extracted from the voltage drop characteristics due to the collector resistance and the base resistance.
Specifically, from the graph showing the measurement results of the base-emitter voltage Vbe-base current Ib and substrate current Isub as shown in FIG. 11, first, the external collector is adjusted to the point where the forward substrate current starts to flow. Extract the resistance RCX. In other words, the condition that the voltage of the node N1 (see FIG. 8) and the voltage of the base terminal B become equal at the voltage point where the substrate current starts to flow should be satisfied. The resistance value is extracted so as to match.
At this time, it is assumed that the collector resistance RC, which is a model parameter of the main transistor Tr10, is changed to “0” and replaced with the external collector resistance RCX.
[0040]
Next, in the graph of FIG. 11, the external base resistance RBX is extracted from the gradient of the characteristic line in the region where the substrate current Isub has flown by a certain amount and the operation is saturated. At this time, the base resistance RB, which is a model parameter of the main transistor Tr10, is changed as follows in consideration of the addition of the external base resistance RBX. That is, the base resistance set in (1) is set as RB0, and the changed base resistance is set as RB, and the base resistance is changed as in the following equation (4).
RB = RB0−RBX (4)
[0041]
FIG. 12 is a graph showing a comparison between a simulation result and an actually measured value of the characteristic of the NPN bipolar transistor Q2 having the vertical structure. 8A illustrates a simulation performed as the sub-circuit in FIG. 8, and FIG. 8B illustrates a simulation performed as a single element model.
As shown in FIG. 12B, when the NPN bipolar transistor Q2 is represented by a single element model and simulated, no matter how the model parameters are set, the effect of the parasitic transistor is not considered. Although the substrate current Isub flowing in the saturation region cannot be simulated, the characteristic of the substrate current Isub flowing in the saturation region can be obtained by adding the action of the parasitic transistor Tr11 as a sub-circuit as shown in FIG. It can be seen that can be approximated to the measured value.
[0042]
Next, a flow of operations from the development to the manufacture of the power IC including the above-described simulation process will be described.
FIG. 13 shows a flowchart from development to manufacturing of the power IC.
When a power IC is developed, first, the process starts from a system design process S1 for performing functional design and logic design of the power IC, and then proceeds to a circuit design process S2 when the system design is completed. In parallel with the system design, a process design (process S4) is performed to determine what kind of semiconductor manufacturing process is used in the manufacturing process. Then, various elements are actually formed in the determined semiconductor manufacturing process, the characteristics thereof are measured, and model parameters used in the simulation are extracted (step S5). In the model parameter extraction step S5, the lateral structure PNP bipolar transistor Q1 and the vertical structure NPN bipolar transistor Q2 are represented as sub-circuits as described above, and the model parameters are extracted.
[0043]
In the circuit design process S2, in the field of power IC, a low voltage of a logic control system or a high voltage for power control is input, and an analog circuit is also included. Cannot be automatically completed, and the circuit verification in the simulation step S3 is appropriately performed so as to satisfy various requirements as to whether there is any problem in the operating characteristics of the circuit, the breakdown voltage of each element, the amount of leak current, and the like. The circuit design is advanced while doing so. In the simulation step S3, elements such as the lateral structure PNP bipolar transistor Q1 and the vertical structure NPN bipolar transistor Q2 in the design circuit data are set so as to be replaced as the above-described sub-circuits.
When the circuit design is completed, the layout of the elements to be formed on the semiconductor wafer and the wiring layout are designed (step S6), the semiconductor chip on which the design circuit is formed is prototyped (step S7), and the characteristics of the semiconductor chip are evaluated (step S7). S8) is performed in order.
[0044]
Further, when the chip area and the arrangement of the input / output pads are determined in the layout design, the packaging design of the IC (step S9) is performed in parallel with the trial manufacture of the semiconductor chip (step S7) and the characteristic evaluation (step S8). A radiator plate for cooling the semiconductor chip is provided in the packaging of the power IC, and the radiator plate is also designed in the packaging design (step S9). Since the amount of heat generated by the semiconductor chip is greatly related to the leakage current to the substrate, the design of the heat sink can be performed by referring to the leakage current characteristics verified in the previous simulation step S3.
When the packaging design is completed, a prototype including packaging (step S10) and characteristic evaluation (step S11) are performed, and when desired characteristics are obtained, the design contents obtained in the above steps are followed. It is shifted to the manufacturing process.
[0045]
As described above, according to the simulation method described in the above embodiment, even if an element model provided in a circuit simulator cannot accurately represent necessary characteristics, this element is regarded as a circuit block. The simulation can be performed by properly expressing necessary characteristics as appropriate. Further, in this case, since only one element is handled as a sub-circuit, unlike the case where an element model is added or changed, it is not necessary to modify a program of a circuit simulator or the like, and the operation can be easily performed at a user level. . Further, since most circuit simulators have a function of defining a sub-circuit, such operations can be performed without selecting a circuit simulator.
[0046]
Therefore, by using such a simulation method, the simulation accuracy at the circuit design stage can be improved, and the inaccuracies of repeating the trial production and design correction many times with low simulation accuracy are reduced. The total development time can be significantly reduced.
[0047]
In particular, in the development of a power IC that requires a heat dissipation design of a package in accordance with a substrate current mainly generated by an operation in a saturation region of a transistor, which greatly affects a heat generation amount of a semiconductor chip. Conventionally, the circuit model of the substrate current could not be verified by simulation because the device model provided in the circuit simulator could not accurately represent the characteristics in the saturation region of a bipolar transistor or the like. According to the method, the circuit verification of the substrate current can be performed with sufficient accuracy, so that the total development period including the packaging design and the heat radiation design can be significantly reduced.
[0048]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the spirit of the invention. Nor.
For example, the bipolar transistors Q1 and Q2 accompanied by a parasitic transistor have been exemplified as elements that can exhibit accurate characteristics by being redefined as a sub-circuit. By applying the same method to various elements that cannot express accurate characteristics in the element model, accurate characteristics can be expressed.
[0049]
FIG. 14 is a longitudinal sectional view showing an element structure of an LD (Laterally diffused) MOSFET as an example of a preferable element to which the same method is applied. FIG. 15 shows a case where this LD-MOSFET is defined as a sub-circuit. FIG. The LD-MOSFET Q3 in FIG. 14 is formed with a p-type back gate region BGA and an n-type source region SA on the surface of an n-type well region WN, and is formed relatively thick for the purpose of insulating between individual elements. An oxide film LS identical to the field oxide film is provided between the gate layer PS and the high-concentration n-type drain region DA.
[0050]
If the simulation device does not have an element model corresponding to the LD-MOSFET Q3 having the structure of FIG. 14, the main MOS transistor M0, the drain terminal D, and the gate terminal mainly exhibiting the original characteristics as shown in FIG. A sub-circuit consisting of a depletion type load MOS transistor M1 attached between G is defined, and this sub-circuit is treated as a model of the LD-MOSFET Q3 by the simulation device, so that a circuit including the LD-MOSFET Q3 is formed. An accurate simulation can be performed.
[0051]
The method of extracting the model parameters of each element constituting the sub-circuit is not limited to the method described in the above embodiment. If the characteristic that needs to be accurately represented by the simulation changes, the parameter extraction method may be appropriately changed. We can respond to that.
[0052]
In the above description, the invention made by the present inventor has been mainly described with respect to the development of a power IC which is a utilization field as a background, but the invention is not limited thereto, and is widely used in the development of various semiconductor integrated circuits. Can be used.
[0053]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
That is, according to the present invention, even when the required characteristics cannot be accurately represented by the element model provided in the simulation apparatus, a highly accurate simulation can be easily performed by representing the elements as circuit blocks. effective.
In addition, the high-precision simulation has an effect that the development and manufacturing period of a semiconductor integrated circuit, particularly, a power IC can be significantly reduced.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a circuit simulator used in a development stage of a semiconductor integrated circuit according to an embodiment.
FIG. 2 is a longitudinal sectional view showing a lateral structure PNP bipolar transistor treated as a circuit block in an embodiment of the present invention.
FIG. 3 is a diagram showing a circuit configuration of a sub-circuit defined as the bipolar transistor in FIG. 2;
FIG. 4 is a graph showing a measurement result of a base-emitter voltage Vbe-a forward substrate current ISub in the bipolar transistor of FIG. 2;
5 is a graph showing a measurement result of a base-substrate voltage Vbs-base-substrate capacitance Cbs in the bipolar transistor of FIG. 2;
6A is a graph showing a comparison between a simulation result and a measured value when a lateral structure PNP bipolar transistor is treated as a sub-circuit, and FIG. 6B is a graph using a standard device model; 9 is a graph showing a comparison between a simulation result and an actually measured value in the case.
FIG. 7 is a longitudinal sectional view showing an element structure of an NPN bipolar transistor having a vertical structure, which is a second example of an element treated as a circuit block.
8 is a diagram showing a circuit configuration of a sub-circuit defined as the bipolar transistor in FIG.
9 is a graph showing a measurement result of a base-collector voltage Vbc-substrate current Isub in the bipolar transistor of FIG. 7;
FIG. 10 is a graph showing a calculation result of a base current Ib_int of the main transistor Tr10 of FIG.
11 is a graph showing measurement results of base-emitter voltage Vbe-base current Ib and substrate current Isub in the bipolar transistor of FIG.
FIG. 12A is a graph showing a comparison between a simulation result and a measured value when a vertical NPN bipolar transistor is treated as a sub-circuit, and FIG. 6B shows a standard element model. 9 is a graph showing a comparison between a simulation result and an actually measured value in the case.
FIG. 13 is a flowchart showing a work flow from development to manufacturing of the power IC.
FIG. 14 is an element structure diagram showing another example of an element capable of performing an accurate simulation by treating it as a circuit block.
FIG. 15 is a diagram showing a circuit configuration of a sub-circuit defined as an element in FIG.
[Explanation of symbols]
10. Circuit simulator
F1 Circuit description data file
F2 control information file
F3 model information file
Q1 Lateral structure PNP bipolar transistor
Tr0 main transistor
Tr1, Tr2 parasitic transistor
Q2 Vertical structure NPN bipolar transistor
Tr10 main transistor
Tr11 parasitic transistor
RCX External collector resistance
RBX external base resistance

Claims (5)

A semiconductor integrated circuit development method for developing a semiconductor integrated circuit by performing circuit design and simulation of the designed circuit,
In the process of the above simulation,
A specific element constituting the design circuit is regarded as a circuit block in which a plurality of elements are connected, and the circuit block is defined by a circuit block definition function of a simulation device, and is substituted for the specific element. A method for developing a semiconductor integrated circuit, comprising performing a simulation. The simulation device has an element model formula representing the characteristics of each element for each of the plurality of types of elements, and is configured to perform circuit simulation according to the element model equation.
2. The method according to claim 1, wherein the circuit block defined for the specific element is represented by a circuit in which a plurality of elements each of which defines the element model formula are connected. . The device model formula includes user-configurable parameters for adjusting device characteristics,
The parameters relating to the plurality of elements constituting the circuit block are handled in association with the characteristics of the specific element defined in the circuit block, and the values of the parameters are set based on the characteristic values of the specific element. 3. The method for developing a semiconductor integrated circuit according to claim 2, wherein the simulation is performed. 4. The method according to claim 1, wherein when the specific element has a parasitic element, the specific element is treated as a circuit block in which the element itself and the parasitic element are combined as constituent elements. 3. A method for developing a semiconductor integrated circuit according to claim 1. After performing circuit design, simulation, and packaging design by the method for developing a semiconductor integrated circuit according to any one of claims 1 to 4, a semiconductor integrated circuit is manufactured using data obtained by these designs. A method for producing a semiconductor integrated circuit.

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