JP2004070300A - Shift register and image display device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a shift register that operates normally even if the amplitude of a clock signal is small, and has a small amount of power consumption. <P>SOLUTION: A level shifter 13 for boosting the voltage of the clock signal CK is provided for each SR flip-flop F1 for composing the shift register 11. As a result, after the voltage of the clock signal is boosted by only one level shifter, the transmission distance of the boosted clock signal can be reduced as compared with the transmission to each flip-flop, and hence a load capacity in the level shifter 13 can be reduced. Additionally, each level shifter 13 operates while the level shifter 13 at the first stage is outputting a pulse and stops the operation when the pulse output is completed, thus achieving operation only when supplying the clock signal CK to the corresponding to SR flip-flop F1 is required. Therefore, the power consumption in the shift register operating normally can be reduced even if the amplitude of the clock signal is small. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, a shift register suitably used for a drive circuit of an image display device and the like and capable of shifting an input pulse even when the amplitude of a clock signal is lower than a drive voltage, and an image display device using the same. Things.
[0002]
[Prior art]
For example, in a data signal line driving circuit or a scanning signal line driving circuit of an image display device, in order to take timing when sampling each data signal from a video signal or to generate a scanning signal to be applied to each scanning signal line, , Shift registers are widely used.
[0003]
On the other hand, the power consumption of the electronic circuit increases in proportion to the frequency, the load capacity, and the square of the voltage. Therefore, for example, in a circuit connected to the image display device, such as a circuit for generating a video signal to the image display device, or in the image display device, in order to reduce power consumption, the drive voltage tends to be set lower and lower. is there.
[0004]
For example, in a circuit in which a polycrystalline silicon thin film transistor is used to secure a large display area, such as a pixel, a data signal line driver circuit, or a scanning signal line driver circuit, the circuit can be performed between substrates or within the same substrate. Since the difference in the threshold voltage may reach, for example, about several volts, it is difficult to say that the drive voltage has been sufficiently reduced. In a circuit using a crystal silicon transistor, the drive voltage is often set to, for example, 5 [V], 3.3 [V], or a value lower than that. Therefore, when a clock signal lower than the drive voltage of the shift register is applied, the shift register is provided with a level shifter that boosts the clock signal.
[0005]
Specifically, for example, as shown in FIG. 39, when a clock signal CK having an amplitude of, for example, about 5 [V] is applied to the conventional shift register 101, the level shifter 103 drives the shift register 101 (15 [V]), the clock signal CK is boosted. The boosted clock signal CK is applied to each of the flip-flops F1 to Fn, and the shift register unit 102 shifts the start signal SP in synchronization with the clock signal CK.
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional shift register 101, the clock signal CK is level-shifted and then transmitted to the flip-flops F1 to Fn. Therefore, as the distance between both ends of the flip-flops F1 to Fn increases, the transmission distance increases. This causes a problem that power consumption increases.
[0007]
Specifically, as the transmission distance increases, the capacity of the signal line for transmission increases, so that the level shifter 103 needs to have a larger driving capability and the power consumption increases. Further, when the driving capability of the level shifter 103 is not sufficient, as in the case where the driving circuit including the level shifter 103 is formed using a polycrystalline silicon thin film transistor, a waveform without distortion is transmitted. As shown by the broken line, since it is necessary to provide the buffer 104 between the level shifter 103 and each of the flip-flops F1 to Fn, more power is required.
[0008]
In recent years, there has been a demand for an image display device having a wider display screen and higher resolution, and thus the number of stages of the shift register unit 102 tends to increase more and more. Therefore, there is a strong demand for a shift register and an image display device that consume less power even when the distance between both ends of the flip-flops F1 to Fn increases.
[0009]
The present invention has been made in view of the above problems, and has as its object to operate normally even when the amplitude of the clock signal is lower than the drive voltage, and to reduce the power consumption of the shift register. An object of the present invention is to realize an image display device using the same.
[0010]
[Means for Solving the Problems]
In order to solve the above problem, a shift register according to the present invention includes a plurality of flip-flops that operate in synchronization with a clock signal, and boosts a clock signal whose amplitude is smaller than a drive voltage of the flip-flop to increase A shift register having a level shifter applied to a flip-flop and transmitting an input pulse in synchronization with the clock signal, wherein each flip-flop is divided into a plurality of blocks each including at least one flip-flop; , At least one of the plurality of level shifters corresponding to a block that does not require the input of the clock signal for transmission of the input pulse at that time is stopped. And each of the above level shifters has an output stabilizing means. It is characterized by a door.
[0011]
That is, each of the flip-flops is divided into a plurality of blocks each including at least one flip-flop. The level shifter is provided for each of the blocks. At least one of the level shifters corresponding to the blocks that do not require the input of the clock signal for transmission of the clock signal is stopped.
[0012]
Whether or not each block requires a clock signal to transmit an input pulse is determined by a flip-flop constituting a shift register. For example, when a set / reset flip-flop that is set in response to a clock signal is used as the flip-flop, the block is configured to operate after the pulse is input to the block until the last-stage flip-flop is set. In the case where the flip-flop is a D flip-flop, a clock signal is required from when a pulse is input to the block until the last stage flip-flop finishes pulse output. . In any case, one flip-flop is included in each block, and a level shifter may be provided for each flip-flop, or a level shifter may be provided for each of a plurality of flip-flops. Good.
[0013]
In the above configuration, after the clock signal is boosted by any of the plurality of level shifters, the clock signal is applied to a flip-flop in a block corresponding to the level shifter, and the input pulse is sequentially transmitted in synchronization with the boosted clock signal. Is done. In addition, at least one of the level shifters that do not need to output the clock signal stops operating.
[0014]
Here, a block that does not require a clock signal includes, for example, a block that does not transmit an input pulse. Further, even in a block transmitting an input pulse, for example, in the case of a set / reset flip-flop in which a flip-flop is set according to a clock signal and reset according to an output of a later-stage flip-flop, Does not require a clock signal during the period after the last flip-flop is set.
[0015]
In the above configuration, since a plurality of level shifters are provided in the shift register, the distance from the level shifter to the flip-flop can be reduced as compared with the case where only one level shifter applies the clock signal after the level shift to all flip-flops. . As a result, the transmission distance of the clock signal after the level shift can be shortened, so that the load capacity of the level shifter can be reduced and the driving capability required for the level shifter can be suppressed. Thus, for example, even when the driving capability of the level shifter is small and the distance between both ends of the flip-flop is long, it is not necessary to provide a buffer between the level shifter and the flip-flop, and the power consumption of the shift register is reduced. Can be reduced. In addition, since the operation of at least one of the plurality of level shifters is stopped, the power consumption of the shift register can be reduced as compared with the case where all the level shifters operate simultaneously. As a result, a shift register which can operate with a low-voltage clock signal input and consumes low power can be realized.
[0016]
By the way, if the output voltage of the level shifter becomes unstable while the operation of the level shifter is stopped, the operation of the flip-flop connected to the level shifter may be unstable.
[0017]
Since each of the level shifters has a configuration including output stabilizing means, according to the configuration, while the level shifter is stopped, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means. As a result, a malfunction of the flip-flop due to an undefined output voltage can be prevented, and a more stable shift register can be realized.
[0018]
In order to solve the above problem, the shift register according to the present invention, in the shift register having the above configuration, further comprises: the level shifter is provided between a clock signal line through which the clock signal is transmitted and the level shift unit. And a switch that is opened while the level shifter is stopped is provided.
[0019]
In the above configuration, unlike the case where all the level shifters are constantly connected to the clock signal line and the input switching elements of all the level shift units load the clock signal line, the input switching elements connected to the clock signal line operate. Limited to medium level shifters. Further, even when the switch is opened during the stop and the input of the level shifter becomes unstable, the output of the level shifter is maintained at a predetermined value by the output stabilizing means, so that the flip-flop does not malfunction. As a result, the load capacity of the clock signal line can be reduced, and the power consumption of a circuit for driving the clock signal line can be reduced.
[0020]
Further, another shift register may have the following configuration.
[0021]
For example, as another shift register, a plurality of flip-flops that operate in synchronization with a clock signal, and a level shifter that boosts a clock signal whose amplitude is smaller than the drive voltage of the flip-flop and applies the boosted clock signal to each of the flip-flops is used. The shift register having the above and transmitting the input pulse in synchronization with the clock signal may be a shift register employing the following means.
[0022]
That is, each of the flip-flops is divided into a plurality of blocks each including at least one flip-flop. The level shifter is provided for each of the blocks. At least one of the level shifters corresponding to the blocks that do not require the input of the clock signal for transmission of the clock signal is stopped.
[0023]
Whether or not each block requires a clock signal to transmit an input pulse is determined by a flip-flop constituting a shift register. For example, when a set / reset flip-flop that is set in response to a clock signal is used as the flip-flop, the block is configured to operate after the pulse is input to the block until the last-stage flip-flop is set. In the case where the flip-flop is a D flip-flop, a clock signal is required from when a pulse is input to the block until the last stage flip-flop finishes pulse output. . In any case, one flip-flop is included in each block and a level shifter may be provided for each flip-flop, or a level shifter may be provided for each of a plurality of flip-flops. Good.
[0024]
In the above configuration, after the clock signal is boosted by any of the plurality of level shifters, the clock signal is applied to a flip-flop in a block corresponding to the level shifter, and the input pulse is sequentially transmitted in synchronization with the boosted clock signal. Is done. In addition, at least one of the level shifters that do not need to output the clock signal stops operating.
[0025]
Here, a block that does not require a clock signal includes, for example, a block that does not transmit an input pulse. Further, even in a block transmitting an input pulse, for example, in the case of a set / reset flip-flop in which a flip-flop is set according to a clock signal and reset according to an output of a later-stage flip-flop, Does not require a clock signal during the period after the last flip-flop is set.
[0026]
In the above configuration, since a plurality of level shifters are provided in the shift register, the distance from the level shifter to the flip-flop can be reduced as compared with the case where only one level shifter applies the clock signal after the level shift to all flip-flops. . As a result, the transmission distance of the clock signal after the level shift can be shortened, so that the load capacity of the level shifter can be reduced and the driving capability required for the level shifter can be suppressed. Thus, for example, even when the driving capability of the level shifter is small and the distance between both ends of the flip-flop is long, it is not necessary to provide a buffer between the level shifter and the flip-flop, and the power consumption of the shift register is reduced. Can be reduced. In addition, since the operation of at least one of the plurality of level shifters is stopped, the power consumption of the shift register can be reduced as compared with the case where all the level shifters operate simultaneously. As a result, a shift register which can operate with a low-voltage clock signal input and consumes low power can be realized.
[0027]
Further, another shift register having the above configuration is not limited to a case including a set / reset flip-flop as a flip-flop, and is applicable to a case where a specific block among the blocks includes a D flip-flop as the flip-flop. In this case, the specific level shifter corresponding to the specific block starts operating when the pulse input to the specific block is started, and starts operating after the flip-flop at the last stage of the specific block finishes the pulse output. It is preferable to stop.
[0028]
According to the configuration, since the specific block includes the D flip-flop as the flip-flop, unlike the case of the set / reset flip-flop, the specific block has a case where the pulse width (the number of clocks) of the input pulse changes. However, the input pulse can be transmitted without any trouble. Further, according to the above configuration, the specific level shifter supplies the clock signal after the level shift during a period required when the D flip-flop of the specific block operates, and the input of the clock signal to the D flip-flop is unnecessary. If so, stop the operation. As a result, a shift register that can transmit input pulses having different pulse widths and consumes less power can be realized.
[0029]
In addition, the period from when a pulse is input to a specific block to when the last-stage flip-flop outputs a pulse is, for example, a logical sum of a pulse signal input to the specific block and an output signal of the flip-flop of each stage. , Or by latching a trigger signal. Therefore, in this case, the circuit configuration of the shift register can be more simplified than when the operation period is calculated separately from the input / output of the flip-flop.
[0030]
In another shift register having the above configuration, when there are a plurality of the flip-flops in the specific block, the specific level shifter outputs a signal input to the specific block and an output of a last-stage flip-flop of the specific block. A latch circuit that changes the output according to the signal may be included.
[0031]
Further, in another shift register having the above configuration, the level shifter may include a current-driven type level shift unit in which an input switching element to which the clock signal is applied is always conductive during operation.
[0032]
According to this configuration, while the level shifter is operating, the input switching element of the level shifter is always conductive. Therefore, unlike a voltage-driven level shifter that turns on / off an input switching element according to the level of a clock signal, there is no problem even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element. The clock signal can be level shifted.
[0033]
Furthermore, the current-driven level shifter consumes more power than the voltage-driven level shifter during operation because the input switching element is conducting, but at least one of the plurality of level shifters stops operating. . This makes it possible to realize a shift register that can perform level shift even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element, and consumes less power than when all the level shifters operate simultaneously.
[0034]
In another shift register having the above configuration, an input signal control unit that stops the level shifter by providing a signal having a level cut off by the input switching element as an input signal to the level shift unit is provided. Is also good.
[0035]
According to this configuration, as an example, a case where the input switching element is a MOS transistor will be described. For example, when an input signal is applied to a gate, an input signal of a level that cuts off between a drain and a source is applied. When applied to the gate, the input switching element is shut off. When the input signal is applied to the source, the input switching element is cut off, for example, by applying substantially the same input signal as the drain.
[0036]
In either configuration, if the input signal control unit controls the level of the input signal and shuts off the input switching element, the current-driven level shifter stops operating. Thus, the input signal control unit can stop the level shifter, and can reduce power consumption by the amount of current flowing to the input switching element during operation during the stop.
[0037]
On the other hand, another shift register of each of the above configurations may include a power supply control unit that stops power supply to the level shift unit and stops the level shifter.
[0038]
According to this configuration, the power supply control unit stops supplying power to each level shift unit, and stops the level shifter. Accordingly, the power supply control unit can stop the level shifter, and can reduce power consumption by the amount of power consumed by the level shifter during operation while the operation is stopped.
[0039]
By the way, if the output voltage of the level shifter becomes unstable while the operation of the level shifter is stopped, the operation of the flip-flop connected to the level shifter may be unstable.
[0040]
Therefore, in the other shift register of each configuration described above, it is preferable that the level shifter includes an output stabilizing means for maintaining the output voltage at a predetermined value when the level shifter is stopped.
[0041]
According to this configuration, while the level shifter is stopped, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means. As a result, a malfunction of the flip-flop due to an undefined output voltage can be prevented, and a more stable shift register can be realized.
[0042]
Further, another shift register of each of the above-described configurations includes a switch disposed between the clock signal line through which the clock signal is transmitted and the level shift unit, and opened while the level shifter is stopped. It is preferable to be provided. The switch can be realized as a part of the input signal control unit.
[0043]
In the above configuration, unlike the case where all the level shifters are constantly connected to the clock signal line and the input switching elements of all the level shift units load the clock signal line, the input switching elements connected to the clock signal line operate. Limited to medium level shifters. Further, even when the switch is opened during the stop and the input of the level shifter becomes unstable, the output of the level shifter is maintained at a predetermined value by the output stabilizing means, so that the flip-flop does not malfunction. As a result, the load capacity of the clock signal line can be reduced, and the power consumption of a circuit for driving the clock signal line can be reduced.
[0044]
On the other hand, an image display device according to the present invention has a plurality of pixels arranged in a matrix, a plurality of data signal lines arranged in each row of each pixel, and A plurality of scanning signal lines arranged in each column, and a scanning signal line driving circuit for sequentially applying scanning signals of mutually different timings to each of the scanning signal lines in synchronization with a first clock signal having a predetermined period; A data signal to each pixel of a scanning signal line to which the scanning signal is applied is converted from a video signal which is sequentially applied in synchronization with a second clock signal having a predetermined cycle and which indicates a display state of each pixel. A data signal line drive circuit for extracting and outputting the data signal line to each of the data signal lines, wherein at least one of the data signal line drive circuit and the scan signal line drive circuit includes the first or the second signal line drive circuit. The clock signal is characterized in that it comprises a shift register of any of the above-described configuration according to the clock signal.
[0045]
Further, any of the other shift registers may be provided as the shift register.
[0046]
Here, in the image display device, as the number of data signal lines or the number of scanning signal lines increases, the number of flip-flops for generating the timing for each signal line increases, and the Becomes longer. However, the shift register of each configuration described above can reduce the number of buffers and power consumption even when the driving capability of the level shifter is small and the distance between both ends of the flip-flop is long.
[0047]
Therefore, by providing at least one of the data signal line driving circuit and the scanning signal line driving circuit with the shift register having the above-described configuration, an image display device with low power consumption can be realized.
[0048]
Further, in the image display device having the above configuration, it is preferable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate.
[0049]
According to this configuration, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate, and the wiring between the data signal line driving circuit and each pixel, and the scanning The wiring between the signal line driving circuit and each pixel is provided on the substrate, and does not need to be out of the substrate. As a result, even if the number of data signal lines and the number of scanning signal lines increase, the number of signal lines extending out of the substrate does not change, thereby reducing the time and labor required for assembly. Further, since it is not necessary to provide a terminal for connecting each signal line to the outside of the substrate, it is possible to prevent an undesired increase in the capacitance of each signal line and to prevent a decrease in the degree of integration.
[0050]
By the way, a polycrystalline silicon thin film can easily increase the substrate area as compared with single crystal silicon, while a polycrystalline silicon transistor has, for example, transistor characteristics such as mobility and threshold value which are different from single crystal silicon transistors. Is inferior. Therefore, when each circuit is manufactured using a single crystal silicon transistor, it is difficult to increase the display area, and when each circuit is manufactured using a polycrystalline silicon thin film transistor, the driving capability of each circuit is reduced. If both the driving circuits and the pixels are formed on different substrates, it is necessary to connect the two substrates with each signal line, which is troublesome at the time of manufacturing and increases the capacitance of each signal line. .
[0051]
Therefore, in the image display device of each configuration described above, it is preferable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element formed of a polycrystalline silicon thin film transistor.
[0052]
In this configuration, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel each include a switching element formed of a polycrystalline silicon thin film transistor, so that the display area can be easily enlarged. Furthermore, since it can be easily formed on the same substrate, the labor and the capacity of each signal line at the time of manufacturing can be reduced. In addition, since the shift register having the above-described configuration is used, the clock signal after the level shift can be applied to each flip-flop without any problem even when the driving capability of the level shifter is low. As a result, an image display device with low power consumption and a large display area can be realized.
[0053]
In addition, in the image display device of each configuration described above, it is preferable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element manufactured at a process temperature of 600 degrees or less.
[0054]
According to this configuration, since the process temperature of the switching elements is set to 600 ° C. or less, even if a normal glass substrate (a glass substrate having a strain point of 600 ° C. or less) is used as the substrate of each switching element, No warping or warping due to the above process. As a result, an image display device which is easier to mount and has a larger display area can be realized.
[0055]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
One embodiment of the present invention will be described below with reference to FIGS. Note that the present invention can be widely applied to a shift register in which an amplitude of an input clock signal is smaller than a driving voltage. Hereinafter, a case where the present invention is applied to an image display device will be described as a preferable example.
[0056]
That is, as shown in FIG. 2, the image display device 1 according to the present embodiment includes a display unit 2 having pixels PIX arranged in a matrix, a data signal line driving circuit 3 for driving each pixel PIX, and a scanning signal. When the control circuit 5 generates a video signal DAT indicating the display state of each pixel PIX, an image can be displayed based on the video signal DAT.
[0057]
The display unit 2 and the two driving circuits 3 and 4 are provided on the same substrate in order to reduce the labor and the wiring capacity at the time of manufacturing. Further, in order to integrate a larger number of pixels PIX and increase the display area, each of the circuits 2 to 4 is formed of a polycrystalline silicon thin film transistor formed on a glass substrate. Further, even when a normal glass substrate (a glass substrate having a strain point of 600 ° or less) is used, the polycrystalline thin film silicon transistor is formed at a temperature of 600 ° or less so that warpage or warpage caused by a process at or above the strain point does not occur. It is manufactured at a process temperature of
[0058]
Here, the display unit 2 includes l (L: in the following, uppercase L is used for convenience of reference) data signal lines SL1 to SLL and m data signal lines SL1 to SLL intersecting with the data signal lines SL1 to SLL, respectively. Scanning signal lines GL1 to GLm. If any positive integer less than L is i and any positive integer less than m is j, a pixel PIX (i, j) is provided for each combination of the data signal line SLi and the scanning signal line GLj, Each pixel PIX (i, j) is arranged in a portion surrounded by two adjacent data signal lines SLi and SLi + 1 and two adjacent scanning signal lines GLj and GLj + 1.
[0059]
On the other hand, the pixel PIX (i, j) includes, for example, a field effect transistor (switching element) SW having a gate connected to the scanning signal line GLj and a drain connected to the data signal line SLi, as shown in FIG. The source of the field effect transistor SW is provided with a pixel capacitor CP to which one electrode is connected. The other end of the pixel capacitor CP is connected to a common electrode line common to all the pixels PIX. The pixel capacitance CP includes a liquid crystal capacitance CL and an auxiliary capacitance CS added as needed.
[0060]
When the scanning signal line GLj is selected in the pixel PIX (i, j), the field effect transistor SW is turned on, and the voltage applied to the data signal line SLi is applied to the pixel capacitance CP. On the other hand, while the selection period of the scanning signal line GLj ends and the field effect transistor SW is shut off, the pixel capacitance CP keeps holding the voltage at the time of shutting off. Here, the transmittance or the reflectance of the liquid crystal changes according to the voltage applied to the liquid crystal capacitance CL. Therefore, if the scanning signal line GLj is selected and a voltage corresponding to the video data is applied to the data signal line SLi, the display state of the pixel PIX (i, j) can be changed in accordance with the video data.
[0061]
In the image display device 1 shown in FIG. 2, the scanning signal line driving circuit 4 selects the scanning signal line GL, and the video data to the pixel PIX corresponding to the selected combination of the scanning signal line GL and the data signal line SL is displayed. Are output to the respective data signal lines SL by the data signal line drive circuit 3. Thereby, the respective video data is written to the pixels PIX... Connected to the scanning signal line GL. Further, the scanning signal line driving circuit 4 sequentially selects the scanning signal lines GL, and the data signal line driving circuit 3 outputs video data to each data signal line SL. As a result, the respective video data is written to all the pixels PIX of the display unit 2.
[0062]
Here, between the control circuit 5 and the data signal line driving circuit 3, video data to each pixel PIX is transmitted as a video signal DAT in a time-division manner, and the data signal line driving circuit 3 Each video data is extracted from the video signal DAT at a timing based on the clock signal CKS having a predetermined cycle and the start signal SPS.
[0063]
Specifically, the data signal line drive circuit 3 sequentially shifts the start signal SPS in synchronization with the clock signal CKS, thereby generating the output signals S1 to SL having different timings at predetermined intervals. And a sampling unit 3b that samples the video signal DAT at the timings indicated by the output signals S1 to SL and extracts video data to be output to the data signal lines SL1 to SLL from the video signal DAT. Similarly, the scanning signal line driving circuit 4 sequentially outputs the scanning signals having different timings at predetermined intervals to the respective scanning signal lines GL1 to GLm by sequentially shifting the start signal SPG in synchronization with the clock signal CKG. A shift register 4a is provided.
[0064]
Here, in the image display device 1 according to the present embodiment, the display unit 2 and both the driving circuits 3 and 4 are formed of polycrystalline silicon thin film transistors, and the driving voltage VCC of these circuits 2 to 4 is, for example, 15 [V] is set. On the other hand, the control circuit 5 is formed of a single crystal silicon transistor on a substrate different from each of the circuits 2 to 4, and the driving voltage is, for example, 5 [V] or lower. It is set to a value lower than the voltage VCC. Although the circuits 2 to 4 and the control circuit 5 are formed on different substrates, the number of signals transmitted between them is larger than the number of signals between the circuits 2 to 4. For example, the video signal DAT, the start signal SPS (SPG), or the clock signal CKS (CKG) is substantially smaller. Further, since the control circuit 5 is formed of a single-crystal silicon transistor, it is easy to secure a sufficient driving capability. Therefore, even if they are formed on different substrates, an increase in the labor and the wiring capacity or the power consumption at the time of manufacturing is suppressed to a level that does not cause a problem.
[0065]
Here, in this embodiment, the shift register 11 shown in FIG. 1 is used as at least one of the shift registers 3a and 4a. In the following, each of the start signals SPS (SPG) is referred to as SP, the number L (m) of stages of the shift register 1 is referred to by n, and the output signal is represented by S1 so as to include the case where any of the shift registers is used. To Sn.
[0066]
Specifically, the shift register 11 includes an n-stage set / reset flip-flop (SR flip-flop) F1 (1)..., The flip-flop unit 12 operating at the drive voltage VCC, and the control circuit 5 includes a level shifter 13 (1) which boosts a clock signal CK having an amplitude smaller than the drive voltage VCC and applies the boosted clock signal CK to each SR flip-flop F1 (1).
[0067]
In the present embodiment, the level shifters 13 (1) are provided so as to correspond to the SR flip-flops F1 (1) on a one-to-one basis. It is configured as a current-driven level shifter so that the voltage can be boosted without any problem even when the voltage is lower than the voltage VCC. When i is an integer equal to or less than n and equal to or greater than 1, each level shifter 13 (i) responds based on the clock signal CK and its inverted signal CK bar while the control signal ENAi instructs the operation. The boosted clock signal CKi can be applied to the SR flip-flop F1 (i). Further, while the control signal ENA instructs the stop of the operation, the operation can be stopped, and the application of the clock signal CKi to the corresponding SR flip-flop F1 (i) can be prevented. By shutting off the element, the power consumption of the level shifter 13 (i) due to the through current can be reduced.
[0068]
On the other hand, the flip-flop unit 12 is configured to transmit a start signal SP having one clock cycle width to the next stage at each edge (rising and falling) of the clock signal CK. Specifically, the output of each level shifter 13 (i) is applied to the SR flip-flop F1 (i) as a negative logic set signal S via the inverter I1 (i). The output Q of each SR flip-flop F1 (i) is output as the output Si of the shift register 11 and is also applied as a control signal ENAi + 1 to the next-stage level shifter 13 (i + 1). The start signal SP from the control circuit 5 shown in FIG. 1 is applied as the control signal ENA1 to the level shifter 13 (1) at the first stage after being boosted. Further, to each SR flip-flop F1 (i), a signal delayed by the pulse width of a pulse to be transmitted among reset signals to the subsequent SR flip-flop F1 is applied as a reset signal R. In this embodiment, since a pulse having one clock cycle width is transmitted, a signal delayed by one clock cycle, that is, a clock signal CK (i + 2) to the SR flip-flop F1 (i + 2) two stages later is reset to a positive logic. Applied as a signal.
[0069]
Also, the odd-numbered level shifters 13 (1)... Receive the non-inverted input of the clock signal CK so that the odd-numbered SR flip-flops F1 (1), F1 (3). The inverted signal CK bar of the clock signal is applied to the inverted input terminal. Conversely, clock signals are applied to the even-numbered level shifters 13 (2), 13 (4),... So that the even-numbered SR flip-flops F1 (2). CK is applied to the inverting input terminal, and the inverted signal CK is applied to the non-inverting input terminal.
[0070]
According to the above configuration, as shown in FIG. 4, while the start signal SP is being pulse-inputted, the level shifter 13 (1) at the forefront stage operates to convert the boosted clock signal CK1 to the SR flip-flop F1 ( Apply to 1). Thus, the SR flip-flop F1 (1) is set when the clock signal CK first rises after the start of the pulse input, and changes the output S1 to the high level.
[0071]
The output S1 is applied to the second-stage level shifter 13 (2) as a control signal ENA2. Accordingly, the level shifter 13 (2) outputs the clock signal CK2 while the SR flip-flop F1 (1) outputs a pulse (while the control signal ENA2 = S1 is at a high level). However, since the clock signal CK is applied to the inverting input terminal of the level shifter 13 (2), the polarity of the clock signal CK is opposite to that of the clock signal CK, and the boosted signal is output as the clock signal CK2. I do. As a result, the SR flip-flop F1 (2) is set when the clock signal CK falls for the first time after the output S1 of the preceding stage has become high level, and changes the output S2 to high level.
[0072]
Since each output signal Si is applied as a control signal ENAi + 1 to the next-stage level shifter 13 (i + 1), the second and subsequent SR flip-flops F1 (2). The outputs S2... Are output with a delay of a half cycle of the signal CK.
[0073]
On the other hand, the output CKi + 2 of the level shifter 13 (i + 2) two stages later is applied as the reset signal R to the level shifter 13 (i) of each stage. Therefore, each output Si goes high for one clock cycle and then goes low. Thus, the flip-flop unit 12 can transmit the start signal SP having one clock cycle width to the next stage at each edge (rising and falling) of the clock signal CK.
[0074]
Here, since each level shifter 13 (i) is provided for each SR flip-flop F1 (i), even when the number of stages of the SR flip-flop F1 (i) is large, the clock signal CK is used by only one level shifter. After the voltage is boosted, the distance between the level shifter and the flip-flop corresponding to each other can be reduced as compared with the case where the voltage is applied to all the flip-flops. Therefore, the transmission distance of the boosted clock signal CKi can be shortened, and the load capacity of each level shifter 13 (i) can be reduced. Further, since the load capacitance is small, it is difficult to sufficiently secure the driving capability of the level shifter 13 (i), for example, when the level shifter 13 (i) is formed of a polycrystalline silicon thin film transistor. Also, there is no need to provide a buffer. As a result, power consumption of the shift register 11 can be reduced.
[0075]
Further, when each SR flip-flop F1 (i) does not require the input of the clock signal CKi, such as when the start signal SP and the output Si-1 of the preceding stage are at the low level, the level shifter 13 (i) operates. Has stopped. In this state, since the clock signal CKi is not driven, power consumption required for driving does not occur. Further, as described later, the power supply itself to the level shift unit 13a provided in each level shifter 13 (i) is stopped, the input switching element is shut off, and no through current flows. Therefore, power is consumed only by the operating level shifter 13 (i) despite the fact that a large number (n) of current-driven level shifters are provided. As a result, the power consumption of the shift register 11 can be significantly reduced.
[0076]
In addition, the level shifter 13 (i) according to the present embodiment performs the period during which the clock signal CKi is required for the SR flip-flop F1 (i), that is, the time when the start signal SP or the preceding stage output Si-1 starts pulse output. Is determined based on only the start signal SP or the output Si-1 of the preceding stage from the time until the SR flip-flop F1 (i) is set. As a result, the operation / stop of each level shifter 13 (i) can be controlled only by directly applying the start signal SP or the output Si-1 of the preceding stage, and compared with the case where a circuit for creating a new control signal is provided. , The circuit configuration of the shift register 11 can be simplified.
[0077]
Further, in the present embodiment, while each level shifter 13 (i) is stopped, clock input to each SR flip-flop F1 (i) is blocked. Therefore, the start signal SP can be transmitted correctly without providing a switch that conducts according to the necessity of clock input separately from the level shifter 13 (i).
[0078]
Here, in each of the SR flip-flops F1, for example, as shown in FIG. 5, a P-type MOS transistor P1 and N-type MOS transistors N2 and N3 are connected in series between the drive voltage VCC and the ground level. The negative polarity set signal S is applied to the gates of the transistors P1 and N3. Further, a positive logic reset signal R is applied to the gate of the transistor N2. Further, the drain potentials of the two transistors P1 and N2 connected to each other are inverted by inverters INV1 and INV2, respectively, and output as an output signal Q. On the other hand, between the drive voltage VCC and the ground level, there are further provided P-type MOS transistors P4 and P5 and N-type MOS transistors N6 and N7 connected in series. The drains of the transistors P5 and N6 are connected to the input of the inverter INV1, and the gates of the transistors P5 and N6 are connected to the output of the inverter INV1. Further, a reset signal R is applied to the transistor P4, and a set signal S is applied to the gate of the transistor N7.
[0079]
In the SR flip-flop F1, as shown in FIG. 6, when the set signal S changes to active (low level) while the reset signal R is inactive (low level), the transistor P1 conducts, The input of the inverter INV1 is changed to a high level. As a result, the output signal Q of the SR flip-flop F1 changes to a high level.
[0080]
In this state, the transistors P4 and P5 are turned on by the reset signal R and the output of the inverter INV1. Further, the transistors N2 and N6 are cut off by the reset signal R and the output of the inverter INV1. Thus, even if the set signal S changes to inactive, the input of the inverter INV1 is maintained at the high level, and the output signal Q is maintained at the high level.
[0081]
Thereafter, when the reset signal R becomes active, the transistor P4 is turned off and the transistor N2 is turned on. Here, since the set signal S remains inactive, the transistor P1 is turned off and the transistor N3 is turned on. Therefore, the input of the inverter INV1 is driven to low level, and the output signal Q changes to low level.
[0082]
On the other hand, for example, as shown in FIG. 7, the level shifter 13 according to the present embodiment includes a level shifter 13a for shifting the level of the clock signal CK, A power supply control unit 13b for interrupting the power supply of the power supply, an input control unit (switch) 13c for interrupting the level shift unit 13a and the signal line through which the clock signal CK is transmitted during the suspension period, and the above-described level during the suspension period. An input switching element cutoff control section (input signal control section) 13d for cutting off an input switching element of the shift section 13a, and an output stabilizing section (output stabilizing means) for maintaining an output of the level shift section 13a at a predetermined value during a stop period. 13e.
[0083]
The level shift unit 13a includes, as a differential input pair of an input stage, P-type MOS transistors P11 and P12 whose sources are connected to each other, and a constant current source Ic that supplies a predetermined current to the sources of the transistors P11 and P12. And N-type MOS transistors N13 and N14 forming a current mirror circuit and serving as active loads of both transistors P11 and P12, and CMOS transistors P15 and N16 for amplifying the output of the differential input pair. .
[0084]
A clock signal CK is input to the gate of the transistor P11 via a transistor N31 described later, and an inverted signal CK bar of the clock signal is input to a gate of the transistor P12 via a transistor N33 described later. The gates of the transistors N13 and N14 are connected to each other, and further connected to the drains of the transistors P11 and N13. On the other hand, the drains of the transistors P12 and N14 connected to each other are connected to the gates of the transistors P15 and N16. The sources of the transistors N13 and N14 are grounded via an N-type MOS transistor N21 as the power supply control unit 13b.
[0085]
On the other hand, in the input control section 13c on the transistor P11 side, an N-type MOS transistor N31 is provided between the clock signal CK and the gate of the transistor P11. In the input switching element cutoff controller 13d on the transistor P11 side, a P-type MOS transistor P32 is provided between the gate of the transistor P11 and the drive voltage VCC. Similarly, the inverted signal CK of the clock signal is applied to the gate of the transistor P12 via the transistor N33 as the input control unit 13c, and the driving voltage is applied via the transistor P34 as the input switching element cutoff control unit 13d. VCC is provided.
[0086]
The output stabilizing unit 13e is configured to stabilize the output voltage OUT of the level shifter 13 during the suspension period to the ground level. A P-type MOS is provided between the driving voltage VCC and the gates of the transistors P15 and N16. The transistor P41 is provided.
[0087]
In the present embodiment, the control signal ENA is set to indicate the operation of the level shifter 13 when it is at the high level. Therefore, the control signal ENA is applied to the gates of the transistors N21 to N41.
[0088]
In the level shifter 13 having the above configuration, when the control signal ENA indicates an operation (in a case of a high level), the transistors N21, N31, and N33 are turned on, and the transistors P32, P34, and P41 are turned off. In this state, the current of the constant current source Ic flows through the transistors P11 and N13 or the transistors P12 and N14, and further flows through the transistor N21. A clock signal CK or an inverted clock signal CK bar is applied to the gates of the transistors P11 and P12. As a result, a voltage flows through both transistors P11 and P12 according to the ratio of the respective gate-source voltages. On the other hand, since the transistors N13 and N14 work as active loads, the voltage at the connection point of the transistors P12 and N14 is a voltage corresponding to the difference between the voltage levels of both CK and CK. This voltage becomes the gate voltage of the CMOS transistors P15 and N16, is power-amplified by both transistors P15 and N16, and is output as the output voltage OUT.
[0089]
The level shifter 13 is configured to switch on / off of the transistors P11 and P12 in the input stage by the clock signal CK, that is, a current drive in which the transistors P11 and P12 in the input stage are always on during operation unlike the voltage drive type. The level of the clock signal CK is shifted by shunting the current of the constant current source Ic according to the ratio of the gate-source voltage of both transistors P11 and P12. Thus, even when the amplitude of the clock signal CK is lower than the threshold values of the transistors P11 and P12 in the input stage, the level of the clock signal CK can be shifted without any problem.
[0090]
As a result, as shown in FIG. 4, while the corresponding control signal ENAi is at a high level, each level shifter 13 (i) generates a clock signal CKi whose peak value is lower than the drive voltage VCC (for example, 5). An output voltage OUT having the same shape as the clock signal CK (about [V]) and a peak value raised to the driving voltage VCC (for example, about 15 [V]) can be output.
[0091]
Conversely, when the control signal ENAi indicates that the operation is stopped (when the control signal ENAi is at a low level), the current flowing from the constant current source Ic via the transistors P11 and N13 or the transistors P12 and N14 is equal to the transistor N21. Cut off by In this state, the supply of current from the constant current source Ic is stopped by the transistor N21, so that power consumption due to the current can be reduced. Also, in this state, no current is supplied to both transistors P11 and P12, so that both transistors P11 and P12 cannot operate as a differential input pair, and an output terminal, that is, a connection point of both transistors P12 and N14. Cannot be determined.
[0092]
Further, in this state, the transistors N31 and N33 of each input control unit 13c are shut off. As a result, the signal line transmitting the clock signal CK (CK bar) is separated from the gates of the transistors P11 and P12 in the input stage, and the gate capacitance serving as the load capacitance of the signal line is reduced by the level shifter 13 in operation. Limited to only things. As a result, despite the fact that a plurality of level shifters 13 (i) are connected to the signal line, the load capacity of the signal line can be reduced, and the clock signal CK (CK bar CK) can be reduced as in the control circuit 5 shown in FIG. ) Can be reduced in power consumption.
[0093]
During stop, the transistors P32 and P34 of each input switching element cutoff controller 13d conduct, so that the gate voltages of both the transistors P11 and P12 become the driving voltage VCC, and both transistors P11 and P12 are cut off. You. Thus, similarly to the case where the transistor N21 is turned off, the current consumption can be reduced by the current output from the constant current source Ic. In this state, since the transistors P11 and P12 cannot operate as a differential input pair, the potential of the output terminal cannot be determined.
[0094]
In addition, when the control signal ENA indicates that the operation is stopped, the transistor P41 of the output stabilizing unit 13e is further turned on. As a result, the output terminal, that is, the gate potential of the CMOS transistors P15 and N16 becomes the drive voltage VCC, and the output voltage OUT becomes the low level. Thereby, as shown in FIG. 4, when the control signal ENAi indicates that the operation is stopped, the output voltage OUT (CKi) of the level shifter 13 (i) is kept at the low level regardless of the clock signal CK. . As a result, unlike the case where the output voltage OUT is indeterminate while the level shifter 13 (i) is stopped, malfunction of the SR flip-flop F1 (i) can be prevented, and the shift register 11 that can operate stably can be realized.
[0095]
(Second embodiment)
In the present embodiment, unlike the first embodiment, a case where the shift register is composed of a plurality of stages of D flip-flops will be described with reference to FIGS. In each of the following embodiments, members having the same functions as those of the above embodiments will be denoted by the same reference numerals and the description thereof will be omitted for convenience of description.
[0096]
That is, as shown in FIG. 8, the shift register 21 according to the present embodiment is provided for each flip-flop unit 22 including a plurality of stages of D flip-flops F2 (1). , And level shifters 23 (1) having the same configuration as the level shifters 13 (1) shown in FIG.
[0097]
Each of the D flip-flops F2 (i) is a D flip-flop that changes the output Q according to the input D while the clock signal CKi is at the high level and maintains the output Q while the clock signal CKi is at the low level. The output Q of the flip-flop F2 (i) is output as the output Si and is also input to the next-stage D flip-flop F2 (i + 1). The start signal SP is input to the D flip-flop F2 (1) at the forefront stage.
[0098]
1, the odd-numbered level shifters 23 (1)... Output the boosted clock signal CK as the clock signal CK1... During operation, and the even-numbered level shifters 23 (2). , And outputs a signal CK2 boosted with the opposite polarity to the clock signal CK. Regardless of the even or odd number, the corresponding clock signal CKi and the inverted signal of the clock signal CKi generated by the inverter I2 (i) are applied to the D flip-flop F2 (i).
[0099]
Here, the output Si of the D flip-flop F2 (i) does not change until the clock signal CKi rises, and therefore differs from the SR flip-flop F1 (i) shown in FIG. The clock signal CKi is required at the time of falling. Therefore, in the present embodiment, the OR circuit G1 (i) for calculating the logical sum of the input and the output of each level shifter 23 (i) is provided, and the control result is sent to the corresponding level shifter 23 (i). It is output as ENAi.
[0100]
In the above configuration, as shown in FIG. 9, when the start signal SP is pulsed, the control signal ENA1 changes to a high level, and the boosted clock signal CK1 is input to the D flip-flop F2 (1). Is done. As a result, the output S1 of the D flip-flop F2 (1) changes to the high level at the next rising edge of the clock signal CK1 after the pulse input of the start signal SP, and while the clock signal CK1 is at the low level. Is maintained at a high level even when the start signal SP changes to a low level.
[0101]
When the clock signal CK1 first rises after the start signal SP changes to the low level, the output S1 of the D flip-flop F2 (1) changes to the low level. Furthermore, in this state, since both the start signal SP and the output S1 are at low level, the OR circuit G1 (1) changes the control signal ENA1 to low level and stops the level shifter 23 (1).
[0102]
Here, the output Si of each D flip-flop F2 (i) is input to the next-stage D flip-flop F2 (i + 1), and the adjacent D flip-flops F2 (i) and F2 (i + 1) have opposite phases. Clock signals CKi and CK + 1 are input. As a result, the flip-flop unit 22 can transmit the start signal SP to the next stage at each edge (rising and falling) of the clock signal CK.
[0103]
In the above-described configuration, each level shifter 23 (i) is connected to the D flip-flop F2 (i) while the corresponding D flip-flop F2 (i) requires the input of the clock signal CKi, that is, after the pulse input to the D flip-flop F2 (i) is started. , D flip-flop F2 (i) operates until the pulse output ends, and the operation can be stopped during the remaining period. As a result, as in the first embodiment, the shift register 21 that can operate with the clock signal CK having an amplitude smaller than the drive voltage VCC and that consumes less power can be realized.
[0104]
Further, unlike the first embodiment, the flip-flop unit 22 according to the present embodiment is configured by a D flip-flop that changes the output Q based on the input D and the clock signal CK. Even if the pulse width (number of clocks) of the SP changes, the start signal SP can be transmitted without any problem.
[0105]
For example, in the sampling section 3b shown in FIG. 2, when the driving capability of the sampling transistor for sampling the video signal DAT is low, a longer sampling period is required, and outputs S1... Sn having a longer pulse width (time) are required. And On the other hand, even if the pulse width is the same, the number of clocks increases as the frequency of the clock signal CK increases. Therefore, the optimum value of the pulse width of the start signal SP changes depending on the driving capability of the sampling transistor and the frequency of the clock signal CK. Therefore, in the case of a configuration in which the connection destination of the reset signal R is set according to the pulse width (the number of clocks) of the outputs S1... Like the shift register 11 shown in FIG. Need to design a different circuit. In addition, when the same data signal line driving circuit 3 is driven by clock signals CK having different frequencies or when the same is used for driving different display units 2, an optimum pulse width cannot be secured and display quality may be degraded. There is.
[0106]
On the other hand, the shift register 21 according to the present embodiment can output the outputs S1 with a desired pulse width only by changing the pulse width of the start signal SP. Therefore, it is possible to reduce the time and effort for designing and realize the image display device 1 in which the display quality does not deteriorate even in the above case.
[0107]
However, as shown in FIG. 5, the SR flip-flop F1 can be realized with a smaller number of elements than the D flip-flop F2 shown in FIG. 10 described later, and can operate at a higher speed when the operation speed of the elements is the same. Further, since the operation / stop of the next-stage level shifter 13 (i) can be directly controlled by the output Si-1 of the preceding stage, the OR circuit G1 (i) is not required. As a result, the optimum pulse width (number of clocks) can be determined in advance, and when a high-speed and small-scale circuit shift register is required, it is preferable to use the SR flip-flop F1.
[0108]
Here, in each of the D flip-flops F2, for example, as shown in FIG. 10, the P-type MOS transistors P51 and P52 and the N-type MOS transistors N53 and N54 are connected between the drive voltage VCC and the ground level. Are connected in series with each other. An input signal D is applied to the gates of the transistors P52 and N53, and the drain potentials of the transistors P52 and N53 connected to each other are inverted as an output Q after being inverted by an inverter INV51. On the other hand, between the drive voltage VCC and the ground level, there are further provided P-type MOS transistors P55 and P56 and N-type MOS transistors N57 and N58 connected in series. The drains of the transistors P56 and N57 are connected to the input of the inverter INV51, and the respective gates are connected to the output of the inverter INV51. Further, the inverted signal CK bar of the clock signal is applied to the gates of the transistors P51 and N58, and the clock signal CK is applied to the gates of the transistors N54 and P55.
[0109]
In the D flip-flop F2 having the above configuration, while the clock signal CK is at the high level, the transistors P51 and N54 are turned on, and the transistors P55 and N58 are turned off. Accordingly, the input D is inverted by the transistors P52 and N53, and then inverted by the inverter INV51. As a result, the output Q changes to the same value as the input D. Conversely, while the clock signal CK is at the low level, the transistors P51 and N54 are cut off, so that the transistors P52 and N53 cannot invert the input D. In this state, the transistors P55 and N58 conduct, and the output of the inverter INV51 is fed back to the input. As a result, while the clock signal CK is at the low level, the output Q is kept at the same value as the falling point of the clock signal CK even if the input D is at the high level. Therefore, as shown in FIG. 11, the output Q of the D flip-flop F2 changes following the input D when the clock signal CK first rises after the input D changes.
[0110]
On the other hand, as shown in FIG. 12, for example, as shown in FIG. 12, each OR circuit G1 includes a series circuit including P-type MOS transistors P61 (1) corresponding to each input IN (1), and each input IN (1). ), A parallel circuit composed of N-type MOS transistors N62 (1), and a CMOS inverter composed of a P-type MOS transistor P63 and an N-type MOS transistor N64. Here, since the OR circuit G1 is a two-input OR circuit, two transistors P61 and N62 are provided respectively, and the input IN (1) is connected to the gates of the transistors P61 (1) and N62 (1). The input IN (2) is applied to the gates of the transistors P62 (2) and N62 (2). The series circuit and the parallel circuit are connected in series with each other, and are arranged between the drive voltage VCC and the ground level. Further, the connection point between the series circuit and the parallel circuit is connected to the input terminal of the CMOS inverter, that is, the gates of the transistors P63 and N64. Thus, the OR circuit G1 can output the logical sum of the inputs IN (1) and IN (2) from the drains of the transistors P63 and N64, which are the output terminals of the CMOS inverter.
[0111]
In FIG. 8, an OR circuit G1 (i) for performing an OR operation on the input / output of each D flip-flop F2 (i) and instructing the level shifter 23 (i) to operate / stop is provided. The OR circuit G1 (i) can be omitted if it can determine the operation / stop by ORing the inputs and outputs of the D flip-flop F2 (i).
[0112]
More specifically, as shown in FIG. 13, in the shift register 21a according to the present modification, a level shifter that operates when one of the control signals ENA1 and ENA2 is active (true) instead of the level shifter 23 (i). 24 (i) are provided. Accordingly, the OR circuit G1 (i) shown in FIG. 8 is omitted, and the input / output of the D flip-flop F2 (i) is directly input as the control signals ENA1 and ENA2 to the corresponding level shifters 24 (i). .
[0113]
For example, as shown in FIG. 14, the level shifter 24 has substantially the same configuration as the level shifter 13 shown in FIG. 7, but differs from the level shifter 13 in that the power supply control unit 24b to the output stabilization unit 24e The same number (in this case, two) of transistors N21 to P41 are provided corresponding to ENA1 and ENA2. Specifically, in the power supply control unit 24b, the transistors N21 (1) and N21 (2) are connected in parallel with each other. Similarly, in the input control unit 24c corresponding to the transistor P11, the transistors N31 (1) and N31 (2) are connected. In the input control unit 24c corresponding to the transistor P12, the transistors N33 (1) and N33 (2) are connected. They are connected in parallel with each other. On the other hand, in the output stabilizing section 24e, the transistors P41 (1) and P41 (2) are connected in series with each other, and each input switching element cutoff control section 24d connects the transistors P32 (1) and P32 (2) connected in series with each other. ) Or transistors P34 (1) and P34 (2) connected in series to each other. In the present embodiment, since the shift register 21a transmits a high-level pulse signal, of the transistors N21 (1) to P41 (2), the one corresponding to the control signal ENA1 (the suffix of (1)). ), The control signal ENA1 is applied to the gate, and the control signal ENA2 corresponding to the gate corresponding to the control signal ENA2 (subscript (2)) is applied.
[0114]
According to the above configuration, when at least one of the control signals ENA1 and ENA2 is at a high level, one of the transistors N21 (1) and N21 (2), one of the transistors N31 (1) and N31 (2), and the transistor N33 (1) Conducts with any of N33 (2). Further, one of the transistors P32 (1) and P32 (2), one of the transistors P34 (1) and P34 (2), and one of the transistors P41 (1) and P41 (2) are shut off. As a result, the level shifter 24 operates similarly to the level shifter 13 described above. Conversely, when both of the control signals ENA1 and ENA2 are at the low level, all the N-type transistors N21 (1) to N34 (2) are shut off, and the P-type transistors P31 (1) to P41 (2) are turned off. 3) Since everything is conducting, the level shifter 24 stops operating similarly to the level shifter 13 described above. As a result, similarly to the level shifter 23 (i) shown in FIG. 8, the level shifter 24 (i) can operate / stop according to the input / output of the corresponding D flip-flop F2 (i), and the same effect can be obtained. Can be.
[0115]
(Third embodiment)
In the first and second embodiments, a level shifter is provided for each flip-flop. However, when a reduction in circuit size is strongly required, a plurality of flip-flops are provided as described in the following embodiments. A level shifter may be provided for each step. In the present embodiment, a case where a level shifter is provided for each of a plurality of SR flip-flops will be described with reference to FIGS.
[0116]
That is, in the shift register 11a according to the present embodiment, as shown in FIG. 15, the N SR flip-flops F1 are divided into K SR flip-flops F1 and divided into a plurality of blocks B1 to BP. I have. Further, the level shifter 13 is provided for each block B. In the following, for convenience of explanation, if i is an integer equal to or greater than 1 and equal to or less than P and j is an integer equal to or greater than 1 and equal to or less than K, in the i-th block Bi, the j-th SR flip-flop F1 is set to F1 (i , J).
[0117]
Further, in the present embodiment, an OR circuit G2 (i) for instructing the level shifter 13 (i) to the control signal ENAi is provided for each block Bi. The OR circuit G2 (i) outputs an input signal to the block Bi and an output signal of each of the SR flip-flops F1 (i, 1)... F1i, (K-1) except for the last stage in the block Bi. This is a K-input OR circuit that calculates a logical sum and outputs the result to the level shifter 13 (i). Here, the input signal to the block Bi is the start signal SP in the first block B1, and is the output signal of the previous block Bi-1 in the second and subsequent blocks Bi. In the OR circuit G2, for example, as shown in FIG. 16, in the OR circuit G1 shown in FIG. 12, the number of transistors P61 and the number of transistors N62 are increased to the number of inputs (in this case, K). It can be realized by a circuit.
[0118]
As a result, as shown in FIG. 17, the outputs Si, (K) of the SR flip-flop F1 (i, (K−1)) immediately before the last stage from the time when the pulse input to the block Bi starts. Until the end of the pulse output of -1), the control signal ENAi to the level shifter 13 (i) is at the high level. As a result, the level shifter 13 (i) operates at least while any of the SR flip-flops F1 (i, 1)... F1 (i, K) in the block Bi requires the input of the clock signal CKi, The clock signal CKi can be output and the SR flip-flop F1 (i-K) can be output from the time when the pulse input is started to the time when the last-stage SR flip-flop F1 (i, K) is set. After the setting, the operation can be stopped when the pulse output of the output Si and (K-1) of the SR flip-flop F1 (i, (K-1)) is completed.
[0119]
Here, in this embodiment, the level shifter 13 (i) continues to output the clock signal CKi when any one of the SR flip-flops F1 (i, j) of the block Bi requires a clock input. When the clock signal CKi is supplied to each SR flip-flop F1 (i, j) as it is, the SR flip-flop F1 (i, j) is reset as shown by the broken line in FIG. Since F1 (i, j) is set, a plurality of pulses are generated from one pulse of the start signal SP. Therefore, as shown in FIG. 15, the shift register 11a is provided with a switch SWi, j between the level shifter 13 (i) and each of the SR flip-flops F1 (i, j). The clock signal CKi is applied to the SR flip-flop F1 (i, j) only while the flip-flop F1 (i, (j-1)) is outputting a pulse. In order to prevent a set input to each SR flip-flop F1 (i, j) while the switch SWi, j is shut off, a negative logic set terminal of each SR flip-flop F1 (i, j) is used. The drive voltage VCC is applied to S bar via P-type MOS transistors Pi and j. In the first stage of the shift register 11a, the start signal SP is applied to the gates of the transistors P1, 1 and the gates of the transistors Pi, j of the remaining stages are connected to the SR flip-flop F1 (i, j-1) of the previous stage. Is applied. As a result, while the switch SWi, j is shut off, the transistor Pi, j conducts, the set terminal S bar is fixed at a predetermined potential (in this case, the drive voltage VCC), and the set input is prevented. You. As a result, the start signal SP is transmitted without any trouble. Note that, for example, in the SR flip-flop F1 to which the clock signal CKi is not supplied after being reset, such as the last-stage SR flip-flop F1 (i, K), the clock signal CKi is directly input without passing through the switch SW. May be.
[0120]
In the above configuration, as shown in the first embodiment, the distance between the level shifter 13 and the SR flip-flop F1 is longer than when the level shifter 13 is provided for each SR flip-flop F1. Compared with the prior art in which the clock signal CK is supplied to all SR flip-flops, the distance between the two can be shortened and the buffer can be reduced, so that the shift register 11a with low power consumption can be provided in substantially the same manner as in the first embodiment. realizable.
[0121]
Here, when the number of the SR flip-flops F1 included in the block B is increased, the number of the level shifters 13 included in the shift register 11a can be reduced, so that the circuit configuration can be simplified. On the other hand, if the number of SR flip-flops F1 is excessively increased, the driving capability of the level shifter 13 becomes insufficient and a buffer is required, so that the power consumption increases. Therefore, when a reduction in circuit size is required without increasing power consumption excessively, a buffer is not provided, and each block B is provided within a range where the level shifter 13 (i) can supply the clock signal CK (i). It is more desirable to set the number of SR flip-flops F1 in the above.
[0122]
In the above embodiment, the case where the operation / stop of the level shifter 13 is controlled by the OR circuit G2 has been described as an example. However, similar to the level shifter 24 shown in FIG. 13, as shown in FIG. The operation / stop may be determined based on each input signal to the circuit G2. For example, as shown in FIG. 19, the level shifter 14 can be realized by a circuit having the same number (K in this case) of transistors N21 to P41 as the number of inputs in the level shifter 24 shown in FIG.
[0123]
(Fourth embodiment)
Hereinafter, a case where a level shifter is provided for each of a plurality of D flip-flops will be described with reference to FIGS. That is, as shown in FIG. 20, the shift register 21b according to the present embodiment is similar to the shift register 21 shown in FIG. 8, but N D flip-flops F2 are provided for every K D flip-flops F2. It is divided into a plurality of blocks B1 to BP. Further, the level shifter 23 is provided for each block B.
[0124]
Further, in the present embodiment, an OR circuit G3 (i) for instructing the level shifter 23 (i) to the control signal ENAi is provided for each block Bi. The OR circuit G3i is a (K + 1) -input OR circuit, and calculates the logical sum of the inputs and outputs of the D flip-flops F2 (i, 1)... F2 (i, K) in the block Bi. Output to the level shifter 23 (i). Here, the input signal to the foremost D flip-flop F2 (i, 1) is the start signal SP in the foremost block B1, and the start signal SP for the foremost block Bi-1 in the second and subsequent blocks Bi. Output signal. In the OR circuit G3, for example, as shown in FIG. 21, in the OR circuit G1 shown in FIG. 12, the number of transistors P61 and the number of transistors N62 are increased to the number of inputs (in this case, K + 1). It can be realized by a circuit.
[0125]
Thereby, as shown in FIG. 22, while any of the D flip-flops F2 (i, 1)... F2 (i, K) in the block Bi requires the input of the clock signal CKi, During the period from the start of the pulse input to Bi to the end of the pulse output of the last D flip-flop F2 (i, K), the control signal ENAi to the level shifter 23 (i) becomes high level, and the level shifter 23 (i) becomes high level. 23 (i) can output the clock signal CKi. In the remaining period, since the control signal ENAi is at the low level, the operation of the level shifter 23 (i) can be stopped.
[0126]
In the above configuration, the distance between the level shifter 23 and the D flip-flop F2 is longer than when the level shifter 23 is provided for each D flip-flop F2 as in the shift register 21 according to the second embodiment. Compared with the prior art in which the clock signal CK is supplied from one level shifter to all the D flip-flops, the distance between the two can be reduced and the number of buffers can be reduced, so that the power consumption is low as in the second embodiment. The shift register 21b can be realized.
[0127]
Furthermore, as in the third embodiment, in the present embodiment, the number of level shifters 23 can be reduced as compared with the shift register 21. Further, when it is required to reduce the circuit size without increasing power consumption excessively, the level shifter 23 (i) can supply the clock signal CKi without providing a buffer within a range in which the clock signal CKi can be supplied. It is desirable to set the number of flip-flops F2.
[0128]
In FIG. 20, the case where the operation / stop of the level shifter 23 is controlled by the OR circuit G3 has been described as an example. However, like the shift register 11b shown in FIG. 18, like the shift register 21c shown in FIG. 25 itself may control the operation / stop based on each input signal to the OR circuit G3. For example, as shown in FIG. 24, the level shifter 25 can be realized by a circuit having the same number of inputs (in this case, K + 1) as the level shifter 14 shown in FIG.
[0129]
(Fifth embodiment)
By the way, in the third (fourth) embodiment, the case where the level shifter or the OR circuit ORs K and (K + 1) signals to control the operation / stop of the level shifter has been described. On the other hand, in the present embodiment, a case where the operation / stop of the level shifter is controlled using a latch circuit will be described with reference to FIGS.
[0130]
Specifically, as shown in FIG. 25, in the shift register 11c according to the present embodiment, a latch circuit 31 (i) is provided instead of the OR circuit G2 (i) of the shift register 11a shown in FIG. I have. The latch circuit 31 changes its output triggered by a pulse input to the first-stage SR flip-flop F1 (i, 1) of the block Bi and a pulse output of the last-stage SR flip-flop F1 (i, K). The operation can be instructed to the level shifter 13 (i) from the time when the pulse input is started to the time when the pulse output is started.
[0131]
In the latch circuit 31, for example, in the case of the first block B1, as shown in FIG. 26, a start signal SP inverted by an inverter 31a is applied as a negative logic set signal S, and a positive logic reset is performed. An SR flip-flop 31b to which the output S1, K of the last-stage SR flip-flop F1 (1, K) is applied as the signal R is provided. In the subsequent blocks Bi, the output of the preceding block Bi-1 is applied instead of the start signal SP.
[0132]
In the above configuration, as shown in FIG. 27, the latch circuit 31 (i) outputs the outputs Si and K from the time when the input to the first-stage SR flip-flop F1 (i, 1) changes to a high level. The control signal ENAi is set to a high level until it changes to the level. Thereby, the level shifter 13 (i) can continue to supply the clock signal CKi during the period. When the outputs Si and K change to the high level, the control signal ENAi changes to the low level, and the level shifter 13 (i) stops operating. As a result, similarly to the third embodiment, it is possible to realize the shift register 11c that consumes less power than the conventional case.
[0133]
Further, like the OR circuit G2 (i) (level shifter 14 (i)) of the third embodiment, the latch circuit 31 (i) according to the present embodiment uses the level shifters 13 (i) ( Unlike the case where the operation / stop is determined in 14 (i)), the control signal ENAi is generated using two signals as triggers regardless of the number K of stages of the SR flip-flop F1 in the block Bi. Therefore, the number of signal lines transmitting signals required for determination can be reduced to two. Here, when the number of signal lines for determination increases, the number of intersections with the signal lines transmitting the outputs Si, j and the clock signals CK, CKi increases, and the capacity of each signal line may increase. However, in the present embodiment, the number of signal lines for determination is reduced to two, so that an increase in wiring capacity due to the signal lines for determination can be suppressed more than in the third embodiment, and furthermore, power consumption is reduced. A small shift register 11c can be realized.
[0134]
In FIG. 26, the case where the latch circuit 31 (i) is configured by an SR flip-flop has been described as an example, but the present invention is not limited to this. If the operation / stop of the level shifter 13 (i) can be controlled by using two signals as triggers, the same effect can be obtained by using, for example, a latch circuit 32 shown in FIG. 28 instead of the latch circuit 31 (i). can get.
[0135]
The latch circuit 32 includes two D flip-flops 32a and 32b constituting a frequency divider, a NOR circuit 32c for calculating a logical negation of the start signal SP and outputs S1 and K, and an output of the NOR circuit 32c. Is provided. The output Q of the D flip-flop 32a is input to the D flip-flop 32a via the D flip-flop 32b. The output LSET of the inverter 32d is applied to the D flip-flop 32a as a clock, and the output of the NOR circuit 32c is applied to the D flip-flop 32b as a clock. Further, the output LOUT of the D flip-flop 32a is output as the control signal ENA1. As a result, as shown in FIG. 29, like the latch circuit 31 (i), the latch circuit 32 (i) starts inputting a pulse to the forefront SR flip-flop F1 (i, 1). By outputting the high-level control signal ENAi until the rise of the outputs Si and K, the operation can be instructed to the level shifter 13 (i).
[0136]
In this embodiment, as triggers of the latch circuits (31 and 32), the start of pulse input to the first-stage SR flip-flop F1 (i, 1) and the last-stage SR flip-flop F1 (i, K) Although the start of the pulse output is used, the present invention is not limited to this. A signal capable of setting the control signal ENAi to active at a timing before the period when the SR flip-flop F1 in the block Bi requires the clock signal CKi, and setting the control signal ENAi to inactive at a timing after the period. A similar effect can be obtained if a possible signal is used as a trigger.
[0137]
(Sixth embodiment)
In the present embodiment, a configuration in which operation / stop of a level shifter is controlled by a latch circuit in a shift register using a D flip-flop will be described with reference to FIGS.
[0138]
That is, in the shift register 21d according to the present embodiment, instead of the OR circuit G3 (i) of the shift register 21b shown in FIG. 20, almost the same as the latch circuit 31 (i) shown in FIG. There is provided a latch circuit 33 (i) triggered by a pulse input to F2 (i, 1) and a pulse output of the last D flip-flop F2 (i, K). However, as described above, in the case of the D flip-flop, the clock signal CKi is necessary until the pulse output of the last D flip-flop F2 (i, K) stops, so that the latch circuit 33 (i) is used. Is configured to instruct the level shifter 23 (i) to operate from the time when the pulse input is started to the time when the pulse output is stopped.
[0139]
Specifically, taking the first block B1 as an example, for example, as shown in FIG. 31, the latch circuit 33 includes an output signal LOUT and an output S1 of the last stage in addition to the latch circuit 31 shown in FIG. , K, and an inverter 33d for inverting the calculation result. In the subsequent blocks Bi, the output of the preceding block Bi-1 is applied instead of the start signal SP.
[0140]
In the above configuration, as shown in FIG. 32, the latch circuits 33 (1) output the outputs S1 and K from the time when the input to the D flip-flop F2 (1,1) at the front stage changes to the high level. The control signal ENA1 is set to a high level until it changes to the level. Thus, the level shifter 23 (1) can continue to supply the clock signal CK1 during the period. When the outputs S1 and K change to low level, the control signal ENA1 changes to low level, and the level shifter 23 (1) stops operating. As a result, similarly to the fourth embodiment, a shift register 21d that consumes less power than the conventional case can be realized.
[0141]
Furthermore, in the present embodiment, as in the fifth embodiment, the number of signal lines required for determining the operation / stop of the level shifter 23 can be reduced. An increase in the wiring capacity can be suppressed, and the shift register 21d with low power consumption can be realized.
[0142]
Although FIG. 31 illustrates an example in which the latch circuit 33 includes an SR flip-flop, the present invention is not limited to this. If the operation / stop of the level shifter 13 can be controlled by using two signals as triggers, the same effect can be obtained by using, for example, a latch circuit 34 shown in FIG. 33 instead of the latch circuit 31 (i).
[0143]
In the latch circuit 34, a NOR circuit 33c and an inverter 33d shown in FIG. 31 are added to the latch circuit 32 shown in FIG. As a result, as shown in FIG. 34, similarly to the latch circuit 33, the latch circuit 34 starts the pulse input to the D flip-flop F2 (i, 1) at the forefront stage of the block Bi from the last stage. By outputting the high-level control signal ENAi until the D flip-flop F2 (i, K) ends the pulse output, the operation can be instructed to the level shifter 23 (i).
[0144]
In this embodiment, as triggers of the latch circuits (33 to 34), the start of pulse input to the front-stage D flip-flop F2 (i, 1) and the last stage D flip-flop F2 (i, K) Although the end of the pulse output is used, the present invention is not limited to this. A signal capable of setting the control signal ENAi to active at a timing before the period when the D flip-flop F2 in the block Bi requires the clock signal CKi, and setting the control signal ENAi to inactive at a timing after the period A similar effect can be obtained if a possible signal is used as a trigger.
[0145]
(Seventh embodiment)
Hereinafter, referring to FIG. 35, as in the fourth and sixth embodiments, in shift registers 21b to 21d in which level shifter 23 (24, 25) supplies clock signal CK to a plurality of D flip-flops F2, A configuration capable of further reducing power consumption will be described.
[0146]
Specifically, the shift register according to the present embodiment has the same configuration as the shift registers 21b to 21d, but the clock signal control circuit 26 (i, j) is provided for each D flip-flop F2 (i, j). The level shifter 23 (i) (24 (i), 25 (i): hereinafter, represented by 23 (i)) is provided with a boosted clock only to the D flip-flop F2 requiring a clock input. The signal CK (i) is supplied.
[0147]
As shown in FIG. 35, the clock signal control circuit 26 (i, j) includes a switch SW1 (i, j) provided on a signal line through which the clock signal CKi is transmitted, and an inverted signal CKi of the clock signal CKi. And a switch SW2 (i, j) provided on the transmission line. The two switches SW1 (i, j) and SW2 (i, j) are OR gates for calculating the logical sum of the input and output of the D flip-flop F2 (i, j), similarly to the level shifter 23 (i, j) shown in FIG. Controlled by the circuit G1 (i, j), it is turned on when the D flip-flop F2 (i, j) requires the clock signal CKi (CKi bar) and cut off when the clock input is not needed. Further, the clock signal control circuit 26 (i, j) includes an N-type MOS transistor N71 (i, j) provided between the clock input terminal of the D flip-flop F2 (i, j) and the ground potential. , And a P-type MOS transistor P72 (i, j) provided between the inverted clock input terminal of the D flip-flop F2 (i, j) and the drive voltage VCC. The output of the OR circuit G1 (i, j) is applied to the gate of the transistor N71 (i, j) after being inverted by the inverter INV71 (i, j), and is applied to the transistor P72 (i, j). The output of the OR circuit G1 (i, j) is applied to the gate of.
[0148]
In the above configuration, the switch SW1 (i, j) (SW2 (i, j)) conducts while the corresponding D flip-flop F2 (i, j) needs the boosted clock signal CKi (CKi bar) for a necessary period. To apply a clock signal CKi (CKi bar) to the D flip-flop F2 (i, j). On the other hand, during a period in which no clock input is required, the switches SW1 (i, j) and SW2 (i, j) are shut off, and for example, both switches SW1 (i, j) such as a D flip-flop F2 (i, j). (2) Separate the circuit after SW2 (i, j) from the level shifter 23 (i). Further, during a period in which no clock input is required, the transistors N71 (i, j) and P72 (i, j) are turned on, and the clock input terminal and the inverted input terminal of the D flip-flop F2 (i, j) are connected. Since each of them is maintained at a predetermined value (low level and high level), it is possible to suppress malfunction of the D flip-flop F2 (i, j), unlike the case where both input terminals are undefined.
[0149]
According to the above configuration, the circuit after the switches SW1 (i, j) and SW2 (i, j) is disconnected from the level shifter 23 (i) during the period in which the clock input is unnecessary, so that the level shifter 23 (i) Need only drive the D flip-flop F2 (i, j) that currently requires the clock signal CK (i). Therefore, the load capacity of the level shifter 23 (i) can be significantly reduced and power consumption can be reduced as compared with the case where all the D flip-flops F2 (i, 1) to F2 (i, K) in the block Bi are driven. . As a result, a shift register with low power consumption can be realized.
[0150]
In the above description, the case where the clock signal control circuit 26 (i, j) is provided for each D flip-flop F2 (i, j) has been described as an example. However, the present invention is not limited to this. A clock signal control circuit 26 may be provided for each of the D flip-flops F2. In this case, both switches SW1 and SW2 are connected while the D flip-flop F2 connected to both switches SW1 and SW2 requires a clock input, that is, after the pulse input to the foremost stage D flip-flop F2 is started. For example, the same operation as the OR circuit G3 shown in FIG. 20 and the latch circuit 33 (34) shown in FIG. 30 (FIG. 33) is performed so that the D-flip-flop F2 of the final stage can conduct until the pulse output ends. Controlled by the circuit. In this case, although the load capacity of the level shifters 23 (24, 25) is increased as compared with the configuration in which the clock signal control circuit 26 is provided for each D flip-flop F2, the number of clock signal control circuits 26 can be reduced. The circuit configuration can be simplified.
[0151]
(Eighth embodiment)
By the way, for example, in the data signal line driving circuit 3 and the scanning signal line driving circuit 4 shown in FIG. 2, the output of each stage of the shift register (11.11a to 11c.21.21a to 21d) according to each of the above embodiments is output. In some cases, a signal indicating timing may be directly used, but a signal obtained by performing a logical operation on outputs of a plurality of stages may be used as a timing signal.
[0152]
In the following, as in the first, third, and fifth embodiments, in a shift register using the SR flip-flop F1, a configuration suitable for performing a logical operation on outputs of a plurality of stages will be described with reference to FIGS. It will be described with reference to FIG. It should be noted that any configuration using the SR flip-flop F1 can be applied to other embodiments, but hereinafter, the case of the first embodiment will be described as an example.
[0153]
That is, in addition to the configuration of the shift register 11 shown in FIG. 1, the shift register 11d according to the present embodiment calculates a logical product of two outputs Si and Si + 1 adjacent to each other, and outputs the calculation result as a timing signal SMPi. An AND circuit G4 (i) is provided. Further, an SR flip-flop F1 (0) is provided in a stage preceding the foremost SR flip-flop F1 (1), and calculates the logical product of the output S0 of the SR flip-flop F1 (0) and the output S1. And an AND circuit G4 (0) for output. Further, an inverted signal SP of the start signal SP is applied to the SR flip-flop F1 (0) as a negative logic set signal, and the output of the SR flip-flop F1 (0) is a level shifter to be a next stage. 13 (1) is input as a control signal ENA1. The SR flip-flop F1 (0) is, like the SR flip-flop F1 (i) of the other stage, a level shifter 13 (in this case, two stages) corresponding to the pulse width of the pulse signal to be transmitted. The output CK2 of 2) is applied.
[0154]
Here, among the outputs S0, S1,... Of the SR flip-flops F1 (0), F1 (1), etc., only the output S0 is connected to the single AND circuit G4 (0), and the other outputs Si, Are connected to two AND circuits G4 (i-1) and G4 (i). As a result, the output load is different between the SR flip-flop F1 (0) and the remaining SR flip-flop F1 (i), and even if driven at the same timing, the output S0 and the remaining output S1. The delay times for the signal CK are different from each other. Therefore, when the frequency of the clock signal CK is high, the output signal of the AND circuit G4 (0) becomes a dummy signal DUMMY that is not used in a subsequent circuit, in order to suppress timing variations due to a delay time delay. Only the remaining outputs SMP1 of the AND circuits G4 (1) are used for video signal extraction.
[0155]
In the above configuration, unlike the other stages, the inverted signal SP bar not synchronized with the clock signal CK is applied as a negative logic set signal to the SR flip-flop F1 (0). Are different from the outputs S1 of the other SR flip-flops F1 (1). However, as described above, the output S0 is not used as a dummy signal DUMMY in a subsequent circuit. Therefore, even if the timing of the output S0 is different, the shift register 11d can output the timing signals SMP1...
[0156]
Further, in the above configuration, the inverted signal SP bar is applied to the SR flip-flop F1 (0), and the level shifter 13 is omitted. Therefore, the number of the level shifters 13 can be reduced as compared with the case where the level shifters 13 are provided also in the SR flip-flop F1 (0).
[0157]
In the first to eighth embodiments, the case where the level shifters (13, 14, 23 to 25) are of the current drive type has been described as an example. However, as shown in FIG. May be used. The level shifter 41a of the level shifter 41 is, as an input switching element, an N-type MOS transistor N81 which is turned on / off in response to a clock signal CK, and is turned on / off in response to an inverted signal CK bar of the clock signal CK. An N-type MOS transistor N82. The drive voltage VCC is applied to the drain of each transistor N81 (N82) via a P-type MOS transistor P83 (P84) as a load, and the sources of both transistors N81 and N82 are grounded. The potential at the connection point between the transistors N82 and P84 is output as the output OUT of the level shifter 41 and is applied to the gate of the transistor P83. Similarly, the potential at the connection point between the transistors N81 and P83 is output as the inverted output OUT bar of the level shifter 41 and applied to the gate of the transistor P84.
[0158]
On the other hand, the level shifter 41 is provided with N-type MOS transistors N91 and N92 as an input open switch section (switch) 41b. During the operation of the level shifter 41, the gate of the transistor N81 is connected via the transistor N91. In addition, the clock signal CK is applied, and an inverted signal CK of the clock signal CK is applied to the gate of the transistor N82 via the transistor N92.
[0159]
Further, the level shifter 41 is provided with an N-type MOS transistor N93 and a P-type MOS transistor P94 as an input stabilizer 41c. Thus, while the level shifter 41 is stopped, the gate of the transistor N81 is grounded via the transistor N93, and the driving voltage VCC is applied to the gate of the transistor N82 via the transistor P94. The input stabilizing unit 41c corresponds to the output stabilizing means described in the claims, and controls the input voltage to both the transistors N81 and N82 to stabilize the output. Here, the level shifter 41 is a voltage-driven type, and consumes power only when the output OUT changes. Therefore, when the level shifter 41 is stopped, power consumption does not occur even if the output voltage is controlled by the input voltage.
[0160]
In the present embodiment, when the control signal ENA is at a high level, the operation of the level shifter 41 is shown. Therefore, the control signal ENA is applied to the gates of the transistors N91, N92, and P94, and the control signal ENA is applied to the transistor N93. ENA is applied after being inverted by the inverter INV91.
[0161]
In the above configuration, when the control signal ENA is at a high level, the transistors N91 and N92 are turned on, and the transistors N81 and N82 are turned on / off according to the clock signal CK and its inverted signal CK bar. Thus, the output OUT is boosted to the level of the drive voltage VCC when the clock signal CK is at the high level, and is at the ground level when the clock signal CK is at the low level.
[0162]
Conversely, when the control signal ENA is at a low level, the transistors N93 and P94 are turned on, so that the transistor N81 is turned off and the transistor N82 is turned on. As a result, the output OUT is maintained at the ground level, and the inverted output OUT is maintained at the drive voltage VCC. In this state, since the transistors N91 and N92 are shut off, the gate of the transistor N81 (N82) as an input switching element is disconnected from the transmission line of the clock signal CK (CK bar). Thus, for example, the load capacitance and power consumption of the drive circuit for the clock signal CK (CK bar) such as the control circuit 5 shown in FIG. 2 can be reduced.
[0163]
In FIG. 38, the case where the operation / stop is controlled by one control signal ENA as in the case of the level shifters 13 and 23 has been described as an example. However, as in the case of the level shifters 14, 24 and 25, the transistors N91 to P94. If the number of inverters INV91 is increased in accordance with the number of control signals ENA, operation / stop can be controlled by a plurality of control signals ENA.
[0164]
Even when the level shifter 41 having the above configuration is used, a plurality of level shifters 41 are provided, and at least one of the level shifters 41 that does not need clock output is stopped, so that a single level shifter is connected to all flip-flops of the shift register. Compared with the case where a clock signal is supplied, the load capacity of each level shifter can be reduced, and the power consumption of the shift register can be reduced.
[0165]
However, the current-driven level shifters 13 (14 · 23 to 25: hereinafter represented by the level shifter 13) shown in the first to eighth embodiments are constantly connected to the input switching elements (P11 · P12) during operation. Since the current flows, even if the amplitude of the clock signal CK is lower than the threshold of the input switching elements (transistors N81 and N82) and the level shifter 41 cannot operate, the clock signal CK is boosted without any problem. it can. In addition, since the level shifter 13 is stopped according to the necessity of clock output, the power consumption increases even if the output is not changed, despite the fact that a plurality of level shifters 13 that consume power are provided. Can be suppressed. Therefore, it is desirable to use the current-driven level shifter 13.
[0166]
In the third to seventh embodiments, the case where the level shifters (13, 14, 23 to 25) are provided for each of the K flip-flops (F1, F2) has been described as an example. If the level shifter is provided for each block, substantially the same effect can be obtained even if the number of flip-flops included in each block is not the same.
[0167]
Further, in each of the above embodiments, an image display device has been described as an example of application of the shift register. However, the present invention is applicable to any application in which a clock signal CK having an amplitude lower than the drive voltage of the shift register is applied. Such a shift register can be widely applied. However, in the image display device, since the improvement of the resolution and the enlargement of the display area are strongly required, the number of stages of the shift register is large, and the driving capability of the level shifter cannot be sufficiently secured in many cases. Therefore, it is particularly effective when applied to a drive circuit of an image display device.
[0168]
Note that the shift register and the image display device may have the following configurations.
[0169]
(1) A plurality of flip-flops that operate in synchronization with a clock signal, and a level shifter that boosts a clock signal having an amplitude smaller than a drive voltage of the flip-flop and applies the boosted clock signal to each of the flip-flops, In a shift register that transmits an input pulse in synchronization with a signal, each of the flip-flops is divided into a plurality of blocks including at least one flip-flop, and the level shifter is provided for each of the blocks. Among the plurality of level shifters, at least one of the level shifters corresponding to a block that does not require the input of the clock signal for transmission of the input pulse at that time is stopped, and a specific block of the blocks is the flip-flop. As a flip-flop, The specific level shifter corresponding to the specific block starts operating when a pulse input to the specific block starts, and stops after the last stage flip-flop of the specific block finishes pulse output. Shift register.
[0170]
(2) In the shift register of (1), the number of the flip-flops in the specific block is plural, and the specific level shifter is configured to control a signal input to the specific block and a flip-flop of a last stage of the specific block. A shift register including a latch circuit for changing an output in response to an output signal.
[0171]
(3) a plurality of flip-flops that operate in synchronization with a clock signal; and a level shifter that boosts a clock signal having an amplitude smaller than the drive voltage of the flip-flop and applies the boosted clock signal to each of the flip-flops. In a shift register that transmits an input pulse in synchronization with a signal, each of the flip-flops is divided into a plurality of blocks including at least one flip-flop, and the level shifter is provided for each of the blocks. At least one of the level shifters corresponding to a block that does not require the input of the clock signal for transmission of the input pulse at that time is stopped, and the level shifter includes a current having an input switching element. Shift register including drive-type level shift unit Data.
[0172]
(4) In the shift register of (3), the level shifter includes an input signal control unit that stops the level shifter by giving a signal of a level cut off by the input switching element as an input signal to the level shift unit. Shift register provided.
[0173]
(5) The shift register according to (3), wherein the level shifter includes a power supply control unit that stops power supply to the level shift unit and stops the level shifter.
[0174]
(6) A plurality of pixels arranged in a matrix, a plurality of data signal lines arranged in each row of each pixel, and a plurality of scanning signal lines arranged in each column of each pixel are predetermined. A scanning signal line driving circuit for sequentially applying scanning signals at mutually different timings to the respective scanning signal lines in synchronization with a first clock signal having a predetermined period, and sequentially applying the scanning signals in synchronization with a second clock signal having a predetermined period. A data signal line drive for extracting a data signal to each pixel of the scanning signal line to which the scanning signal is applied from a video signal indicating a display state of each pixel and outputting the data signal to each data signal line And at least one of the data signal line driving circuit and the scanning signal line driving circuit uses the first or second clock signal as the clock signal (1) to (5). The image display device includes any one of the shift register.
[0175]
(7) The image display device according to (6), wherein the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate.
[0176]
(8) The image display device according to (6) or (7), wherein the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element made of a polycrystalline silicon thin film transistor.
[0177]
(9) In the image display device according to any one of (6) to (8), the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element manufactured at a process temperature of 600 degrees or less. Image display device.
[0178]
【The invention's effect】
As described above, the shift register according to the present invention includes a plurality of flip-flops that operate in synchronization with a clock signal, and boosts a clock signal having an amplitude smaller than the driving voltage of the flip-flop to each of the flip-flops. A shift register having an applied level shifter and transmitting an input pulse in synchronization with the clock signal, wherein each of the flip-flops is divided into a plurality of blocks each including at least one flip-flop; At least one of the plurality of level shifters provided for each block and corresponding to a block that does not require the input of the clock signal for transmission of the input pulse at that time is stopped, Each level shifter has a configuration including output stabilizing means.
[0179]
In this configuration, since a plurality of level shifters are provided in the shift register, the distance from each level shifter to the flip-flop can be reduced. At least one of the plurality of level shifters has stopped operating. As a result, there is an effect that a shift register which can operate with a low-voltage clock signal input and consumes low power can be realized.
[0180]
Further, according to this configuration, while the level shifter is stopped, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means, so that a malfunction of the flip-flop due to an undefined output voltage can be prevented. This has the effect of realizing a more stable shift register.
[0181]
Further, as described above, in the shift register according to the present invention, in the shift register having the above configuration, the level shifter is disposed between the clock signal line through which the clock signal is transmitted and the level shift unit, In this configuration, a switch that is opened while the level shifter is stopped is provided.
[0182]
In this configuration, the input switching elements connected to the clock signal line are limited to those of the operating level shifter, so that the load capacity of the clock signal line can be reduced and the power consumption of the circuit driving the clock signal line is reduced. It has the effect of being able to.
[0183]
Note that, as another shift register, a flip-flop is divided into a plurality of blocks each including at least one flip-flop, and a level shifter that boosts a clock signal having an amplitude smaller than a driving voltage is provided for each block. And at least one of the plurality of level shifters corresponding to a block that does not require the input of the clock signal for transmission of the input pulse at that time is stopped. Is obtained.
[0184]
In this configuration, since a plurality of level shifters are provided in the shift register, the distance from each level shifter to the flip-flop can be reduced. At least one of the plurality of level shifters has stopped operating. As a result, there is an effect that a shift register which can operate with a low-voltage clock signal input and consumes low power can be realized.
[0185]
Further, in the shift register having the above-described configuration, a specific block includes a D flip-flop, and the specific level shifter starts operating when a pulse input to the specific block is started. If the operation is stopped after the last-stage flip-flop has finished outputting the pulse, the following effects can be obtained.
[0186]
According to this configuration, the specific level shifter supplies the clock signal after the level shift during a period necessary for the operation of the D flip-flop of the specific block, so that the input of the clock signal to the D flip-flop is unnecessary. Has an effect that, since the operation is stopped, input pulses having different pulse widths can be transmitted, and a shift register with low power consumption can be realized.
[0187]
In another shift register having the above-described configuration, the shift register includes a plurality of D flip-flops in a specific block, and the specific level shifter is configured to control a signal input to the specific block and a flip-flop in a final stage of the specific block. The following effects can be obtained by using a configuration including a latch circuit that changes the output in accordance with the output signal.
[0188]
According to this configuration, the output of the latch circuit changes based on the two signals, and the operation / stop of the specific level shifter is controlled. Therefore, even when the number of flip-flops in the specific block is large, the circuit configuration of the shift register can be changed. An effect that simplification can be achieved.
[0189]
Further, if the shift register is configured to include a current-driven level shift unit in which the input switching element for applying the clock signal is always in conduction during operation, in the shift register having the above configuration, The following effects can be obtained.
[0190]
According to this configuration, since at least one of the current-driven level shifters stops operating, the level shift can be performed even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element, and power consumption is reduced. This has the effect of realizing a shift register with less noise.
[0191]
Further, in the shift register according to another aspect of the present invention, the shift register further includes an input signal control unit that stops the level shifter by supplying a signal of a level that the input switching element shuts off to the level shift unit. Then, the following effects can be obtained.
[0192]
According to this configuration, since the input signal control unit controls the level of the input signal and shuts off the input switching element, power consumption can be reduced by the amount of current flowing to the input switching element during operation during stoppage. This has the effect.
[0193]
Further, if the shift register has a power supply control unit that stops power supply to the level shift unit and stops the level shifter in another shift register having the above configuration, the following effects can be obtained. can get.
[0194]
According to this configuration, since the power supply to each level shift unit is stopped to stop the level shifter, the power consumption can be reduced by the amount of power consumed by the level shifter during stop and operation. .
[0195]
Further, if the shift register is configured to have an output stabilizing means for maintaining the output voltage at a predetermined value when the level shifter is stopped in the other shift register of each of the above configurations, the following effects can be obtained. Can be
[0196]
According to this configuration, while the level shifter is stopped, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means, so that a malfunction of the flip-flop due to an undefined output voltage can be prevented, and There is an effect that a stable shift register can be realized.
[0197]
Further, in the above-mentioned other shift register, each of the shift registers is provided with a switch provided between the level shift unit and the transmission line of the clock signal, the switch being opened while the level shifter is stopped. Then, the following effects can be obtained.
[0198]
In this configuration, the input switching elements connected to the clock signal line are limited to those of the operating level shifter, so that the load capacity of the clock signal line can be reduced and the power consumption of the circuit driving the clock signal line is reduced. It has the effect of being able to.
[0199]
As described above, the image display device according to the present invention has a configuration in which at least one of the data signal line driving circuit and the scanning signal line driving circuit includes the shift register having any one of the above-described configurations.
[0200]
According to this configuration, at least one of the data signal line driving circuit and the scanning signal line driving circuit includes the shift register of each of the above configurations, so that an image display device with low power consumption can be realized.
[0201]
The same effect can be obtained even when any of the other shift registers is provided as the shift register.
[0202]
In the image display device according to the present invention, in the above configuration, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate.
[0203]
According to this configuration, even if the number of data signal lines and the number of scanning signal lines increase, the number of signal lines extending out of the substrate does not change. This has the effect of preventing a reduction in the degree of integration.
[0204]
In the image display device according to the present invention, in the above configuration, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element made of a polycrystalline silicon thin film transistor.
[0205]
In this configuration, since the data signal line driving circuit, the scanning signal line driving circuit, and each pixel each include a switching element formed of a polycrystalline silicon thin film transistor, an image with low power consumption and a large display area is provided. There is an effect that a display device can be realized.
[0206]
In the image display device according to the present invention, in the above configuration, the data signal line drive circuit, the scan signal line drive circuit, and each pixel include a switching element manufactured at a process temperature of 600 degrees or less.
[0207]
According to this configuration, even when a normal glass substrate (a glass substrate having a strain point of 600 ° or less) is used, warpage or warpage due to a process at or above the strain point does not occur, so that mounting is further facilitated. There is an effect that an image display device having a large display area can be realized.
[Brief description of the drawings]
FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a main configuration of a shift register including a set / reset flip-flop.
FIG. 2 is a block diagram illustrating a main configuration of an image display device using the shift register.
FIG. 3 is a circuit diagram illustrating a configuration example of a pixel in the image display device.
FIG. 4 is a timing chart showing the operation of the shift register.
FIG. 5 is a circuit diagram showing a configuration example of a set / reset flip-flop used in the shift register.
FIG. 6 is a timing chart showing the operation of the set / reset flip-flop.
FIG. 7 is a circuit diagram showing a configuration example of a level shifter in the shift register.
FIG. 8 illustrates another embodiment of the present invention, and is a block diagram illustrating a main configuration of a shift register including a D flip-flop.
FIG. 9 is a timing chart showing the operation of the shift register.
FIG. 10 is a circuit diagram showing a configuration example of the D flip-flop.
FIG. 11 is a timing chart showing the operation of the D flip-flop.
FIG. 12 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.
FIG. 13 is a block diagram showing a modified example of the shift register.
FIG. 14 is a circuit diagram showing a configuration example of a level shifter in the shift register.
FIG. 15 illustrates still another embodiment of the present invention, and is a block diagram illustrating a shift register in which a level shifter is provided for each of a plurality of set / reset flip-flops.
FIG. 16 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.
FIG. 17 is a timing chart showing the operation of the shift register.
FIG. 18 is a block diagram showing a modification of the shift register.
FIG. 19 is a circuit diagram showing a configuration example of a level shifter in the shift register.
FIG. 20 is a block diagram illustrating a shift register in which a level shifter is provided for each of a plurality of D flip-flops according to still another embodiment of the present invention.
FIG. 21 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.
FIG. 22 is a timing chart showing the operation of the shift register.
FIG. 23 is a block diagram showing a modification of the shift register.
FIG. 24 is a circuit diagram showing a configuration example of a level shifter in the shift register.
FIG. 25 shows still another embodiment of the present invention, and is a block diagram illustrating a latch circuit for controlling the operation of a level shifter and a shift register including a set / reset flip-flop.
FIG. 26 is a block diagram illustrating a configuration example of the latch circuit.
FIG. 27 is a timing chart showing the operation of the shift register.
FIG. 28 is a block diagram showing another configuration example of the latch circuit.
FIG. 29 is a timing chart showing the operation of the latch circuit.
FIG. 30 is a block diagram showing a shift register including the latch circuit and a D flip-flop according to still another embodiment of the present invention.
FIG. 31 is a block diagram illustrating a configuration example of the latch circuit.
FIG. 32 is a timing chart showing the operation of the shift register.
FIG. 33 is a block diagram showing another configuration example of the latch circuit.
FIG. 34 is a timing chart showing the operation of the latch circuit.
FIG. 35 shows still another embodiment of the present invention, and is a circuit showing a clock signal control circuit provided when a level shifter of each block selectively supplies a clock signal to a D flip-flop in the block. FIG.
FIG. 36 shows another embodiment of the present invention, and is a block diagram showing a main configuration of a shift register.
FIG. 37 is a timing chart showing the operation of the shift register.
FIG. 38, showing a modification of the present invention, is a circuit diagram illustrating a voltage-driven level shifter.
FIG. 39 shows a conventional example, and is a block diagram showing a shift register including a level shifter.
[Explanation of symbols]
1 Image display device
3 Data signal line drive circuit
4 Scanning signal line drive circuit
11.11a-11d-21.21a-21c shift register
13.14.23 to 25.41 Level shifter
13a / 14a / 23a to 25a / 41a Level shift unit
13b / 14b / 23b-25b Power supply control unit
13c / 14c / 23c ~ 25c Input control unit (switch)
13d ・ 14d Input switching element cutoff control unit (input signal control unit)
13e ・ 14e ・ 23e ～ 25e Output stabilization part (output stabilization means)
23d-25d Input switching element cutoff control unit (input signal control unit)
31-34 Latch circuit
41b Input release switch (switch)
41c Input stabilizer (output stabilizer)
B1 ... block (specific block)
F1 (1) ... SR flip-flop (flip-flop)
F2 (1) ... D flip-flop (flip-flop)
P11 / P12 transistor (input switching element)
PIX pixel

Claims (6)

A multi-stage flip-flop operating in synchronization with a clock signal,
A shift register for boosting a clock signal having an amplitude smaller than the driving voltage of the flip-flop and applying the boosted clock signal to each flip-flop, and transmitting an input pulse in synchronization with the clock signal;
Each of the flip-flops is divided into a plurality of blocks including at least one flip-flop,
The level shifter is provided for each of the blocks, and
At least one of the level shifters corresponding to a block that does not require the input of the clock signal to transmit the input pulse at that time is stopped,
A shift register, wherein each of the level shifters includes output stabilizing means. The level shifter is provided with a switch disposed between the clock signal line through which the clock signal is transmitted and the level shift unit, and opened while the level shifter is stopped. The shift register according to claim 1, wherein: A plurality of pixels arranged in a matrix,
A plurality of data signal lines arranged in each row of each of the pixels,
A plurality of scanning signal lines arranged in each column of each of the pixels,
A scanning signal line driving circuit for sequentially applying scanning signals at mutually different timings to the respective scanning signal lines in synchronization with a first clock signal having a predetermined cycle;
A data signal to each pixel of a scanning signal line to which the scanning signal is applied is converted from a video signal which is sequentially applied in synchronization with a second clock signal having a predetermined cycle and which indicates a display state of each pixel. An image display device having a data signal line driving circuit for extracting and outputting the data signal lines to the data signal lines,
3. The image according to claim 1, wherein at least one of the data signal line driving circuit and the scanning signal line driving circuit includes the shift register according to claim 1 or 2, wherein the first or second clock signal is used as the clock signal. Display device. 4. The image display device according to claim 3, wherein the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate. 5. The image display device according to claim 3, wherein the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element made of a polycrystalline silicon thin film transistor. The image according to any one of claims 3 to 5, wherein the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element manufactured at a process temperature of 600 degrees or less. Display device.

Images