JP2004064648A - Packet processing method and apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packet processing method and apparatus which dispenses with high-performance CPUs prepared expressly for extracting information required for generating a new transmitting packet header and generating the transmitting packet header respectively. <P>SOLUTION: Packet analytic elements 100a, 100b-100N are configured in pipelines as many as the number corresponding to a kind of a received packet and/or packet analysis contents assigned in advance, the kind of the received packet is judged by comparing a data portion corresponding to the header with comparison information at a fixed cycle, a search table 40 is retrieved, and data corresponding to the header are updated as needed and outputted to the next stage. At the same time, the analysis result is succeeded to elements 100 on the next stage when the elements 100 on the next stage use the analysis result. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a packet processing method and apparatus for mounting a newly generated header in a transmission packet in accordance with a header mounted in a reception packet, and more particularly, to a network for processing header analysis of a packet corresponding to a plurality of protocols at high speed. The present invention relates to a packet processing method and apparatus suitable for use in a LAN switch.
[0002]
[Prior art]
In the field of digital communication, packet communication is widely used for transferring information. At the head of the packet, a header indicating information on the transmission destination, the type of information, and the like is mounted, and a different header is provided for each type of packet (protocol).
[0003]
FIGS. 14A to 14H show examples of packets widely used in recent years. Packets are classified by type.
(A) DIX packet described in RFC194,
(B) RAW packet described in IEEE802.3,
(C) an LLC packet carrying the LLC information 405 described in IEEE 802.2;
(D) LLC + SNAP packet
And VLAN information 407 described in IEEE 802.1Q in the above four types of packets
(E) DIX + VLAN packet,
(F) RAW + VLAN packet,
(G) LLC + VLAN packet,
(H) LLC + SNAP + VLAN packet
And the packet processing apparatus is required to process these eight types of packets accurately and promptly.
[0004]
The Layer2 header (hereinafter, L2 header) of each packet includes MAC-DA information (destination MAC address) 401, MAC-SA information (source MAC address) 402, Type information 403, Length information 404, LLC information 405, SNAP Since the information 406 and the VLAN information 407 are mounted, and the L2 header is composed of a combination of the respective information, the length of the L2 header differs for each type of packet. In FIG. 14, such information is simply displayed as “MAC-DA”, “Type”, or the like.
[0005]
The packet has a payload 408 following the L2 header. In the case of an IPv4 packet, as shown in FIG. 15, Version information 701, header length information 702, TOS information 703, total length information 704, identification number Information 705, fragment information 706, TTL information 707, protocol number information 708, header checksum information 709, source IP address information 710, destination IP address information 711, and a Layer 3 header (hereinafter, L3 header) including option information 712. It is installed.
[0006]
In the case of a packet processing device having an IPv4 routing function, it is necessary to newly generate a transmission packet header in which the above-described MAC-DA information 401, MAC-SA information 402, TTL information 707, and header checksum information 709 have been rewritten. The newly generated MAC-DA information 401 needs to have a value corresponding to the transmission destination IP address information 711.
[0007]
Conventionally, as this type of device, a device having a configuration such as a packet processing device described in Japanese Patent Application Laid-Open No. 11-317783 shown in FIG. 13 has been used. In the figure, a register 350 is a memory for storing information of a head portion of a packet including a lower layer header and an upper layer header of the packet. The CPU 354 analyzes the received packet header stored in the register 350, and Information necessary for generating a transmission packet header included in the header is extracted and stored in a register 351, and a value corresponding to the information stored in the register 351 is stored in a register 352 with reference to a table 357 by a CPU 355. A new transmission packet header is generated by the CPU 356 according to the value stored in the register 352 and stored in the register 353. In order to transfer data between the registers 350, 351 and 352, the start of each program is determined while checking the flag register for writable or readable.
[0008]
[Problems to be solved by the invention]
As described above, since the lengths of the L2 header and the upper layer header differ depending on the type of each packet, the conventional packet processing apparatus extracts the destination IP address information 711 from the received packet and stores it in the register 351. In addition, the CPU 354
A processing step for reading the L2 header;
A processing step for determining the length of the read L2 header;
A processing step of detecting the position of the destination IP address information 711 according to the length of the obtained L2 header;
A processing step of reading the destination IP address information 711 from the detected position;
A processing step of storing the read destination IP address information 711 in the register 351;
Need to do it. Further, in the processing step of reading the L2 header, it is necessary for the CPU 354 to divide the L2 header into an amount of data that can be read at one time and to repeatedly read the data in several times.
[0009]
That is, the time required to detect the position of the destination IP address information 711 on the received packet depends on the amount of data that can be read by the CPU 354 at one time and the number of times that it can be read per unit time. Since the packet processing device requires the CPU 354 having higher performance, the cost of the product is increased. Similarly, the time required to write the transmission packet header to the register 353 depends on the amount of data that can be written by the CPU 356 at a time and the number of times that data can be written per unit time. Since the CPU 356 is required, the cost of the product is also increased (first problem).
[0010]
Further, between the CPUs 354, 355, and 356, the use of flag register information mounted in each of the registers 350, 351, 352, and 353 is notified and detected in a fixed cycle. For this reason, it is determined that the registers 350, 351, 352, and 353 are to be read, and an extra processing step other than the packet analysis is required, and the program size including the packet analysis is increased, that is, the program storage memory is also increased and the product This leads to high costs (second problem).
[0011]
Further, in the conventional device, the register 351 and 352 that can be connected to the table 357 are changed depending on the processing load, for example, because the register 350 for reception, the registers 351 and 352 that can be connected to the table 357, and the register 353 used for transmission are fixed. You cannot change it if you want to. For this reason, there is a demand for a packet processing device capable of processing a packet equipped with not only the above-mentioned IPv4 header but also various types of headers represented by an IPv6 header and MPLS, and a new protocol is defined every day. There is a need for a packet processing apparatus that can be easily modified and changed in the future, and has high flexibility in design change (third problem).
[0012]
Therefore, in view of the first problem described above, the present invention particularly prepares a high-performance CPU for each of the information extraction processing required to generate a new transmission packet header and the transmission packet header generation processing. An object of the present invention is to provide a packet processing device that does not need to be provided.
Another object of the present invention is to provide a packet processing device having a memory size necessary only for analysis of a received packet in view of the second problem described above.
In view of the third problem described above, the present invention also facilitates modification and future function changes for a received packet equipped with not only an IPv4 header but also various types of headers represented by an IPv6 header and MPLS. Therefore, it is an object of the present invention to provide a packet processing apparatus that is highly flexible in design change.
[0013]
[Means for Solving the Problems]
The invention according to claims 1 and 2
Search data for converting a header of a received packet into a header of a transmitted packet is stored in a search table,
Storing comparison information for determining the type of the received packet,
Detecting a data break of the received packet, separating a header equivalent data portion and a payload equivalent data portion,
The header-equivalent data portion separated by the packet separation step in a fixed cycle and stored in the comparison information storage step by a pipeline configuration of a number corresponding to the type of the received packet and / or the packet analysis content assigned in advance. The type of the received packet is determined by comparing the comparison information, and the search table is searched to update the header-equivalent data as necessary, and output to the next stage. When using, take over to the next stage,
The header-equivalent data from the last stage of the one or more packet analysis steps and the payload-equivalent data part separated by the packet separation step are sequentially combined and output as a transmission packet.
According to the first and second aspects of the present invention, processes such as identification of each field in a received packet header, extraction of search key information, and generation of a transmitted packet header after receiving a search result are performed according to the type of the received packet. Therefore, it is possible to select how many packet analysis elements are to be processed and what processing is to be performed by each packet analysis element, so that it is not particularly necessary to prepare a high-performance CPU.
[0014]
According to a third aspect of the present invention, each of the packet analysis elements includes:
A header data storage circuit that stores a header-equivalent data portion transmitted from the received packet separation unit and outputs a packet analysis start timing signal after completion of storage;
A memory for storing a packet analysis program executed by the packet analysis element;
A CPU and a special arithmetic unit that start executing a packet analysis program stored in the memory with a packet analysis start timing signal output from the header data storage circuit as a trigger,
After the fixed period, execution of the packet analysis program is completed, and a packet analysis completion timing signal is output to the next element or the updated packet transmission unit.
According to the configuration of the third aspect, since information transfer between the packet analysis elements of the pipeline configuration is also performed by a predetermined timing signal, no special flag (register) and processing are required. All can be assigned to individual packet analysis processes.
[0015]
The invention according to claim 4, wherein each of the packet analysis elements further includes:
A header edit storage circuit for extracting and storing different information from the header data storage circuit according to the packet analysis program, and for storing the comparison information and temporary data generated during execution of the program;
A header analysis result storage circuit that stores a packet analysis result obtained by executing the packet analysis program,
The data stored in the header analysis result storage circuit is output to the header analysis result storage circuit of the subsequent packet analysis element in synchronization with the packet analysis completion timing signal.
According to the configuration of the fourth aspect, when one or more packet analysis elements are used, the information extracted and analyzed by the preceding packet analysis element is not redundantly processed, so that the program load is reduced. The distribution can be flexibly handled, and the memory size for storing the program can be all allocated to individual packet analysis processing.
[0016]
The invention according to claim 5, wherein the header analysis result storage circuit comprises:
While the analysis of the current header is performed, the next packet is received and the analysis result of the next header is not overwritten with the analysis result of the next header. And stored alternately.
According to the configuration of claim 5, since the analysis result information of the current packet can be held even during reception of the next packet, the packet analysis result information can be transmitted to the subsequent packet analysis element without lowering the throughput.
[0017]
In the invention according to claim 6, the special operation unit includes:
Based on a special operation instruction included in the packet analysis program, data was directly determined in advance from any of the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit. It is configured to read in bit width units and perform various logical operations for packet analysis on the read data.
According to the configuration described in claim 6, the special arithmetic unit can directly read and write data in the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit. By changing the instruction order of the operation instructions, it is possible to implement a design change or add a function and maintain high-speed packet processing.
[0018]
The invention according to claim 7 is configured such that the special arithmetic unit further performs a logical operation of an immediate value included in the packet analysis program.
According to the configuration described in claim 7, it is possible to realize a design change and a function addition.
[0019]
The invention according to claim 8, wherein the special operation instruction directly reads any data of the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit. The configuration includes an access control signal for writing and various enable signals necessary for executing the instruction.
According to the configuration described in claim 8, information necessary for executing the special operation instruction can be directly read and written from the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit. An access control signal such as an address can be generated at the same time, and various enable signals required at the time of executing an instruction can be generated.
[0020]
In the invention according to claim 9, the header data storage circuit comprises:
A header is provided which alternately stores the header-equivalent data of each packet in a two-sided configuration including a side to be written during packet reception and a side analyzed by the CPU and the special arithmetic unit.
According to the configuration of claim 9, since the reception of the next packet can be started even during the analysis of the current packet, the header equivalent data is transmitted to the CPU and the special arithmetic unit in the packet analysis element while maintaining the wire speed, The data can be transferred to the header data storage circuit in the packet analysis element at the subsequent stage.
[0021]
The invention according to claim 10, further comprising a payload accommodating unit accommodating each payload-equivalent data portion of the plurality of received packets separated by the packet separating unit until the processing of the last-stage element is completed, The payload accommodating unit is configured to store the payload equivalent data of the plurality of packets in one payload data storage memory and manage the data by a pointer.
According to the configuration of the tenth aspect, since only one pointer corresponding to the header-equivalent data being analyzed in the packet is managed in one memory, each payload data of a plurality of received packets is accommodated. The device can be realized at low cost without requiring a memory.
[0022]
The invention according to claim 11, wherein the search key output by the one or more packet analysis elements to search the search table is selected and output to the search table, and the search is performed based on the search key. The apparatus further includes a search data selector for outputting a search result output from the table to the packet analysis element that has output the search key.
According to the configuration of claim 11, when the search data selector includes a plurality of packet analysis elements, the search data selector can receive a search key from any of the packet analysis elements, and the search result is output to any of the packet analysis elements. Can be transmitted, a plurality of packet analysis elements can access the search table, and the flexibility of the program processing is increased.
[0023]
According to a twelfth aspect of the present invention, the search data selector comprises:
A queue for responding to a difference in search time of each element with respect to the search table, storing search result data output from the search table in the queue, and outputting the data in response to an instruction from a packet analysis element serving as an output destination Configuration.
According to the configuration of the twelfth aspect, when the search data selector receives the search result data from the search table by FIFO, even if the response time of the search table changes, the search result is obtained at a timing when the packet analysis element is necessary. Can receive data.
[0024]
The invention according to claim 13 is characterized in that the update packet transmitting unit comprises:
When a transmission instruction is output from the packet analysis element at the last stage, the header-equivalent data is updated according to the rewrite / insert / delete instruction to the header data, and then combined with the subsequent payload-equivalent data from the payload accommodating unit. Send as a packet,
When a discard instruction is output from the packet analysis element at the last stage, it is not a pointer to be read that was to be combined with the payload equivalent data instructed to be discarded via the payload read control signal to the payload storage unit, The pointer to be read next is selected and held until the next read instruction.
According to the configuration of the thirteenth aspect, the updated packet transmitting unit, according to the analysis result of the packet analysis element, includes a header newly generated from the header equivalent data stored via the header data storage circuit. A new transmission packet can be generated from the payload equivalent data stored in the payload storage unit.
[0025]
According to a fourteenth aspect of the present invention, in the first-stage element, the header equivalent data stored in the header data storage circuit, the temporary data stored in the header edit storage circuit, and the header analysis result storage circuit A common sequential number is assigned to each packet for the three systems of data obtained as a result of the packet analysis and transferred to the last-stage element, and the three-system data of the same packet is transmitted to the last-stage element by the sequential number. The data is configured to be consistent.
According to the configuration described in claim 14, information extracted from one received packet for packet analysis passes through three routes, but is transmitted with a common sequential number assigned to each route. By mounting the comparison circuit for finally detecting the consistency in the packet analysis element, the reliability in the packet processing device can be improved.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The packet processing apparatus according to the present invention shown in FIG. 1 schematically includes a received packet separation unit 10 and one or more packet analysis elements (hereinafter also simply referred to as elements) 100 (100a, 100b to 100N) configured by a pipeline. , A received packet payload accommodating unit (also simply referred to as a payload accommodating unit) 20, a search table 40, a search data selector 30, a comparison information storage circuit 50, and an update packet transmitting unit 60. Details are shown in FIGS.
[0027]
The reception packet separation unit 10 detects data breaks of the reception packet 1 having different formats, for example, as shown in FIGS. 14A to 14H, and separates the header-equivalent data 11 and the payload-equivalent data 12 from each other. To the packet analysis element 100 a and the payload accommodating unit 20.
[0028]
Each packet analysis element 100 stores the header-corresponding data 11 separated by the packet separation unit 10 and the data from the preceding element 100, analyzes the packet type, and updates the header. For example, when the eight types of packets shown in FIGS. 14A to 14H are determined, the first element 100a can be divided into two groups by determining the presence or absence of the VLAN information 407 and the like. Next, by determining the presence / absence of Length information 404 or the like in the second element 100b, the data can be further divided into two groups. Since the packet type can be specified, the element 100 may be composed of three elements. Further, if the number of packet types to be determined increases in the future, the amount may be increased after the third element 100c. Here, each element 100 is configured to execute packet analysis and header conversion processing at a fixed cycle, and to pass the analysis result to the subsequent element 100 when the analysis result is used by the next stage.
[0029]
The search table 40 stores search data for converting the header of the received packet 1 into the header of the transmitted packet, and stores, for example, the correspondence between the MAC-DA information 401 and the destination IP address information 711. The search data selector 30 outputs the search key data 171a, 171b to 171N extracted from any one or more of the packet analysis elements 100a, 100b to 100N to the search table 40 as the search key data 31. The search result data 41 corresponding to the search key data 31 transmitted from the table 40 is selected by the search data selector 30. Any one of the search result data 32a, 32b to 32N is determined in advance by the packet analysis elements 100a, 100b. To 100.
[0030]
Here, FIG. 2 shows the bus configuration in each element 100 in detail, and reference numerals 111, 112, 113, 141, 142 and 132 indicate that the data is transmitted on the bus. The comparison information storage circuit 50 previously stores, for example, comparison information for determining packet types as shown in FIGS. 14A to 14H and stores the comparison information in the CPUs 110 a, 110 b to 110 N in each element 100. CPUs 110a, 141b-141N as read data (111a, 111b-111N) and (141a, 141b-141N) in accordance with access control signals 112a, 112b-112N from the decoder and access control signals 132a, 132b-132N from the decoders 130a, 130b-130N, respectively. 110b to 110N and output to the special operation units 140a and 140b to 140N.
[0031]
The update packet transmitting unit 60 includes a header-equivalent data 11 to be updated according to an instruction from the packet analysis element 100N corresponding to the last stage among the one or more packet analysis elements 100a and 100b to 100N, and a transmission waiting packet output from the payload accommodating unit 20. The payload data 21 is sequentially combined and output.
[0032]
<Received packet separation unit 10>
The packet processing apparatus shown in FIG. 1 receives a variable length received packet 1 as shown in FIG. 14, and the received packet separating unit 10 converts the received packet 1 into a predetermined bit width such as 8 bits (bits), 16 bits, or 32 bits. The data is fetched and rearranged in units of data starting from the transmission destination MAC address (MAC-DA) 401 as shown in FIG. 14, and it is assumed that an L2 header and an upper header as shown in FIGS. 14 and 15 are included. The header-equivalent data 11 is separated into two pieces of data, a header-equivalent data 11 of a predetermined data length and a payload-equivalent data 12 other than the data length. 20 respectively.
[0033]
<Packet analysis element 100>
The header equivalent data 11 separated by the received packet separation unit 10 is stored in the packet analysis element 100a at the first stage. The packet analysis element 100 is composed of one or more pipelines, and when composed of one, the packet analysis element 100a = 100N. In the case of two or more, the header equivalent data 11 stored in each packet analysis element 100 is used. Output to the packet analysis elements 100b, 100c to 100N or the update packet transmitting unit 60 at the subsequent stage after a predetermined fixed period.
[0034]
When the packet analysis elements 100a, 100b to 100N store the header equivalent data 11, the packet analysis start timing signal for notifying that a bit string that can be analyzed by the packet analysis program among the header equivalent data 11 has been stored in the element 100. 152A, 152b to 152N are generated, and the packet analysis start timing signal 152a, 152b to 152N is used as a trigger to start executing the packet analysis program.
[0035]
In accordance with an access control signal from each packet analysis program, all packet analysis elements 100 are used in common to identify whether or not the information is required by the packet analysis program by comparing with information extracted from the header equivalent data 11 of the received packet 1. The comparison information storage circuit 50 generates comparison information required for the packet analysis program from the information stored and stored, thereby identifying and extracting data sequentially from the beginning of the data. The analysis is advanced to complete the execution of the packet analysis program for each packet analysis element 100, such as clarifying the format and extracting information from the search key data 31 and the search result data 41 as described later. The analysis result and header equivalent data 11 are passed to the packet analysis elements 100a, 100b to 100N (in one case, the same packet analysis element 100).
[0036]
The received packet payload accommodating unit 20 stores the payload equivalent data 12 from the received packet separating unit 10, and the header equivalent data 11, which is the other data separated from the received packet separating unit 10, is stored in one or more pipelines. Through the packet analysis elements 100a, 100b to 100N having the structure, the payload-equivalent data 12 is held until the update packet transmitting unit 60 reads the data.
[0037]
The transmission destination of the transmission packet 61 with the new header is determined by the analysis result by the packet analysis elements 100a and 100b to 100N and the search of the search table 40 as described above. At this time, the search data selector 30 outputs the search key data 31 extracted from the header equivalent data 11 by any of the packet analysis elements 100a, 100b to 100N, and outputs the search key data 31 to the search table 40. An entry (search result data) 41 corresponding to the key data 31 is transmitted to predetermined packet analysis elements 100a, 100b to 100N.
[0038]
<Update packet transmitting unit 60>
The update packet transmitting unit 60 reads the header equivalent data 11 to be updated according to the instruction from the packet analysis element 100N corresponding to the last stage among the packet analysis elements 100a and 100b to 100N under the control of the payload accommodating unit 20. When the final data is detected, the transmission-ready packet payload data 21 corresponding to the header-corresponding data 11 is read so as to be able to be sequentially combined, and the transmission packet 61 is output.
With the above-described configuration, various processes such as identification of each field in the header equivalent data 11, extraction of search key information, and generation of a new header after receiving a search result are processed by one or more packet analysis elements 100. , Or what processing to execute in each packet analysis element 100, that is, a packet analysis program to be executed can be selected.
[0039]
<< Detailed description of element 100 >>
The packet analysis elements 100a and 100b to 100N shown in FIG.
A received packet separation unit 10, header data storage circuits (simply referred to as header storage circuits) 150a, 150b to 150N (shown in detail in FIG. 5) for storing header-equivalent data 11 transmitted from the preceding element 100;
-Memories 120a, 120b to 120N storing a packet analysis program;
A CPU 110a that fetches, decodes, and executes each instruction of the packet analysis program stored in each of the memories 120a, 120b to 120N, and outputs special operation instruction instruction signals 115a, 115b to 115N from the fetched result; 110b to 110N,
Special operation instruction decode circuits (decoders) 130a, 130b to 130N (detailedly shown in FIG. 4) for decoding special operation instruction instruction signals 115a, 115b to 115N output from the CPUs 110a, 110b to 110N;
Special operation units 140a, 140b to 140N (detailed in FIG. 3) for executing the special operation instructions 133a, 133b to 133N decoded by the decoders 130a, 130b to 130N, respectively.
I have it.
[0040]
In the above configuration, when the header data storage circuits 150a, 150b to 150N can store a predetermined number of bits of the header-corresponding data 11, the packet analysis start timing signals 152a, 152b to 152N respectively output the special operation units 140a, 140b. To 140N. With this as a trigger, the CPUs 110a, 110b to 110N start executing the packet analysis program, and the special operation units 140a, 140b to 140N execute special operation instructions (special operation instruction decode signals 133a, 133b to 133N) in parallel. .
[0041]
At this time, the CPUs 110a, 110b to 110N use the access control signals 112a, 112b to 112N output to the header data storage circuits 150a, 150b to 150N to read the read data 111a, 111b to 111N and write data 113a, Writes 113b to 113N are performed, and the CPU 110a and 110b to 110N repeat transfer with the built-in general-purpose registers to execute various general-purpose operations. The decoders 130a, 130b to 130N decode the special operation instruction instruction signals 115a, 115b to 115N output from the CPUs 110a, 110b to 110N, respectively, and convert the special operation instructions 133a, 133b to 133N to the special operation units 140a, 140b to 140N. And the special operation data extraction access control signals 132a, 132b to 132N are generated and output to the header data storage circuits 150a, 150b to 150N and the comparison information storage circuit 50 via the bus.
[0042]
The header data storage circuits 150a, 150b to 150N respectively extract header extraction information from the stored header of the received packet 1 and output them as read data 141a, 141b to 141N via the bus to the special computing units 140a, 140b to 140N. . The comparison information storage circuit 50 extracts comparison information for comparison with the read data 141a, 141b to 141N (header extraction information) and outputs the same as read data 141a, b,... The special computing units 140a and 140b to 140N compare the header extraction information and the comparison information, and output state notification signals 142a and 142b to 142N, which are comparison result information, to the CPUs 110a and 110b to 110N. A packet to be transmitted to the subsequent packet analysis element 100 is determined according to the status notification signals 142a, 142b to 142N.
[0043]
Here, as shown in FIG. 14, the 19th and 20th bytes of the received packet 1 are any of the first two bytes of Type information, Length information or VLAN information. As a header extraction information, an access control signal 132a is output to the header data storage circuit 150a to extract the 19th and 20th bytes of the received packet 1, and a comparison information storage circuit is generated so as to generate 0800h indicating IPv4 as the comparison information. Similarly, when the match comparison result signal included in the status notification signal 142 indicates that the header extraction information and the comparison information match, the output from the header data storage circuit 150a is output from the access control signal 132a from the decoder 130a. Determines that received packet 1 is a DIX packet When the processing of the DIX packet is started from the packet analysis element 100 at the subsequent stage, and when a mismatch is indicated, the 19th and 20th bytes of the received packet 1 are the next two bytes of the Length information and the first two bytes of the VLAN information from the next time. A process for determining which one is started is started. Therefore, a plurality of formats of the received packet 1 can be determined, and a packet process according to the format of the determined received packet 1 can be performed.
[0044]
Although each packet analysis element 100 has a pipeline configuration, each has the same configuration and the same function. Therefore, by changing a packet analysis program mounted on each element 100, each packet analysis element 100 has the same configuration without changing hardware, and has a different configuration. Protocol header analysis can also be performed.
[0045]
With the above configuration, each packet analysis element 100 is simply compared with the configuration using only the general-purpose CPU 110. By combining the CPU 110 and the special operation unit 140, information is extracted from the header-equivalent data 11 and transferred to the general-purpose register built in the CPU. Since the necessary information can be directly extracted from the header data storage circuit 150 instead of the header analysis after that, the configuration is such that high-speed header analysis is possible.
[0046]
Further, each packet analysis element 100 needs to extract different information for each header data storage circuit 150 in accordance with the packet analysis program. Header editing storage circuits 170a, 170b to 170N as locations for storing temporary data generated during execution, and header analysis result storage circuits 160a, 160b to 160N for storing packet analysis results obtained by executing a packet analysis program. I do.
[0047]
For example, when the packet analysis element 100a analyzes the L2 header and the packet analysis element 100b analyzes the IP header, the normality of the MAC-DA 401 and the MAC-SA 402 shown in FIG. Depending on the values of the fields, it is possible to identify whether the received packet 1 is in the DIX format or the LLC + SNAP format.
[0048]
Therefore, the value "05DC" is stored in advance in the header edit storage circuit (also simply referred to as edit storage circuit) 170a, and the value "4" is stored in advance in the header edit storage circuit 170b. When the value “0800” is extracted from the header data storage circuit 150a, the packet analysis element 100a compares the value “05DC” stored in the header edit storage circuit 170a with the later-described magnitude comparison instruction of the special operation unit 140a. When it is determined that the value of “0800” extracted from the header data storage circuit 140a is large, the DIX format can be specified. As a result, the header analysis result storage circuit (also simply referred to as an analysis result storage circuit) 160a Write a value indicating that the format was "DIX".
[0049]
Then, in synchronization with the packet analysis completion timing signal 153a, the information of the header analysis result storage circuit 160a is written to the subsequent packet analysis element 100b to the header analysis result storage circuit 160b. “05DC” in the header edit storage circuit 170a is used only by the packet analysis program of the packet analysis element 100a, and the special operation unit 140b of the packet analysis element 100b uses “DIX” written in the header analysis result storage circuit 160b. Based on the format information, it is assumed that the IP header is mounted on the 15th and subsequent bytes, and the field of the 15th byte is “4” stored in the header edit storage circuit 170b in order to identify some values of the version information. "And" Match comparison ".
[0050]
With the above-described configuration, the information extracted and analyzed by the preceding packet analysis element 100N-1 is not duplicated and the analysis processing is not performed by the latter packet analysis element 100N, so that each packet analysis element 100 has an individual packet analysis program. System can be configured efficiently.
[0051]
Each of the header data storage circuits 150a, 150b to 150N of each element 100 shown in FIG. 1 stores the header-corresponding data 11 between predetermined fixed periods, and the packet analysis start timing signals 152a, 152b during the next fixed period. The CPU 110a, 110b to 110N and the special computing units 140a, 140b to 140N execute packet analysis processing in accordance with the respective packet analysis programs, starting from the base point of each of them, respectively. Processing.
[0052]
However, if packets can be received even during the packet analysis processing, the number of packets that can be processed per unit time increases, and the throughput improves. Therefore, even when there is a possibility that a packet may be received during the analysis of the header, the header data storage circuits 150a, 150b to 150N cause the CPUs 110a, 110b to 110N and the special arithmetic units 140a, 140b to 140N to respectively. The packet analysis completion timing signals 153a, 153b to 153N are received as a two-sided configuration so as not to overwrite the current analysis result being analyzed or the current analysis result being analyzed with the next analysis result obtained by newly analyzing the received packet 1. Plane and packet analysis plane are switched and selected alternately.
[0053]
According to the above-described configuration, the two sides of the header data storage circuits 150a, 150b to 150N are selected in a predetermined order for each packet analysis completion timing signal 153a, 153b to 153N and the information is held, so that the CPUs 110a, 110b to 110N and Even when the special computing units 140a, 140b to 140N are extracting information necessary for packet analysis, the newly received information can be stored without losing the information including the header of the previously received packet 1 already stored. Can be.
[0054]
<Detailed description of special computing unit 140>
As shown in detail in FIG. 3, the special operation unit 140 (140a to 140N) directly receives the special operation control unit 145, the special operation data control signal 141 and the special operation instruction decode signal 133 from the special operation instruction decode circuit 130, and Arithmetic operation unit group 146 that performs various processes on data 141 read out from header data storage circuit 150, header analysis result storage circuit 160, header edit storage circuit 170, and comparison information storage circuit 50 in predetermined bit width units. And a status notification unit 147 and a special calculation result data output unit 148. The operation unit group 146 receives a one-to-many match comparison unit 1461, a magnitude comparison unit 1462, a data transfer unit 1463, a partial data transfer unit 1464, a It includes a product section 1465, a logical sum section 1466, an adder section 1467, a bit shift section 1468, a bit-shifted logical sum section 1469, a checksum operation section 1470, and an indirect address data transfer section 1471.
[0055]
The one-to-many match comparison section 1461 includes first data and second data (a header data storage circuit 150, a comparison information storage circuit 50, a comparison information storage circuit 160, and an analysis result storage circuit 160) forming the special operation data control signal 141 (141a to 141N). The first data and the second data are compared at the beginning, and consecutive data are simultaneously compared. The magnitude comparison unit 1462 determines whether the first data is large or the second data is large for the bit width specified by the bit mask signal 1332 for the first data and the second data, respectively. Compare according to 1334. The data transfer unit 1463 transfers the extracted first data from one of the storage circuits 150, 50 to another storage circuit 50, 150, and the partial data transfer unit 1464 uses the bit mask signal 1332 of the first data. Only the designated bit width is transferred to different storage circuits 50 and 150.
[0056]
The logical product unit 1465, the logical sum unit 1466, and the adder unit 1467 perform logical sum, logical product, and addition of the first data and the second data, respectively. The bit shift unit 1468 performs a bit shift on the first data to the right or left indicated by the bit shift direction instruction signal 1333 by the number of bits specified by the second data. After the bit shift, the OR unit 1469 performs a logical OR of the data obtained by bit-shifting the first data by the number of bits specified by the immediate data 1335 in the direction indicated by the bit shift direction instruction signal 1333 by a combination operation. In the checksum operation unit 1470, the first data (first operand) represents a head pointer (origin), and the data length specified by the second data (second operand) is added over a plurality of clocks. The indirect address data transfer unit 1471 transfers the data at the address indicated by the data output from any one of the storage circuits 150 and 50 specifying the second data as the address to the storage circuits 50 and 150 indicated by the first data.
[0057]
The state notifying unit 147 notifies the CPU 110 of the state of the comparison result executed by one of the comparison instructions (1461, 1462) in the operation unit group 146 and the packet analysis start timing signal 152 output from the header data storage circuit 150 to the CPU 110. Generated as a signal 142. The special operation result data output unit 143 generates write data 143 to be written to an address specified via the decode circuit 130 by an instruction (1463-1471) other than the comparison in the arithmetic unit group 146, and writes this to the header storage circuit 150. .
[0058]
With the above-described configuration, the special operation unit 140 is not the operation unit group 146 that only analyzes the headers illustrated in FIGS. 14 and 15. Can be used by changing the program, and the data can be directly extracted from the header data storage circuit 150, the header analysis result storage circuit 160, the header edit storage circuit 170, and the comparison information storage circuit 50 without taking the data into the CPU 110. A program can be executed while maintaining packet processing. Further, by outputting the status notification signal 142 to the CPU 110, packet analysis can be performed by a program to be executed next using branching of a program and comparison result determination.
[0059]
<Detailed Description of Special Operation Instruction Decode Circuit 130>
As shown in detail in FIG. 4, in the special operation instruction decoding circuit 130 constituting the decoder 130 in FIG. 1, the instruction instruction analysis unit 131 performs the read operation on the header data included in the special operation instruction instruction signal 115 from the CPU 110. The read address generation of information to be extracted from the storage circuit 150, the header editing storage circuit 170, or the comparison information storage circuit 50, and the special operation execution result (write data) 143 are stored in the header data storage circuit 150, the header analysis result storage circuit 160, and the header. As one of the write destination addresses of the edit storage circuit 170, three addresses of a first address 1321, a second address 1323, and a third address 1325, and first and second addresses corresponding to the addresses 1321, 1323, and 1325, respectively. , Third write or read enable signal 13 The special-operation data extraction access control signal 132 including 2, 1324, and 1326, the enable instruction signal 1331 for each instruction necessary for executing the special operation instruction, the bit mask signal 1332, and the bit shift direction instruction signal 1333 are compared in magnitude. The special operation instruction decode signal 133 including the direction instruction signal 1334 and the immediate data 1335 of the operand of the instruction described in the program can be output.
[0060]
With the above-described configuration, the special operation unit 140 includes a plurality of operation unit groups 146, but can perform a plurality of operations with a common interface.
[0061]
<Detailed Description of Header Data Storage Circuit 150>
As shown in detail in FIG. 5, the header data storage circuit 150 includes a header register write select circuit 156, a two-sided header register 157, a packet analysis timing generation circuit 154, a header register read select circuit 158, a header register pointer And a selection unit 159.
[0062]
The header register write select circuit 156 detects that the header equivalent data 11, the write data 113 from the packet analysis CPU 110 or the write data 143 (143a to 143N) from the special operation unit 140 has been input, and has a two-sided configuration. The write pointer 1561 is generated by selecting the write destination register side of the header register 157, and this is output to the header register 157. The header register 157 has a two-sided configuration including a side written during packet reception and a side analyzed by the CPU 110 and the special operation unit 140, and stores the header equivalent data 11 alternately by a packet analysis plane selection signal 1541 described later. .
[0063]
The packet analysis timing generation circuit 154
It is special that the header-corresponding data 11 of a predetermined number of bits is written to the header register 157 by using the input data detection notification signal 1562 generated from the header register write select circuit 156 as a trigger only when the header-corresponding data 11 is detected. A packet analysis start timing signal 152 to be notified to the arithmetic unit 140;
A packet analysis plane selection signal 1541 for selecting the reception packet write side and packet analysis (read) side of the header register 157;
A packet analysis completion timing signal 153 indicating the data transfer timing of the storage circuit 150 to the subsequent packet analysis element 100;
Generate.
[0064]
The header register read select circuit 158 generates a head register read pointer 1581 based on the data of the header register 157 with the packet analysis completion timing signal 153 from the packet analysis timing generation circuit 154, and reads the data stored in the header register 157. . The header register pointer selection unit 159 generates the pointer information for accessing the header register 157 output from the CPU 110 to generate the header extraction information and the read or write enable signal 112, or generates the header extraction information from the special operation unit 140. The pointer information for accessing the header register 157 and the read or write enable signal 132 output to the header register 157 or the header register read / select circuit 158 for determining whether or not the packet is being analyzed are selected. Output.
[0065]
The header data storage circuit 150 having the above configuration will be described with reference to FIG. FIG. 11 shows an example in which the number of packet analysis elements 100 is three (#a, #b, #c) with respect to the packet length that can be stored only in the header data storage circuit 150. When the header-equivalent data H of the received packet 1 is detected, the header register 157 is sequentially selected from the pointer 0 according to the write pointer 1561 from the header register write select circuit 156 in a predetermined bit width unit. The data H corresponding to the first header is stored in the plane-1.
Here, FIG. 11 shows only “H” as the header equivalent data, but “H + P # x” is actually the header equivalent data and has a “predetermined bit width”. The fixed time (fixed period) shown in FIG. 11 is “H + P # x” + α (α: minimum gap between packets of the Ethernet (R) standard). In FIG. 12, the data corresponding to the header is "H + P # x (part)", and the data corresponding to the payload is "P # x (remaining)".
[0066]
When the packet data storage in the header register 157 is completed, the packet analysis start timing signal 152 is output from the packet analysis timing generation circuit 154 to the special operation unit 140, and this timing generation also indicates that a fixed time has elapsed. After this, a new packet can be received, and when the header register write / select circuit 156 detects the new header equivalent data H, it selects the selection surface-2 of the header register 157 for which packet storage has been completed, and Header equivalent data H can be stored.
[0067]
The packet analysis start timing signal 152 for the first header equivalent data H + P # x triggers the CPU 110 and the special computing unit 140 in the packet analysis element to perform analysis. By outputting a packet analysis completion timing signal 153 indicating that analysis has been completed to the analysis result storage circuit 160, the packet analysis element 100 at the next stage is notified that the transfer preparation is completed. By generating the packet analysis completion timing signal 153 (153a to 153N) within a fixed time, the fixed time triggered by the packet analysis start timing signal 152 generated from the packet analysis timing generation circuit 154 is periodically repeated, Pipeline order can be correctly maintained.
From the reception of the packet to the completion of the packet analysis, the processing of the first header equivalent data H selects the selection plane -1 by the packet analysis plane selection signal 1541, and generates the packet analysis completion timing signal 153 to select the header register. The data H corresponding to the first header that has been analyzed at −1 is transferred to the subsequent packet analysis element 100 as takeover data 151. At this time, the storage of the second header equivalent data H stored in the selection plane-2 is also completed, the packet analysis start timing signal 152 is output, and the above operation is repeated every fixed time.
[0068]
In addition, it is possible to achieve both packet reception and packet analysis while arbitrating the contention between the header-equivalent data H from the received packet separation unit 10 and the write or read from the CPU 110 or the special arithmetic unit 140 during packet analysis.
Although not shown in the figure, a flag indicating the end of the packet is written in the header storage circuit 150 when storing the data corresponding to the header and the data corresponding to the payload. Thus, whether to read the payload-equivalent data after the header-equivalent data is determined based on whether or not the packet end flag is detected.
[0069]
<< Detailed Description of Payload Housing Unit 20 >>
As shown in detail in FIG. 6, the payload accommodating unit 20 includes a payload data storage memory (also simply referred to as a memory) 22 for storing the payload equivalent data 12, a payload data writing circuit 23, a header corresponding pointer generation circuit 24, a pointer A holding circuit 25, a read pointer generation circuit 26, and a payload data reading circuit 27 are provided. The payload data writing circuit 23 generates an address for writing data to the payload data storage memory 22 and a write enable signal. The header corresponding pointer generation circuit 24 generates a write end pointer for each received packet in order to store (write) the payload equivalent data 12 in association with the header equivalent data 11 analyzed by the packet analysis element 100 at the time of generating the transmission packet. .
[0070]
The pointer holding circuit 25 is composed of a plurality of registers (for the received packets # 1, # 2 to #Y in the figure) in order to hold the pointer value for each received packet on one payload data storage memory 22. ing. The read pointer generation circuit 26 generates a pointer value from the pointer that has just finished reading from the pointer holding circuit 25 to the write end pointer based on the payload read control signal 62 from the update packet transmitting unit 60. The payload data reading circuit 27 generates an address and a read enable signal for reading the payload equivalent data 12 from the payload data storage memory 22 by using the payload reading control signal 62 from the update packet transmitting unit 60 as a trigger.
[0071]
The payload accommodation unit 20 having the above configuration will be described with reference to FIG. FIG. 12 shows an example in which the number of packet analysis elements 100 is three (#a, #b, #c) with respect to the length of a packet stored separately in the header data storage circuit 150 and the payload accommodating unit 20. The received packet 1 is separated into a header equivalent data H (actually “H + P # x (partial)”) and a payload equivalent data P (actually “P # x (remaining)”) by the received packet separation unit 10. When the payload data writing circuit 23 detects the payload-equivalent data P, an address and a write enable signal are generated in order to write to the payload data storage memory 22 in a predetermined bit width unit, and are written in order from address 0.
[0072]
When the payload data P # 1 has been written into the payload data storage memory 22, the header corresponding pointer generation circuit 24 extracts the address value at the end of the writing in order to store that the payload data is the payload data of the first header equivalent data H. Then, the data is stored (written) into the register for the first header equivalent data of the pointer holding circuit 25. Subsequently, the payload-equivalent data P # 2 of the second header-equivalent data is written from the address value +1 at the end of the writing of the first payload-equivalent data P # 1, and the address value at the end of the writing is used for the second header-equivalent data. The data is stored in the register of the pointer holding circuit 25. The third payload equivalent data P # 3 is similarly stored.
[0073]
When the analysis of the first header equivalent data H by the packet analysis elements #a, #b, and #c is completed, the packet analysis element #c transfers the packet to the header edit storage circuit 170c to the destination of the result obtained from the table search. An instruction to discard or discard the packet, or an instruction to insert or delete a VLAN, for example, is written, and in synchronization with the packet analysis completion timing signal 153c, the header control data 172N and the new header data 151N are updated together with the updated packet transmission unit 60. Output to
[0074]
The update packet transmitting unit 60 performs packet update processing such as insertion or deletion into new header data. If the flag indicating the end of the packet cannot be detected when the processing of the updated header data is completed to the end, the data corresponding to the following payload exists and is combined into one packet. A payload read control signal 62 is output.
[0075]
In accordance with the control signal 62, the read pointer generation circuit 26 reads the first header stored in the pointer holding circuit 25 from the pointer 0 via the payload data read circuit 27 so that the first payload equivalent data subsequent to the first header equivalent data can be read. An address up to the write end pointer value of the corresponding data is instructed to the payload data storage memory 22, and the data is read. When reading to the write end pointer value stored in the pointer holding circuit 25 is completed, the read pointer generation circuit 26 stores the address at that time and holds it until the next time the payload read control signal 62 is received.
When the packet discard instruction is included in the header control data 172N, the read pointer generation circuit 26 shown in FIG. 6 selects the pointer holding value to be read next without reading the payload equivalent data 12 as the control signal 62. .
[0076]
<< Detailed Description of Search Data Selector 30 >>
As shown in detail in FIG. 7, the search data selector 30 includes a search key selection unit 33, a search result transmission unit 34, and a search result reception FIFO (queue) 35. The search key selection unit 33 receives the search key data 171 output from any one of the packet analysis elements 100a, 100b to 100N, and stores the search key data 171a, 171b to 171N (any one) in the search table 40. Output. The search result sending unit 34 receives the search result 41 from the search table 40 via the FIFO 35, and converts the search results 32a, 32b to N corresponding to the search key data 171 into the designated packet analysis elements 100a, 100b to 100N. Output to
[0077]
With the above-described configuration, the search data selector 30 is necessary for a program that only analyzes a MAC address and a program that also analyzes an IP header and an upper header, for example, when individual analysis is performed for each packet analysis element 100. Since the number of packet analysis elements changes, the search key data 171 is not always fixedly output from the determined packet analysis element 100, and a packet analysis program for generating the search key data 171 based on information obtained by packet analysis is implemented. The search key data 171 from the packet analysis element 100 is selected and output to the search table 40. Also, the search result data 32 corresponding to the search key data 171 is output only to the packet analysis element 100 used for generating a new header.
[0078]
Further, the search result data 41 output from the search table 40 is stored in the search result reception FIFO 35, and the search result data 32 is not output until an instruction is given from the packet analysis element 100 as an output destination. For example, when generating an update header in the packet analysis elements 100a, 100b, and 100c, the search key data 171 is transmitted from the packet analysis element 100b, and the search result data 32 is required in the element 100c. It is possible to cope with processing time delays and differences in search times due to the multiple search key data 171.
[0079]
<< Detailed Description of Update Packet Transmitter 60 >>
As shown in detail in FIG. 8, the update packet transmitting unit 60 includes a control signal generating unit 63 that generates a payload read control signal 62 and a packet generating unit 64. The packet generation unit 64 issues an instruction to insert into header data output from the packet analysis element 100N (a = N in the case of one packet analysis element), which is the final stage among the one or more packet analysis elements 100a and 100b to 100N. In accordance with a signal 1721N, a delete instruction signal 1722N from the header data, a header control data 172N including a transfer or discard instruction signal 1723N, the header-equivalent data 151N to be updated, and the transmission-waiting packet payload data 21 read from the payload accommodating unit 20 are updated. Combine with cereal.
[0080]
With the above-described configuration, the update packet transmitting unit 60 synchronizes with the packet analysis completion timing signal 153 from the packet analysis element 100N, and takes over the takeover header data 151N, the insertion instruction signal 1721N from the header edit storage circuit 170N into the header data, and the header. The header control data 172N including the data deletion instruction signal 1722N and the transfer or discard instruction signal 1723N is received. The takeover header data 151N is updated to a new header by various instruction signals, and if necessary, the transmission-waiting packet payload data 21 is combined and output as a transmission packet 61.
[0081]
<< Modified Example of Packet Analysis Element 100 >>
In the modified example of the packet analysis element 100 shown in FIG. 9, sequential number comparison circuits (also simply referred to as comparison circuits) 180N and 181N are added to the configuration shown in FIG.
[0082]
In order to analyze the header of the received packet 1, the sequential number comparison units 180N and 181N store the search key data 171 of the table search via the header data storage circuit 150, the header analysis result storage circuit 160, and the header edit storage circuit 170. Since one piece of received packet information is transmitted through three paths of sending and receiving a search result, the first-stage packet analysis element is used to detect that information of the same received packet is not aligned due to a failure in any one of the paths. A sequential number is assigned from the packet analysis program 100a, and the sequential number 162N transmitted via the header analysis result storage circuit 160 and the sequential number transmitted via the header data storage circuit 150 are assigned to the last stage of the packet analysis element 100. With number 1571N Compare results, and outputs two kinds of comparison result of the header analysis result storage circuit 160 compares the sequential number 173N transmitted in sequential number 162N and the search table 40 which is transmitted via the result.
[0083]
A transfer image of the sequential numbers having the above configuration will be described with reference to FIG. When the number of packet analysis elements 100 is three (#a, #b, #c), the search data selector 30 outputs the search key data 171a by the element 100a and receives the search result 32c by the element 100c. When the packet analysis program of the packet analysis element 100a writes the analysis result of the received packet 1 to the header analysis result storage circuit 160a, the sequential number #A also writes to the header analysis result storage circuit 160a. The sequential number #A is similarly written in the header data storage circuit 150a storing the header equivalent data based on this analysis result.
[0084]
Then, the sequential number #A is also written and transferred to the search key data 171 generated based on the information extracted from the header equivalent data 12 via the header edit storage circuit 170a. These sequential numbers #A are synchronized with the packet analysis completion timing signal 153a, the header data storage circuit 150a combines the header equivalent data 11 with the header data storage circuit 150b, and the header analysis result storage circuit 160a stores the analysis result information. One of them is transferred to the analysis result storage circuit 160b, and the header edit storage circuit 170a does not directly transfer it to the edit storage circuit 170b, but transfers it as search key data 171 to the search table 40. In the search result data 32 corresponding to the search key data 171, the sequential number #A multiplexed in the search key data 171 is stored in the header edit storage circuit 170c of the packet analysis element 100c. And outputs the #A value from the table route sequential number 173c.
[0085]
As described above, the elements 100a to 100b and the elements 100b to 100c take over between the elements 100 in synchronization with the packet analysis completion timing signal 153, and output the #A value from the sequential number 1571N of the path of the header data storage circuit 150. I do. The #A value is output from the sequential number 162N of the header data analysis result storage circuit 160 path. By comparing the sequential numbers of these routes, it is possible to detect that one packet information is normally transferred on three routes because all of them have the #A value.
[0086]
【The invention's effect】
As described above, according to the configuration of the first and second aspects, processes such as identification of each field in a received packet header, extraction of search key information, and generation of a transmission packet header after receiving a search result are received. Since it is possible to select the number of packet analysis elements to be processed according to the type of packet and the type of processing to be performed by each packet analysis element, it is not necessary to prepare a particularly high-performance CPU.
According to the configuration of the third aspect, since information transfer between the packet analysis elements of the pipeline configuration is also performed by a predetermined timing signal, no special flag (register) and processing are required. All can be assigned to individual packet analysis processes.
According to the configuration of the fourth aspect, when one or more packet analysis elements are used, the information extracted and analyzed by the preceding packet analysis element is not redundantly processed, so that the program load is reduced. The distribution can be flexibly handled, and the memory size for storing the program can be all allocated to individual packet analysis processing.
According to the configuration of claim 5, since the analysis result information of the current packet can be held even during reception of the next packet, the packet analysis result information can be transmitted to the subsequent packet analysis element without lowering the throughput.
According to the configuration described in claim 6, the special arithmetic unit can directly read and write data in the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit. By changing the instruction order of the operation instructions, it is possible to implement a design change or add a function and maintain high-speed packet processing.
According to the configuration described in claim 7, it is possible to realize a design change and a function addition.
According to the configuration described in claim 8, information necessary for executing the special operation instruction can be directly read and written from the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit. An access control signal such as an address can be generated at the same time, and various enable signals required at the time of executing an instruction can be generated.
According to the configuration of claim 9, since the reception of the next packet can be started even during the analysis of the current packet, the header equivalent data is transmitted to the CPU and the special arithmetic unit in the packet analysis element while maintaining the wire speed, The data can be transferred to the header data storage circuit in the packet analysis element at the subsequent stage.
According to the configuration of the tenth aspect, since only one pointer corresponding to the header-equivalent data being analyzed in the packet is managed in one memory, each payload data of a plurality of received packets is accommodated. The device can be realized at low cost without requiring a memory.
According to the configuration of claim 11, when the search data selector includes a plurality of packet analysis elements, the search data selector can receive a search key from any of the packet analysis elements, and the search result is output to any of the packet analysis elements. Can be transmitted, a plurality of packet analysis elements can access the search table, and the flexibility of the program processing is increased.
According to the configuration of the twelfth aspect, when the search data selector receives the search result data from the search table by FIFO, even if the response time of the search table changes, the search result is obtained at a timing when the packet analysis element is necessary. Can receive data.
According to the configuration of the thirteenth aspect, the updated packet transmitting unit, according to the analysis result of the packet analysis element, includes a header newly generated from the header equivalent data stored via the header data storage circuit. A new transmission packet can be generated from the payload equivalent data stored in the payload storage unit.
According to the configuration described in claim 14, information extracted from one received packet for packet analysis passes through three routes, but is transmitted with a common sequential number assigned to each route. By mounting the comparison circuit for finally detecting the consistency in the packet analysis element, the reliability in the packet processing device can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a basic configuration of a packet processing device according to the present invention.
FIG. 2 is a block diagram showing a bus configuration in the packet analysis element of FIG. 1 in detail;
FIG. 3 is a block diagram showing a special operation unit in FIG. 1;
FIG. 4 is a block diagram showing a special operation instruction decode circuit in FIG. 1;
FIG. 5 is a block diagram showing a header data storage circuit in FIG. 1;
FIG. 6 is a block diagram showing a received packet payload accommodating unit in FIG. 1;
FIG. 7 is a block diagram showing a search data selector in FIG. 1;
FIG. 8 is a block diagram showing an update packet transmitting unit in FIG. 1;
FIG. 9 is a block diagram showing a modified example in which a sequential number comparison circuit is added to the packet analysis element in FIG.
FIG. 10 is an image diagram showing a sequential number comparison in FIG. 9;
FIG. 11 is a processing timing diagram when a minimum packet length and a minimum inter-packet gap are used by using three packet analysis elements according to the present invention.
FIG. 12 is a processing timing diagram when three packet analysis elements according to the present invention are used, and an arbitrary packet length and a gap between arbitrary packets are used.
FIG. 13 is a block diagram showing a conventional packet processing device.
FIG. 14 is a diagram showing a configuration of a lower layer header of a conventional packet.
FIG. 15 is a diagram showing a configuration of a conventional IPv4 header.
[Explanation of symbols]
1 Received packet
10 Received packet separation unit
11 Header equivalent data
12 payload equivalent data
20 Received packet payload storage
21 Transmission waiting packet payload data
22 Payload data storage memory
23 Payload data writing circuit
24 Header-compatible pointer generation circuit
25 Pointer holding circuit
26 Read Pointer Generation Circuit
27 Payload data read circuit
30 Search data selector
40 Search Table
50 Comparison information storage circuit
60 Update packet transmission unit
61 Transmission packet
62 Payload read control signal
63 Payload read control signal generator
64 packet generator
100, 100a, b, ..., N packet analysis elements
110a, b,..., N CPU
.., N CPU read data from the storage circuits 150 and 50
112a, b,..., N Storage circuits 150, 50 access control signals from CPU
113a, b,..., N Write data from storage circuits 150, 50 from CPU
115a, b, ..., N special operation instruction instruction signal
120a, b,..., N CPU program storage memory
130a, b, ..., N special operation instruction decode circuit (decoder)
131 Instruction instruction analysis unit
132a, b, ..., N Special operation data extraction access control signal
133a, b, ..., N special operation instruction decode signal
140, 140a, b, ..., N special operation unit
141, 141a, b,..., N Special operation data control signal (read data from header data storage circuit 150 and comparison information storage circuit 50 of special operation unit)
142a, b, ..., N status notification signal
143, 143a, b,..., N Write data to the storage circuits 150 and 50 of the special operation unit
145 Special operation control unit
146 arithmetic unit group
147 Status notification unit
148 Special operation result data output unit
150, 150a, b,..., N Header data storage circuit
151a, b, ..., N-element inherited header data
152, 152a, b,..., N Packet analysis start timing signal
153, 153a, b,..., N Packet analysis completion timing signal
154 Packet analysis timing generation circuit
156 Header register write select circuit
157 Header register
158 Header register read select circuit
159 Header register pointer selection unit
160, 160a, b,..., N Analysis result storage circuit
161a, b, ..., N element takeover analysis result data
162N Header analysis result storage circuit path sequential number
170, 170a, b,..., N Header edit storage circuit
171, 171a, b, ..., N search key data
172a, b, ..., N header control data
1331 Enable instruction signal for each instruction
1332 bit mask signal
1333 bit shift direction instruction signal
1334 Size comparison direction instruction signal
1335 immediate data
1321 (for special operation) First address
1322 (for special operation) 1st write or read enable
1323 (for special operation) 2nd address
1324 (for special operation) 2nd write or read enable
1325 (for special operation) 3rd address
1326 (for special operation) 3rd write or read enable
1461 One-to-many match comparison unit
1462 large and small comparison section
1463 Data transfer unit
1464 Partial data transfer unit
1465 AND
1466 OR
1467 Adder
1468 bit shift section
OR section after 1469 bit shift
1470 Checksum calculation unit
1471 Indirect address data transfer unit
1541 Packet analysis plane selection signal
1561 Header register write pointer
1571 Header data storage circuit path sequential number
1581 Header register read pointer
1721 Header insertion instruction data
1722 Header deletion instruction data
1723 Packet transfer discard instruction signal
173N search table route sequential number

Claims (14)

A search data storing step of storing search data for converting a header of a received packet into a header of a transmitted packet in a search table;
A comparison information storage step of storing comparison information for determining the type of the received packet;
A received packet separation step of detecting a data segment of the received packet and separating a header equivalent data portion and a payload equivalent data portion;
A pipeline is formed with a number corresponding to the type of the received packet and / or a packet analysis content assigned in advance, and the header-equivalent data portion separated by the packet separation step at a fixed period and stored by the comparison information storage step. The type of the received packet is determined by comparing the comparison information, and the search table is searched to update the header-equivalent data as necessary, and output to the next stage. One or more packet analysis steps to take over to the next stage if used;
An update packet transmission step of sequentially combining the header-equivalent data from the last stage of the one or more packet analysis steps and the payload-equivalent data part separated by the packet separation step and outputting the combined data as a transmission packet;
Provided packet processing method. A search table for storing search data for converting a header of a received packet into a header of a transmitted packet;
A comparison information storage unit that stores comparison information for determining the type of the received packet;
A reception packet separation unit that detects a data segment of the reception packet and separates a header equivalent data portion and a payload equivalent data portion;
A pipeline is formed with a number corresponding to the type of the received packet and / or a packet analysis content allocated in advance, and the header-equivalent data portion separated by the packet separation step at a fixed period and stored by the comparison information storage step. The type of the received packet is determined by comparing the comparison information, and the search table is searched to update the header-equivalent data as needed, and output to the next stage. One or more packet analysis elements that take over to the next stage when used,
An update packet transmitting unit that sequentially combines the header-equivalent data from the last stage of the one or more packet analysis elements and the payload-equivalent data part separated by the packet separation unit and outputs the combined data as a transmission packet;
Equipped with a packet processing device. Each of the packet analysis elements comprises:
A header data storage circuit that stores a header-equivalent data portion transmitted from the received packet separation unit and outputs a packet analysis start timing signal after completion of storage;
A memory for storing a packet analysis program executed by the packet analysis element;
A CPU and a special arithmetic unit that start executing a packet analysis program stored in the memory with a packet analysis start timing signal output from the header data storage circuit as a trigger,
The packet processing device according to claim 2, wherein after the fixed period, the execution of the packet analysis program is completed, and a packet analysis completion timing signal is output to a next element or an updated packet transmitting unit. Each of the packet analysis elements further comprises:
A header edit storage circuit for extracting and storing different information from the header data storage circuit according to the packet analysis program, and for storing the comparison information and temporary data generated during execution of the program;
A header analysis result storage circuit that stores a packet analysis result obtained by executing the packet analysis program,
3. The packet processing device according to claim 2, wherein the data stored in the header analysis result storage circuit is output to a header analysis result storage circuit of a subsequent packet analysis element in synchronization with the packet analysis completion timing signal. The header analysis result storage circuit,
While the analysis of the current header is performed, the next packet is received and the analysis result of the next header is not overwritten with the analysis result of the next header. 5. The packet processing apparatus according to claim 4, wherein the packet processing is switched and stored alternately. The special computing unit is
Based on a special operation instruction included in the packet analysis program, data was directly determined in advance from any of the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit. The packet processing apparatus according to claim 3, wherein the packet processing apparatus reads data in bit width units and performs various logical operations for packet analysis on the read data. The packet processing apparatus according to claim 3, wherein the special operation unit further performs a logical operation on an immediate value included in the packet analysis program. The special operation instruction includes:
An access control signal for directly reading and writing data in any of the header data storage circuit, the header analysis result storage circuit, the header edit storage circuit, and the comparison information storage circuit; The packet processing device according to claim 6, further comprising an enable signal. The header data storage circuit includes a header register for alternately storing the header-equivalent data of each packet in a two-sided configuration including a side written during packet reception and a side analyzed by the CPU and the special arithmetic unit. The packet processing device according to claim 3, wherein: A payload accommodating unit for accommodating each payload-equivalent data portion of the plurality of received packets separated by the packet separating unit until the processing of the last-stage element is completed; The packet processing apparatus according to any one of claims 2 to 9, wherein the payload equivalent data is stored in one payload data storage memory and managed by a pointer. A search key output by the one or more packet analysis elements is selected to output the search table, and the selected search key is output to the search table. 11. The packet processing apparatus according to claim 2, further comprising a search data selector that outputs a search key to the packet analysis element that outputs a search key. The search data selector,
A queue for responding to a difference in search time of each element with respect to the search table, storing search result data output from the search table in the queue, and outputting the data in response to an instruction from a packet analysis element serving as an output destination The packet processing device according to claim 10, wherein The update packet transmitting unit,
When a transmission instruction is output from the packet analysis element at the last stage, the header-equivalent data is updated according to the rewrite / insert / delete instruction to the header data, and then combined with the subsequent payload-equivalent data from the payload accommodating unit. Send as a packet,
When a discard instruction is output from the packet analysis element at the last stage, it is not a pointer to be read that was to be combined with the payload equivalent data instructed to be discarded via the payload read control signal to the payload storage unit, 13. The packet processing apparatus according to claim 2, wherein a pointer to be read next is selected and held until a next read instruction. In the first stage element, there are three systems: header equivalent data stored in the header data storage circuit, temporary data stored in the header edit storage circuit, and packet analysis results stored in the header analysis result storage circuit. The same sequential number is assigned to data for each packet and transferred to the next-stage element, and the three-line data of the same packet is matched by the sequential number in the last-stage element. Item 13. The packet processing device according to any one of Items 2 to 12.

Images