JP3233353B2 - Header processing device and header processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a header processing apparatus and a header processing method for a packet, and more particularly to a header processing apparatus and a header processing method having a packet transfer means for processing a packet at a high speed.

[0002]

2. Description of the Related Art Conventionally, public telephone lines used to be analog voice communications. However, data communication has become popular since the beginning of the information age. In order to transmit data at high speed, the data is often transmitted in a packet format.

[0003] The header processing in the packet format consists in obtaining an output interface having a destination of the packet and in obtaining information for converting to a header suitable for the output interface. These operations are performed using various fields of the header and the forwarding table, and require a very large number of processing steps. For example, a multi-layer switch (which processes layers L2 and L3, which are higher layers of the physical layer,
Switch in one device or LSI chip. )), From the header of the L2 packet (MAC packet), the MAC (Media Access Control: Media Ac
cess Control) address, identifies which of the following four types of MAC formats it is, and from the header position determined according to the identification result, the L3 packet (I
P packet) and extract I from the header of the IP packet.
Take out the address of P.

Further, a test is performed to determine whether or not the MAC address is a predetermined address (router test). If not, a process of L2 is performed, and if it is a predetermined address, a process of L3 is performed. Depending on the identification result,
The L2 process is performed without performing the process of extracting the L3 packet. Regarding the router test, in the processing of L2 and L3,
A process of searching a forwarding table is performed. Since this forwarding table is generally quite large, the search process is very time consuming.

[0005] The four types of MAC formats are shown in FIG.
As shown in the above, there are four types of products: two standard formats, DIX standard also called Ethernet II and IEEE 802.3 standard, and two types of whether each has a virtual LAN identifier also called 802.1Q standard. is there. For example, in the combination of the DIX rule and the 802.1Q rule, the IP PDU and the VLAN ID are set extra than the DIX rule alone. When LAN emulation is standardized, the service emulates the existing Ethernet and token link LAN applications.
Connection at the AC level is mandatory. Furthermore, this MAC
An IP packet is a payload of the packet, and a payload of the IP packet is any of a TCP packet and a UDP packet.

[0006] As described above, since the content format of the packet header is clarified only by analyzing the packet header in order, it is unknown at the time of packet reception before the header analysis how much the packet header is. However, since the protocol to be handled is fixed, if the maximum header is assumed and this part, that is, a part of the packet that always includes the header (called a header possibility part) is extracted from the packet, unnecessary information is obtained. May be included, but the necessary information is not lost. Furthermore, it is necessary to appropriately process the search result and prepare for sending the packet to the destination. This preparation includes processes such as adding a packet to a queue for a destination, rewriting a packet header, and copying a packet.

The above-described header processing is sequentially performed by one CPU, thereby completing the processing of one packet. In order to increase the speed, it is necessary to perform this processing at high speed.

[0008] When a general-purpose CPU is used, hardware constituted by a logic circuit may require a function that can be executed in one step, that is, one clock, for two or more clocks.

For example, in a hardware logic circuit,
To add twice the contents of memory A and memory B and store them in memory C (C = 2 × A + 2 × B),
At the first clock, the memories A and B are simultaneously read out and put into the registers. At the second clock, the registers are shifted by one bit (doubling), added, and the result can be written into the memory C (special operation). ).

On the other hand, in the case of a general-purpose CPU, the memory A is read into a register by using the most basic operation such as addition and shift (referred to as a basic operation) (first clock), and
The memory B is read into the register (second clock), the register of the memory A is shifted by one bit (third clock), and the register of the memory B is shifted by one bit (fourth clock). (5th clock), and write the result to the memory C (6
Clock eye).

As shown in this example, the former requires two clocks and the latter requires six clocks, and hardware constituted by a logic circuit can process at higher speed than a general-purpose CPU. However, it is difficult to modify or change the hardware logic circuit or add a function in the future. Therefore, the hardware logic circuit lacks flexibility in design change. Conventionally, there has been a method of using a programmable dedicated CPU called a sequencer in order to improve the disadvantage of lacking flexibility in a hardware logic circuit, which has been used in fields such as signal processing.

Both the sequencer and the general-purpose CPU generally have RO
Having a program stored in the M / RAM, the contents (instructions) of the address pointed to by a pointer called a program counter are extracted, and the instructions are decoded (decoded).
A decode signal is output, and an arithmetic circuit receiving the decode signal operates.

However, in the sequencer, the arithmetic circuit is specially made. For example, the operation of doubling the contents of the registers A and B and adding the contents is one.
An operation such as that performed by a clock can be incorporated.
Therefore, the calculation is performed faster than the general-purpose CPU. In a signal processing sequencer, a calculation of a linear function such as Y = AX + B using X and Y as variables and A and B as parameters is set as an arithmetic circuit. However, there was no sequencer to process the header of the packet.

[0014]

The first problem of the above-mentioned prior art is that header processing can be performed in an orderly manner and can be performed concurrently (independently) in a header processing. , All that had been done in order. Therefore, to increase the speed, it is necessary to increase the capacity of the general-purpose CPU.
Because the performance of U itself is improved, the cost is increased.

Further, when a large number of general-purpose CPUs are prepared and pipeline processing is performed, unless the number of pipelines is designed appropriately, the cost will increase. Or resources like forwarding tables become bottlenecks,
There is a possibility that the general-purpose CPU cannot make full use of its capabilities.

The second problem is that when a hardware logic circuit is used in place of a general-purpose CPU, there is a lack of flexibility in design change. On the other hand, there is a method using a programmable dedicated CPU called a sequencer, which has been used in fields such as signal processing. However, such a sequencer for performing packet header processing at high speed has not been disclosed yet.

The object of the present invention is to increase the speed of header processing of packets and the like up to a speed restricted by resources such as a forwarding table which becomes a bottleneck.
It is intended to be performed at low cost using a PU. Also,
It is an object of the present invention to realize a design change or a future function addition at a low cost while maintaining high speed by realizing packet header processing by a programmable hardware logic circuit, that is, sequence processing.

[0018]

In order to achieve the above object, the present invention extracts data of each field of a protocol header from a part of a packet including a header extracted from the packet, and stores the data in a designated storage location. First to enter
Means, performs a search in the data search key of the specified storage location, a second means for outputting the contents of the table entry that matches the search key, and outputs the contents of the second means the And third means for creating attribute information of the header update information from the destination of the packet from the data of the storage location , wherein the first to third means are respectively
At the beginning or end of a predetermined fixed time,
Which processing plan is within the current fixed time or within the next fixed time
It is an object of the present invention to provide a header processing device for determining whether to execute a program . In addition, the present invention
Part of the packet containing the header extracted from the packet
Extract the data of each field of the protocol header
First means for inputting to a designated storage location;
Performs a search using the data in the specified storage location as a search key.
Output the contents of the table entry that matches the search key.
Second means for inputting, and the output contents of the second means and the
From the data in the storage location, the destination of the packet and the header
And third means for creating attribute information of the update information.
The first to third means are each determined in advance.
Processing ends at an integral multiple of the number of instructions
Confirms completion or start of processing of other means at the start
Terminate or open in at least one other means.
If the start cannot be confirmed, execution of the instruction is suspended,
Wait for all means to end or start processing.
And a header processing device characterized by the following.
The present invention also provides a packet including a header extracted from a packet.
Each field of the protocol header from a portion of the
The first to extract the data of the data and input it to the specified storage location
And the data at the designated storage location as a search key
Search, and find the table entry that matches the search key.
Second means for outputting the re contents, the output of the second means
From the contents and the data in the storage location, the packet transmission
Third means for creating attribute information of destination and header update information
And, as the storage location in the first means,
Having one common part and two separate parts, the common part
Converts some or all of the field data into the second
Storage space that is shared by the means and the third means
The individual parts are the same as each individual part.
And each of the individual parts is stored in the second
And the third means are used independently.
This is to provide a header processing device that performs

According to the present invention , a first step of extracting data of each field of a protocol header from a part of a packet including a header extracted from the packet and inputting the data to a designated storage location, A second procedure of performing a search using the data of the storage location as a search key and outputting the contents of a table entry that matches the search key; and, based on the output content of the second procedure and the data of the storage location, possess a third step in creating the attribute information of the destination and the header update information of the packet, and the first to third individual steps
Is the beginning of a predetermined fixed time
At the end or at the current fixed time or at the next fixed time
The present invention provides a header processing method for determining which processing program is to be executed in a short time.

[Operation] In the packet header process, the following three processes mainly occupy most of the processing time. That is, as a first process, the structure of the header of a packet is clarified, and a field to be written in the header is extracted. As a second process, information of an address field,
In other words, determining the destination of the packet from the address,
The third process is to perform header conversion necessary for sending the packet to the destination of the packet.

FIG. 5 is a conceptual diagram showing the configuration of a CPU for performing such processing. In the case of the CPU, the CPU 10 includes an adder (+), a multiplier (×), registers R1, R2, R3, and an instruction decoder.
And an operating system OS 11 and a program 12. In the case of such a configuration, according to the example of the contents of the program 12, 3A + 3B
It takes 9 steps to get = D, but it is perfect for cost performance.

FIG. 2 is a conceptual diagram of a configuration based on a dedicated sequence. As a dedicated sequence, a sequencer 20 having an instruction decoder, function processing F1 (21),
F2 (22) and a program 23 for storing a procedure for operating the sequencer 20. In the case of such a configuration, since dedicated function processing means is provided, two steps are required to obtain a result similar to that of FIG. 5, and it is excellent for speeding up.

Further, according to the present invention, in order to perform a series of first to third processes of the packet header in a pipeline manner, the packet header is divided into the above three portions which need to be performed in sequence, Minimize use,
In addition, CPUs using the resources are divided so that the CPUs operate 100%, and the respective parts can be independently processed by allocating the respective CPUs. As a result, the optimal number of CPUs can be selected, and the CPU with the highest load is set
It can be used up to 0% or nearly 100%.

In order to process packet headers at high speed, it is necessary to perform these at high speed. Conventionally, one C
Although the PU performs the above three processes in order, if the same is performed by hardware, the pipeline process can be performed by separately performing the three processes.

FIG. 3 shows a conceptual example of the processing by such a pipeline configuration. The processing A, the processing B, and the processing C are completed in the same fixed time, and are set to a fixed time from the start to the end, and when a series of processing is required, the processing can be performed in the same fixed time. Process A, process B, and process C. After the process A is completed by the CPU 1, the process B is started by the CPU 2 and the next process A is started by the CPU 1, and the process B is completed by the CPU 2. The process in which the process C is started by the CPU 3 and the next process B is started by the CPU 2 is called a pipeline process.

There are various methods for performing program processing when the processing A to C does not end in the same fixed time, and three examples will be described with reference to FIG. Here, the description will be made with the CPU replaced with a sequencer. FIG.
(A) shows processing program A when the time of each processing is different.
When 41 is shorter than the processing program B42, since the flag corresponding to the processing program B42 in the register 43 is not set until the processing program B42 ends, the sequencer 1 that processes the processing program A41 is in a standby state, and the processing program B42 ends. Then, the flag of the register 43 is set, and the sequencer 1 processes the subsequent processing program A. In FIG. 4B, the processing program A4
1 is shorter than the processing program B42, the sequencer 1
Waits for a predetermined period of time after the processing program A41 ends, detects whether a flag corresponding to the processing program B42 of the register 43 is set, and if the flag is set, processes the next processing program A41. I do. On the other hand, if the flag is not set, a predetermined period of time is waited, and it is detected again whether the flag corresponding to the processing program B42 of the register 43 is set. That is,
By setting a certain period of time in the standby state, the load on the sequencer 1 is reduced. Further, in FIG. 4C, when the processing program A41 is shorter than the processing program B42, the sequencer 1 detects whether or not a flag corresponding to the processing program B42 in the register 43 is set at a predetermined constant clock number. In this case, the load on the sequencer can be further reduced by detecting the flag at every multiple of a predetermined fixed number of clocks.

[0027]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment> A first embodiment of the present invention comprises, as shown in FIG. 1, three general-purpose CPUs serving as first to third means and various registers. CPU
The first general-purpose CPU 101 named (pre-processing)
Header register group (simply called header register) 12
From the information of 0, the contents of a search key register group (simply called a search key register) 121 are generated.

CPU (search / learning engine)
The second general-purpose CPU 102 named “forwarding table 10
9 is searched, and a search result register group (simply called a search result register) 122 is generated based on the search result.

Further, a third general-purpose CPU 103 named CPU (post-processing) generates the contents of a queue buffer preparation register group (simply called a queue buffer preparation register) 123 from the information of the search result register 122.

The header register 120 and the queue buffer preparation register 123 need the number of reception interfaces, that is, the number N of packets arriving at the same time. Since the search result register 122 relates to the search of the forwarding table 109 having only one, the search result register 122 may be N or less.
To operate under the restriction that two general-purpose CPUs do not access any one register at the same time, 3
Is necessary.

The three search result registers 122 store the write and search /
Writing and post-processing general-purpose CPU 10 for learning engine 102
3 are used simultaneously. Three search key registers 121 are also prepared in order to control the search result register 122. However, search key register 1
21, the two are respectively pre-processing general-purpose C
It is used at the same time for writing of the PU 101 and reading of the search engine 102, and one of them is paused.

Hereinafter, three general-purpose CPUs will be described. In the processing per packet, the search / learning engine 102 takes a long time to search the forwarding table 109, and thus becomes the bottleneck most. Also,
In order to reduce this time as much as possible, processing for minimizing the number of searches is left to the pre-processing general-purpose CPU 101 and the post-processing general-purpose CPU 103.

General-purpose CPU 1 for each of pre-processing and post-processing
The processing of 01 and 103 will be described. Pre-processing general-purpose CPU 10
1 performs header analysis, determines the header format of the MAC packet, and, if necessary, performs the payload of the MAC packet, that is, performs the header analysis of the IP packet.
The payload of a MAC packet is not necessarily an IP packet. That is, if the MAC address is the MAC address of the router, the packet is processed as a layer L3 as an IP packet. Otherwise, it is not necessary to check whether the packet is an IP packet, and the layer L2 is processed. In the conventional technology, the MAC address is set to M
Whether it is an AC address or not is determined by the forwarding table 1
09 was searched. But this is the search engine 10
Since the load is 2, the preprocessing general-purpose CPU 101 makes the determination.

In addition, it is necessary to analyze the router destination in the judgment,
That is, when the processing of L3 needs to be performed, the analysis of the header of the IP packet is started. As for the IP header, a destination IP address is extracted and input to the search key register 121 as a search key. Information such as the reception port number and the VLAN-ID is stored in the search key register 12.
1 as well as the search result register 122. These information are stored in the queue buffer preparation register 1
This is because it is also necessary when writing to.

The post-processing general-purpose CPU 103 specifies a register having a number that matches the reception port number of the search result register 122, and specifies the search result input to the search result register 122 by the search engine 102 in the queue preparation register 123. To the specified format. For example, if the destination is multicast, the search engine 102
, A bit map is extracted from the search result register 122 and input to the search result register 122.
U103 analyzes the bitmap and turns on the bit.
/ Off is converted into an instruction sequence of sending a packet to an output port corresponding to the bit.

The search / learning engine 102 determines whether the search key input to the search key register 121 is L2 or L2.
Using the information indicating whether the processing is 3 or which processing should be performed, the corresponding forwarding table 109 is searched. If the search finds a match with the key, the information associated with the found key in the table is extracted. The information includes an output port number, an address field name to be changed at the time of output, an address used for the change, and the like.

As described above, by performing processing independently by three general-purpose CPUs, it is possible to exceed the limit of speeding up which is a problem when processing is performed by one general-purpose CPU. Further, it is not necessary to use four or more general-purpose CPUs, and three can sufficiently distribute processing.

In the above-described embodiment, a part of the processing requires the processing to be performed after the preprocessing. However, since the processing can be performed in an overlapping manner, the CPU shown in FIG. High-speed packet processing can be achieved.

<Second Embodiment> A second embodiment of the present invention has a configuration in which a sequencer is used instead of each general-purpose CPU in the first embodiment. Thereby, general purpose CP
The speed can be further increased as compared with the case where U is used. FIG. 6 shows an example of processing by the sequencer. The operation of the sequencer and the configuration of the sequencer are as shown in FIG. 2, and the operation according to this embodiment is the same as that of the first embodiment shown in FIG. The processing steps can be performed in a very short time by functional processing.

<Third Embodiment> A third embodiment of the present invention is different from the first or second embodiment in that each CP
U or each sequencer operates as a pipeline and has the following structure. FIG. 7 is a diagram showing a case where each sequencer operates as a pipeline.

Each sequencer 101, 102, 103
A fixed time (period) is determined so that the processing is completed in a fixed time. When starting the operation of the system, the cycle timer 201 supplies a cycle aligning clock from the cycle timer 201 so that a signal is output at the same timing.
By simultaneously inputting the values to 3, the start of the cycle is made the same. As a result, the processing in each sequencer can operate independently without considering the following means.
In FIG. 7, a general-purpose CPU can be used instead of the sequencer.

As a result, in the general-purpose CPU or the sequencer control, the procedure necessary for communication between the general-purpose CPUs can be deleted, or the procedure necessary for communication between the sequencers can be deleted. And speedup is further improved.

<Fourth Embodiment> A fourth embodiment of the present invention has the following structure as shown in FIG. 8 in the second embodiment of FIG.

Each of the register groups 120 to 123 has a first ready register which indicates whether there is data necessary for performing the process, that is, whether there is input data for the process. That is, each of the registers 120a to 120c, 121a to 121c, 12
2a to 122c and 123a to 123c have ready registers 301, 302, and 303, respectively. Further, each of the register groups 120 to 123 indicates whether or not a storage location for outputting the processing result can be used, that is, whether or not the result of the header processing of the previous packet has been used as an input by the following means. Each has a ready register. That is, each of the registers 120a to 120c, 121a to 121c, and 122a of each of the register groups 120 to 123.
122c and 123a to 123c have ready registers 401, 402 and 403, respectively.

The operation of the above structure will be described below.

For example, at the beginning of the process, the sequencer 102 firstly registers the first ready register 301 of the first register 121 a of the read-side register group (search key register group) 121 and the write-side register group (search result register group) 122. , The second ready register 401 of the register 122a is always read, and the first ready register 301 is read out.
Is “input data”, and only when the second ready register 401 is “write OK”, data is read from the register 121 a of the read-side register group 121, data is processed, and the write-side register group 122 is read. The data is written to the register 122a. Thereafter, “write OK” is set in the second ready register 401 of the register 121 a of the read-side register group 121, and “input data exists” is set in the first ready register 301 of the register 122 a of the write-side register group 122. .
Further, the register 121 of the read-side register group 121
"No input data" in the first ready register 301 of "a"
Is set, and the register 1 of the write-side register group 122 is set.
"Write inhibit" is set in the second ready register 401 of 22a.

On the other hand, when the first ready register 301 of the register 121a of the read-side register group 121 is "no input data", or when the write-side register group 12
When the second ready register 401 of the second register 122a is “write-protected”, the process is not started, and the first ready register 301 or the second ready register 4 is not started.
The wait state of only reading 01 is continued.

The two sequencers have at least three registers, and these three registers are used exclusively by the two sequencers. For example, sequencer 1
01 is one register 12 of the search key register group 121
1a, the sequencer 1
02 reads data from another register 121b of the search key register group 121, and the other register 121c of the search key register group 121 is inactive.

The exclusive operation will be further described with reference to FIG. 8 showing the operation of each register group and each sequencer.

Although a plurality of sequencers transfer data using a certain register, if writing and reading to the register occur at the same time, the validity of the data may be lost. Control is required. Hereinafter, the exclusive operation will be described.

For example, focusing on the operation of the search key register group 121, when the first register 121a of the search key register group 121 is used for writing in the sequencer 101, the second register of the search key register group 121 is used. Of the search key register group 121 are used for reading of the sequencer 102.
Is in a state where it is not accessed from anywhere, or a state where either of the sequencers 101 and 102 can be used.

After completing each process, the sequencers 101 and 102 use another register for the next process. That is, the second register 121b of the search key register group 121 is used for writing in the sequencer 101,
Third register 121c of search key register group 121
Is used for reading of the sequencer 102, and the first register 121a of the search key register group 121 is not accessed from anywhere, or the sequencer 10
It becomes a state where either one of 1, 102 can be used.

By performing such an operation, reading and writing of each register are performed exclusively, so that concern about the validity of data due to simultaneous writing and reading of the register is eliminated.

As described above, in the present embodiment, reliable pipeline control using handshake can be performed, or the period can be different for each means, and it is not necessary to match the start of the period. In the case of pipeline control, the processing can be completed in a shorter time than when all means need to be adjusted to the one having the longest cycle. In FIG. 8, it is also possible to use a general-purpose CPU instead of the sequencer in the configuration of the first embodiment.

<Fifth Embodiment> In the fourth embodiment of the present invention, each of the sequencers 101 to 103 has a first ready register of "no input data" or a second ready register of In the case of "write-inhibited", the wait state in which reading is always performed is set. However, in the fifth embodiment, reading is performed for a predetermined wait time, similarly to the operation described with reference to FIG. There was no weight state. This further simplifies the control, thereby speeding up the processing.

In the present embodiment, even if it is determined which processing program is to be executed within the current fixed time at the beginning of a predetermined fixed time, at the end of the fixed time, which processing program is to be executed within the next fixed time Whether to execute the processing program may be determined.

<Sixth Embodiment> The sixth embodiment of the present invention relates to the case where the processing time of the sequencer is not constant but becomes an integral multiple of a predetermined reference period in the fifth embodiment. is there.

For example, the sequencer 101 and the sequencer 1
02 is an integral multiple of a predetermined reference cycle, but if the processing times are different, the difference in processing time between the sequencer 101 and the sequencer 102 is also an integral multiple of the reference cycle. Therefore, in the present embodiment, the determined wait time in the fifth embodiment is set to an integral multiple of the reference cycle.

For example, a specific description will be given with reference to FIG. 4C. For example, when the reference cycle is 100 clocks,
After completion of the processing program A, the sequencer 1 reads the register every 100 clocks and detects the state of the flag of the register for the processing program B. Further, the state of the register is read out at the 400th clock which is an integral multiple of the 100th clock, instead of every 100th clock. If the flag is set, the processing of the next processing program A is started. This determines when the process does not need to start,
Since the control is simplified, the processing can be accelerated accordingly.

<Seventh Embodiment> A seventh embodiment of the present invention is different from the second embodiment in that, as shown in FIG.
A key register 121 and a search result register 122 are used as registers in which the first sequencer 101 accumulates processing results.
Are used, the second sequencer 102 uses the search result register 122 as a register for storing processing results, and the third sequencer 103 uses the queue preparation register 123 as a register for storing processing results. is there. That is, the search result register 122 is a register to which data is written from both the first sequencer 101 and the second sequencer 102. However, the search result register 122 is not accessed simultaneously by both of the sequencers 101 and 102. This is because, as described in the first embodiment, three registers 122 are prepared, and each of the three sequencers uses one to read or write one.

The first sequencer 101 writes information necessary for the search in the first register 121, and at the same time, stores the information (through information) required by the third sequencer 103 in the second register 122 as a packet header-capable portion. Extract from and write. The rest is the same as the first embodiment (in which the CPU is replaced with a sequencer).

This eliminates the need for the second sequencer 102, which is required in the first embodiment (in which the CPU is replaced with a sequencer), to move through information from the register 122 to the register 123, thereby eliminating the need for processing. Since the control is simplified, the processing can be accelerated accordingly.

In this embodiment, a general-purpose C is used instead of the sequencer.
A configuration using a PU is also possible. In addition, the sequencer 10
Although 1 indicates that the search / learning sequencer 102 directly operates on the search result register 122 managed by the search / learning sequencer 102, the search / learning sequencer 102 may directly write into the queue preparation register 123.

<Eighth Embodiment> As shown in FIGS. 11, 12, and 13, an eighth embodiment of the present invention is the same as that shown in FIGS.
In the processing performed by each sequencer in the embodiment, the processing is composed of a plurality of instructions. As shown in FIG. 12, execution of one instruction is performed by a general-purpose CPU such as addition, shift calculation, and comparison calculation. One instruction is composed of parallel or sequential combinations of the basic operations such as those used, or one instruction shifting the other data at the same time while comparing the result of adding one data. It consists of an operation and an instruction executed using the special operation. Both of these operations are configured by hardware.

The comparison of the number of processing clocks between the general-purpose CPU and the sequencer will be described below.

As shown in FIG. 11, in the general-purpose CPU 600, the instructions fetched from the instruction set 604 are:
Using the information in the register 603, a first basic operation 601
Alternatively, an operation result is obtained using the second basic operation 602, and the result is written into the register 603 again.

As shown in FIG. 12, in the sequencer 700 of the present embodiment, an instruction fetched from the instruction set 704 uses a special operation 701 or a basic operation 602 or a basic operation 601 by using information of a register 703. Is used to generate the operation result, and the result is written into the register 703 again.

For example, there is a register having two pieces of information, X and Y, and using these two, Z = 2 × X + 2 × Y
And writing Z into the register Z is performed. The basic operation is an addition 602 as shown in FIG.
And a shift 601, and the instructions are arranged using the basic operation as follows. Each instruction executes in one clock. Register X is shifted by one bit (first clock), register Y is shifted by one bit (second clock), register X and register Y are added (third clock), and the result is written to register Z. (4th clock).

On the other hand, as shown in FIG.
Is the bit shift 801 and the bit shift 802 and the addition 8
03, and Z = 2 × X + 2 × Y is obtained, and Z is written into the register Z813 in one clock (referred to as operation Z). Therefore, if an instruction is formed using a special operation, only the operation Z (first clock) is performed. As described above, since necessary operations are realized by hardware as special instructions, the processing speed can be increased. On the other hand, if special operations can be realized by combining basic operations, the same processing can be performed at a higher speed in hardware than a general-purpose CPU, so that the speed can be increased. Can be changed, giving you the flexibility to make design changes and add new processing while maintaining the benefits of speed.
It can be realized at low cost.

In the above embodiments, the header processing apparatus and the header processing method of the packet have been described. However, the present invention is not limited to the MAC header and the TCP / IP header, but can be applied to other header processing. In addition, general-purpose C
Although the number of PUs and sequencers has been described as three, the speed can be further increased by using a larger number of general-purpose CPUs or sequencers.

In each embodiment, the first to third means are replaced by the CPU 101 to 103 or the sequencer 101 to 1.
Although the example of the configuration in FIG. 03 is shown, the first to third means may be configured by one sequencer and two CPUs, two sequencers and one CPU, three independent sequencers, and three independent CPUs. Also, a sequencer that is shared (two of the first to third means are shared) and one sequencer or one CPU, shared C
It may be composed of a PU and one sequencer or one CPU. FIG. 9 is a conceptual block diagram of a system showing a case where one of the three CPUs in FIG. 1 is replaced with one sequencer.

[0073]

According to the present invention, header processing can be performed at low cost and at high speed using a general-purpose CPU up to a speed restricted by resources that become a bottleneck. Also, by using a sequencer to implement packet header processing with a programmable hardware logic circuit, design changes and future functions can be realized at low cost while maintaining high speed. Further, by operating a plurality of processes as a pipeline, header processing, for example, routing processing such as searching for the destination of the next router and inserting destination data into a packet can be executed at high speed.

[Brief description of the drawings]

FIG. 1 is a conceptual block diagram of a system according to an embodiment of the present invention.

FIG. 2 is a conceptual block diagram of a header processing system according to the present invention.

FIG. 3 is a conceptual block diagram of a header processing system according to the present invention.

FIG. 4 is a conceptual block diagram of a header processing system according to the present invention.

FIG. 5 is a conceptual block diagram of a header processing system according to the present invention.

FIG. 6 is a conceptual block diagram of a system according to an embodiment of the present invention.

FIG. 7 is a conceptual block diagram of a system according to an embodiment of the present invention.

FIG. 8 is a conceptual block diagram of a system process according to an embodiment of the present invention.

FIG. 9 is a conceptual block diagram of a system showing a case where one CPU is replaced with one sequencer in FIG. 5;

FIG. 10 is a conceptual block diagram of a system according to an embodiment of the present invention.

FIG. 11 is a conceptual block diagram of a system according to an embodiment of the present invention.

FIG. 12 is a conceptual block diagram of a system according to an embodiment of the present invention.

FIG. 13 is a conceptual block diagram of a system according to an embodiment of the present invention.

FIG. 14: 80 of DIX regulation and IEEE 802.3 regulation
2.1 Q format.

[Explanation of symbols]

 101 Pre-processing sequencer 102 Search / learning engine 103 Post-processing sequencer 120 Header register 121 Search key register 122 Search result register 123 Queue preparation register 201 Synchronous timer 301, 302, 303 Ready register 401, 402, 403 Ready register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 29/02 H04L 12/56

Claims (15)

(57) [Claims] 1. A first method of extracting data of each field of a protocol header from a part of a packet including a header extracted from the packet and inputting the data to a designated storage location
Means for performing a search using the data at the specified storage location as a search key, and outputting the contents of a table entry matching the search key; and output means of the second means and from a storage location of the data, and a third means for creating the attribute information of the destination and the header update information of the packet, have a, the first to third means, respectively predetermined et al
At the beginning or end of the fixed time
Or which processing program to execute within the next fixed time
Header processing device, characterized in that
Place. 2. A packet including a header extracted from a packet.
Each field of the protocol header from a portion of the
The first to extract the data of the data and input it to the specified storage location
And a search using the data at the designated storage location as a search key.
And the contents of the table entry that matches the search key are
Second means for outputting, output contents of the second means and data of the storage location,
The destination information of the packet and the attribute information of the header update information
The has a third means for creating the said first to third means, respectively predetermined et al
Processing ends at an integral multiple of the number of instructions
Confirms completion or start of processing of other means at the start
Terminate or open in at least one other means.
If the start cannot be confirmed, execution of the instruction is suspended,
Wait for all means to end or start processing.
And a header processing device. 3. A packet including a header extracted from a packet.
Each field of the protocol header from a portion of the
The first to extract the data of the data and input it to the specified storage location
And a search using the data at the designated storage location as a search key.
Done, the contents of the table entry that one Itasu to the search key
Second means for outputting, output contents of the second means and data of the storage location,
The destination information of the packet and the attribute information of the header update information
A third means for creating a a, as a storage location in said first means, one shared section
It has a minute and two separate parts, and the common part is part or
Converts all the field data into the second means and the third
Used as a storage location that is shared by
The individual parts have the same data in each individual part.
And, each of the individual parts, the second means,
Header processing characterized by being used independently by the third means
apparatus. 4. A header processing apparatus according to claim 1, wherein the first through third means, one of the sequencer and two CPU, two sequencers and one CPU, 3 A header processing device comprising one of three sequencers and three CPUs. 5. The header processing apparatus according to claim 1, wherein the first through third means, sequencer and one sequencer or a C shared
A header processing device comprising a PU, a shared CPU and one sequencer or one CPU. In the header processing apparatus according to any one of the claims 6] claims 1-5, header processing apparatus characterized by comprising: means for pipelining respectively the first to third means. 7. A header processing apparatus according to claim 6, header processing, characterized in that for transferring the control in any of the first through third means for the pipeline processing using a handshake apparatus. 8. A header processing apparatus according to any one of claims 4-7, as a sequencer instruction in the first means, from the header possibility moiety, MAC (Me
dia Access Control) MAC address of packet header
DIX standard and IEEE standard 80
2.3 Two standard formats and 80
2.1 Whether the virtual LAN identifier specified in Q is attached
And extract the four types of MAC formats.
If necessary, I as the payload of the MAC packet
It has a first instruction set consisting of a special operation for extracting P packets and a second instruction set consisting of a basic operation for extracting arbitrary plural bits, and has a first instruction set and a second instruction set. A header processing device wherein instructions are processed by respective hardware. 9. The header processing apparatus according to claim 4 , wherein the instruction of the sequencer in the second means is a search data input to a table and a register of a search result from the table. A first instruction set consisting of a special operation for accumulating data and a second instruction consisting of a basic operation for moving arbitrary plural bits from register to register
A header processing apparatus, comprising: a first instruction set and a second instruction set, wherein instructions of the first instruction set and the second instruction set are respectively processed by unique hardware. 10. The header processing device according to claim 4 , wherein the sequencer instruction in said third means comprises a special operation for generating an in-device packet header from a search result output. A first instruction set and a second instruction set consisting of basic operations for moving arbitrary plural bits from a register to a register, wherein the instructions of the first instruction set and the instructions of the second instruction set are respectively unique. A header processing device characterized by processing by hardware. 11. A first step of extracting data of each field of a protocol header from a part of a packet including a header extracted from the packet and inputting the data to a designated storage location, A second procedure of performing a search using data as a search key and outputting the contents of a table entry matching the search key; and transmitting the packet from the output contents of the second procedure and the data of the storage location. possess a third step in creating the attribute information of the previous and the header update information, and the first to third steps in each predetermined et al
At the beginning or end of the fixed time
Or which processing program to execute within the next fixed time
Header processing method that determines whether to execute. 12. The header processing method according to claim 11 , wherein the first to third procedures include one sequencer and two CPUs, two sequencers and one CPU, three sequencers, three CPUs, A header processing method characterized by being performed using any one of the following. 13. The header processing method according to claim 11 , wherein the first to third procedures are performed by a shared sequencer and one sequencer or one CPU, and a shared CPU and one sequencer or one sequencer. A header processing method characterized by being executed using any one of a CPU. 14. The header processing method according to claim 11 , wherein each of the first to third procedures is performed by pipeline processing. 15. The header processing method according to claim 14 , wherein said pipeline processing is performed by said first to third headers.
Wherein the control is passed using a handshake in any one of the above procedures.